DesigningSystemsonFPGAs

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DocumentVersion1.2,April2008 Software,documentationandrelatedmaterials: Copyright2008AltiumLimited. Allrightsreserved.Youarepermittedtoprintthisdocumentprovidedthat(1) theuseofsuchisforpersonaluseonlyandwillnotbecopiedorpostedon anynetworkcomputerorbroadcastinanymedia,and(2)nomodificationof thedocumentismade.Unauthorizedduplication,inwholeorpart,ofthis documentbyanymeans,mechanicalorelectronic,includingtranslationinto anotherlanguage,exceptforbriefexcerptsinpublishedreviews,isprohibited withouttheexpresswrittenpermissionofAltiumLimited.Unauthorized duplicationofthisworkmayalsobeprohibitedbylocalstatute.Violatorsmay besubjecttobothcriminalandcivilpenalties,includingfinesand/or imprisonment. Altium,AltiumDesigner,BoardInsight,CAMtastic,CircuitStudio,Design Explorer,DXP,LiveDesign,NanoBoard,NanoTalk,Nexar,nVisage,PCAD, Protel,SimCode,Situs,TASKING,andTopologicalAutoroutingandtheir respectivelogosaretrademarksorregisteredtrademarksofAltiumLimitedor itssubsidiaries. Microsoft,MicrosoftWindowsandMicrosoftAccessareregisteredtrademarks ofMicrosoftCorporation.OrCAD,OrCADCapture,OrCADLayoutand SPECCTRAareregisteredtrademarksofCadenceDesignSystemsInc. AutoCADisaregisteredtrademarkofAutoDeskInc.HPGLisaregistered trademarkofHewlettPackardCorporation.PostScriptisaregistered trademarkofAdobeSystems,Inc.Allotherregisteredorunregistered trademarksreferencedhereinarethepropertyoftheirrespectiveownersand notrademarkrightstothesameareclaimed.

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DesigningaSystemtoDisplayVideo ..................................................................15 1.1 Thenutsandboltsofcapturingvideo..........................................................15 1.2 ThenutsandboltsofDisplayingvideoonatouchscreen............................16 1.3 Ahighlevelviewofoursystem ...................................................................16 Utilizingmicroprocessorsoftcores......................................................................27 2.1 Howsoftisasoftcore?................................................................................27 2.2 UsingasoftcoreinanFPGAschematic ......................................................28 2.3 Accessingsoftcoredatasheets....................................................................28 2.4 TheTSK3000Processor .............................................................................28 2.5 Exercise1PlacingasoftcoreontoanFPGAschematic............................29 2.6 ConfiguringtheTSK3000processor............................................................29 2.7 Exercise2ConfiguringtheTSK3000AProcessor ...................................211 WishboneInterconnectionArchitecture ............................................................312 3.1 Wishbonecompatiblecores ......................................................................312 3.2 Wishboneinterfacesignaldescriptions......................................................313 3.3 Pinnamingconventionsforwishbonesignalpins......................................315 PlacingtheFPGAPeripherals ............................................................................417 4.1 Exercise3Placingtheperipherals .........................................................417 BusInterconnectivityandArbitration ................................................................520 5.1 WishboneInterconnectComponentWB_INTERCON................................520 5.2 ConfiguringtheWishboneInterconnectcomponent...................................521 5.3 Exercise4ConnectingourPeripherals...................................................524 5.4 Managingmemoryaccess ........................................................................525 5.5 Arbitrationofmultiplemasterssharingasingleslave.................................525 5.6 WishboneDualandMultiMasterdevices................................................526 5.7 Configuringthewishbonemulti mastercomponent...................................527 5.8 Exercise5DefiningourMultiMasterComponents..................................530 InterfacingtoExternalMemory ..........................................................................631 6.1 ConfiguringtheSRAMController ..............................................................631 6.2 TheSharedMemoryController .................................................................633 6.3 ConfiguringtheSharedMemoryController................................................634 6.4 Exercise6Placingandconfiguringmemorycontrollers ..........................636 6.5 Exercise7Multiplememoriesasslaves .................................................637 6.6 Exercise8PlacingthePortPlugInComponents....................................638 6.7 Exercise10 WiringUpYourFPGADesign .............................................640 ConfiguringProcessorMemory .........................................................................742 7.1 Dividingtheprocessormemory .................................................................743 7.2 Exercise11Configuringtheprocessormemory......................................745 7.3 Configuringprocessorperipherals.............................................................746 7.4 Exercise12Specifyingprocessorperipherals.........................................747 FinalizingtheDesign,CompilingandResolvingErrors....................................848 CreatingEmbeddedSystemsonFPGAs...........................................................949 9.1 Exercise13EditorBasics.......................................................................949 9.2 TheTASKINGtoolchain...........................................................................953 9.3 TheBuildflow ...........................................................................................953 9.4 TargetingtheProject.................................................................................954 9.5 Projectoptions..........................................................................................954 9.6 AttachinganembeddedprojecttoanFPGAproject ..................................966 9.7 Exercise13Linkingprojects...................................................................968 9.8 Exercise14Buildingourdesign .............................................................968 9.9 Exercise15UpdatingoursoftwareLive..................................................970 UpdatingtheDesigntoDisplayVideo ............................................................. 1071 10.1 DefiningSections.................................................................................... 1071 10.2 Exercise16UpdatingoursoftwareLive................................................ 1072

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10.3 Exercise17UpdatingourSoftwaretoCaptureVideo ........................... 1073 10.4 UtilizingtheVirtualInstruments ............................................................... 1074 10.5 Usinginstrumentstocontrolourdesign................................................... 1074 10.6 Exercise18UpdatingtheWishbonePortIO......................................... 1075 10.7 Exercise19AddingtheVirtualInstruments .......................................... 1076 10.8 Exercise20Rebuildingtheprojectwithinstruments .............................. 1078 10.9 Updatingourembeddedprojecttousetheinstruments ........................... 1078 10.10 Exercise21AddingAdditionalSourceFiles.......................................... 1078 10.11 Exercise22Updatingmain.c................................................................ 1078 10.12 Exercise23Controllingourdesignwithinstruments ............................. 1079 RealtimeDebuggingofaProcessor ............................................................... 1181 11.1 OnChipDebugging ................................................................................ 1181 11.2 Awordaboutsimulation.......................................................................... 1181 11.3 Embeddedcontrolpanels........................................................................ 1183 11.4 InstrumentRackNexusDebugger........................................................ 1189 CtoHardware.................................................................................................... 1292 12.1 WhatarethebenefitsoftheCtoHardwareCompiler?............................ 1292 12.2 UsingtheCHCCompiler......................................................................... 1292 12.3 ImplementingCtoHardwareinourDesign ............................................. 1293 12.4 Exercise24MakingRoomforCtoHardware ....................................... 1293 12.5 Exercise25AddingtheApplicationSpecificProcessor......................... 1294 12.6 Exercise26GivingtheASPAccesstoMemory(part1)........................ 1295 12.7 Exercise27GivingtheASPAccesstoMemory(part2)........................ 1297 12.8 ConfiguringtheASP ............................................................................. 12101 12.9 Exercise28AcceleratingourperformancewithASP .......................... 12103 OpenBus.......................................................................................................... 13106 13.1 CreatinganOpenBusversionofourdesign .......................................... 13106 13.2 Exercise29BeginninganFPGAProjectUsingOpenBus ................ 13106 13.3 OpenBusDevices ................................................................................. 13107 13.4 Exercise30PlacingOpenBusComponents(part1) .......................... 13107 13.5 Exercise31UsinganInterconnect ..................................................... 13111 13.6 Exercise32LinkingOpenBusPorts ................................................... 13114 13.7 Exercise33Configuringourprocessorunderopenbus...................... 13115 13.8 Exercise34ConfiguringtheGPIOComponent................................... 13115 13.9 Exercise35FinalizingtheInterconnectComponent ........................... 13116 13.10 DefiningtheMemorySideofourSystem............................................... 13117 13.11 Exercise36AddingtheRemainingComponents ................................ 13117 13.12 Exercise37CompletingtheConnectivity............................................ 13118 13.13 Exercise38ConfiguringtheSRAMControllers................................... 13118 13.14 Exercise39ConfiguringtheArbiters .................................................. 13120 13.15 Exercise40ConfiguringtheInterconnects.......................................... 13121 13.16 FinalizingtheOpenBusPortionoftheDesign........................................ 13121 13.17 Exercise41ConfiguringtheProcessorMemory ................................. 13122 13.18 Exercise42CreatingasheetsymbolfromanOpenBusDocument .... 13123 13.19 Exercise43LinkinganEmbeddedProjecttoanOpenBusDesign...... 13124 13.20 Exercise44ProcessinganOpenBusDesign...................................... 13125 Review ............................................................................................................. 14126

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1 DesigningaSystemtoDisplayVideo
Thisnextsectionofthecourseisdesignedtotakeyouthroughtheprocessofdevelopinga completesoftprocessorbasedsystemonanFPGA.Toaccomplishthis,wewillfollowa singledesignthroughavarietyofdifferentstagesanddifferentcapturemethods.Thedesign wevechosenisasimplevideodisplaysystemcapableofcapturingcompositevideoand displayingthevideoonatouchscreen,withoptionstoscaleandrotatetheimage. CentraltoourdesignwillbetheTSK3000A,aderivativeoftheTSK3000familyofsoft microprocessorssuppliedwithAltiumDesigner.SupportingtheTSK3000Awillbeahostof peripheralsthatwillsupplythemeanswithwhichtobothcaptureanddisplayourvideoonthe touchscreenlocatedontheDesktopNanoBoard.

1.1 Thenutsandboltsofcapturingvideo
TheDesktopNanoBoardsperipheralboardPB01supportstheconnectionofexternalPALor NTSCanalogvideosignals.BothCompositeVideoandSVideoinputsaresupported. ConnectionofaCompositeVideosignalismadethroughtwoRCAphonojacks, designatedJ5andJ6,whichcaterfortheLuma(luminanceorintensity)andChroma (chrominanceorcolor)componentsofthesignalrespectively. Theanalogvideoinputisconvertedintoan8bitdigitalYCbCr4:2:2componentvideothrough theuseofaTVP5150AM1videodecoderdevicefromTexasInstruments. Thedecoderprovidesa9bitADC,withsamplingcarriedoutinaccordancewiththeITUR BT.601recommendation.Thisrecommendationdefinestheschemeforencodinginterlaced analogvideosignalsforboth625and525linesystemsindigitalform. Theconverteddigitalvideostreamcanbeoutputinoneoftwoformats: 8bitITURBT.656interfacewithembeddedsynchronization 8bit4:2:2YCbCr,withdiscretesynchronizationsignals BydefaulttheTVP5150AM1isconfiguredtooutputdigitalvideointheITURBT.656format andthisistheformatexpectedbyaBT656ControllerusedwithinandFPGAdesign.

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Inourdesign,wewillusetheBT656ControllercoresuppliedwithAltiumDesignertofetch thevideofromthevideodecoderandsupplythattotherestofoursystem. TheBT656ControllertakesasitsinputsfromtheTVP5150AM1: VIDIN_DATA[7..0]theITURBT.656compliantvideostream VIDIN_PCLKthepixelclock,fixedat27MHzandusedtoclocktheoutputvideo datastream VIDIN_INTERQ_GPLCusedtoindicatetheverticalblankingintervalofthevideo datastream ThevideodecoderiscontrolledbyaprocessorwithintheFPGAdesignovertheI2Cbus. Thedecoder(anI2Cslave)iscontrolledthroughanintermediateI2Ccontroller(theI2C master,alsoresidentwithintheFPGAdesign).

1.2 ThenutsandboltsofDisplayingvideoonatouchscreen
TheDesktopNanoBoardprovideshighqualitycolordisplaythroughaHitachi TX09D50VM1CAATFT(ThinFilmTransistor)LCDpanel.Thepanelalsofeaturesananalog resistivetouchscreen.Fromauserperspectiveyoucaneitheroutputstraightforward graphicstothepanel,orprovideamoresophisticatedlevelofinteractioninvolvinginputto yourFPGAdesignfromthetouchscreen. The3.5panelfeaturesaTransmissiveColorTFTLCD,witharesolutionof240(W)by 340(H).Thedisplayisbasedonanactivematrixandbacklightforthepanelsisprovided through6LEDs.Thepanelisfixedtouse16bpp(bitsperpixel)display,withbit0fromboth RedandBlueintensityinputstiedtoGND.Thisresultsinatotalof65536colorsbeing availablefordisplay. Inourdesign,wewillusetheWB_VGAConfigurableWishboneDisplayDriversupplied withAltiumDesignertofetch16bppformatteddatafromexternalmemory,processit,and displayitontheconnectedTFTLCDpanel.Allofthecontrolsignalsaregeneratedincore, usinganintegratedTFTTimingControllerunit.

1.3 Ahighlevelviewofoursystem
Ithelpstohaveahighlevelunderstandingofhowoursystemwillgotogetherbeforegetting started.Belowisablockdiagramthatexplainstheflowofdataintoandoutofoursystem.
AnalogVideoInput

ADC

TVP5150AM1

BT656Controller

TSK3000

VGATFTController

Figure1.Simplifiedflowdiagramofoursystem.

Figure1showsasimplifiedflowdiagramofoursystem.Onthelefthandsideofthediagram youcanseetheanalogvideoinput.ThisisconvertedtodigitalbytheTVP5150AM1and outputasBT656totheFPGAbasedBT656decoder.Thiswillthenbeprocessedbythe TSK3000andoutputtothetouchscreendisplayusinganFPGAbasedVGAcontroller.

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2 Utilizingmicroprocessorsoftcores
InthissectionwewillbegintoexploreutilizingsoftmicroprocessorcoresonFPGAs.

2.1 Howsoftisasoftcore?
AltiumDesignercomesbundledwithanumberofpreverified,presynthesized microprocessorsoftcoresthatcanbeincorporatedintoanFPGAproject.Theseprocessors arelabeledassoftbecausetheyareimplementedasadownloadablecore(utilizing resourcesontheFPGA)thatrunsfromanFPGAdeviceratherthanasahardphysical microprocessorinitsowndistinctpackage.

Figure2.PictorialrepresentationofasoftcoreloadedontoanFPGAdevice.

OneofthefundamentaldifferencesbetweenFPGAbasedmicroprocessorcores(suchas thosebundledwithAltiumDesigner)andhardprocessorsistherelationshipoftheperipherals totheprocessoritself.Intraditionalhardprocessors,asetofstandardperipheralswillcome onchipandarefixed(i.e.cannotbechanged).Anexamplemightbean8051withanon chipHighSpeedUSBinterface.FPGAbasedprocessorsontheotherhand,generally includeonlytheCPUenablingtheengineertopackwhateverperipheralsmightberequired aroundtheprocessor.Thisiscentraltotheincreasedflexibility/scalabilityofFPGAbased systems.Systemscanbemodifiedinthesoftdomaintoaddandremoveperipheralsasa designchanges,allowingmoreflexibilityatthedesignstagetomakerealtimemodifications toasystemthusnotrequiringtheengineertolockinthehardwareupfront.

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2.2 UsingasoftcoreinanFPGAschematic
BuildinganFPGAprojectthatincorporatesasoftcoreisnodifferentfrombuildinganyother FPGAprojectyousimplyselectcomponentsfromalibraryandplacethemontoyour schematic.TheFPGAsoftcorescanbeaccessedfromtheintegratedlibraryFPGA Processors.IntLib

Figure3.FPGAProcessors.IntLiblibrarycontentswithpopupHelp

2.3 Accessingsoftcoredatasheets
Detaileddatasheetscanbeaccessedforeachdevicebyhighlightingthedeviceand selectingtheF1keyorbyrightclickingthedeviceintheLibrariespanelandselectingShow Helpfor<DeviceName>asseeninFigure3.

2.4 TheTSK3000Processor
CentraltoourdesignistheTSK3000Acore. TheTSK3000Aisaconfigurable32bit, Wishbonecompatible,RISCprocessorcore.Mostinstructionsare32bitswideandexecute inasingleclockcycle.Inadditiontofastregisteraccess,theTSK3000Afeaturesauser definable(from1KBytesupto1MBytes)amountofzerowaitstateblockRAM,withtrue dualportaccess.

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TheTSK3000Aalsofeatures: FPGAdeviceindependentimplementation 5stagepipelinedRISCprocessor 32x32to64bithardwaremultiplier,signedandunsigned 32x32bithardwaredivider 32bitsinglecyclebarrelshifter 32inputinterrupts,individuallyconfigurabletobeleveloredgesensitiveandusedin oneoftwomodes: StandardModeallinterruptsjumptothesame,configurablebasevector VectoredModeproviding32vectoredpriorityinterrupts,eachjumpingtoa separateinterruptvector InternalHarvardarchitecturewithsimplifiedexternalmemoryaccess 4GByteaddressspace WishboneI/Oandmemoryportsforsimplifiedperipheralconnection FullViperbasedsoftwaredevelopmenttoolchainCcompiler/assembler/source leveldebugger/profiler CcodecompatiblewithotherAltiumDesigner8bitand32bitWishbonecompliant processorcores,foreasydesignmigration

2.5 Exercise1PlacingasoftcoreontoanFPGAschematic
InthisexercisewewillcreateanewFPGAprojectandaddtheTSK3000Atoanew,blank schematicdocument. 1. CreateanewFPGAprojectandanewschematicsheet 2. AdjustthesheettoCsizewithintheDocumentOptionsdialoglocatedunder DesignDocumentOptionsorbydoubleclickingintheborderareaaroundthe outsideoftheschematicdocument. 3. SavetheFPGAprojectusingFileSaveProjectAsandyouwillbepromptedto saveboththeschematicandtheFPGAproject.Namethefiles CHC_Image_Rotation.SchDocandCHC_Image_Rotation.PrjFpgrespectively. 4. SelecttheTSK3000AprocessorfromtheFPGAProcessors.IntLiblibraryandplaceit ontotheschematic. 5. AnnotatethecomponentU2andsaveyourwork.

2.6 ConfiguringtheTSK3000processor
TheConfigure(32bitProcessors)dialog(Figure4)isaccessiblebyrightclickingthe processorintheschematicandselectingConfigure...oralternativelybyselectingthe Configurebuttoninthecomponentpropertiesdialog.

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Figure4.Processorconfigurationdialog

Severaloptionsareavailablewhenconfiguringtheprocessor: InternalProcessorMemory ThisisauserconfigurablefeatureoftheTSK3000A.UtilizingdualportFPGABlock RAM,thisareagenerallycontainsthebootportionofyourapplicationaswellas interruptandexceptionhandlers. Thismemoryisgenerallythefastestandyouwillwanttoconsiderplacinganyspeed criticalpartsofyourapplicationinthismemoryspace.Thismemoryishowever limitedtotheamountofDualPortBlockRAMavailableintheFPGAandthusthe amountyouspecifyneedstobebalancedforthedeviceselected. TheMultiply/DivideUnit(MDU) Fundamentallytherearetwoapproachestomanagingmultiply/divideinstructions, onebeingtoimplementtheminhardwareusingFPGAresourcestocreatethe multiply(MULT,MULTU)anddivide(DIV,DIVU)hardwareinstructions,or alternativelyimplementingtheminsoftwaresuchthattheseinstructionsareemulated bytheCCompiler. Thisisatradeoffofspeedversussize.TheHardwareMDUwillbefasterasthese instructionshavededicatedhardwareresources,howeveritwillconsumeFPGA resourcesandthusthespaceavailableintheFPGAwillbereduced. OnChipDebugSystem TheTSK3000includesanoptionalonchipdebugging(OCD)system. TheOCD systemcanbeusedtodebugaprocessorasitexecutesinsystem,inrealtime.This includesoptionsto: o Reset,Go,Haltprocessorcontrol o Singleormultistepdebugging o Readwriteaccessforinternalprocessorregisters o ReadwriteaccessformemoryandI/Ospace o Unlimitedsoftwarebreakpoints Theonchipdebuggingsystemcanberemovedatanytimewhichwillthenfreeup theFPGAresourcesitrequires.Nochangeswillberequiredinthesourceembedded

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applicationwhenswitchingbetweenOCDandnonOCDversionsofthe microprocessor. BreakpointsonReset TheTSK3000Ahasthefeaturetoenabletheapplicationtoruntoabreakpointaftera hardreset(RST_Ipingoeshigh).Thisoptionisuserconfigurableandcanbe selecteddependingontheneedsofthetargetapplication.

2.7 Exercise2ConfiguringtheTSK3000AProcessor
HavingplacedtheTSK3000Ainourdesign,wenowneedtoconfigureitforourapplication. 1. RightclicktheTSK3000Aintheschematicandselect ConfigureU2(TSK3000A). ThiswilllaunchtheConfigure(32bitProcessors)dialog. 2. SettheInternalProcessorMemoryoptionto32KBytes(8Kx32BitWords) 3. SettheMultiply/DivideUnit(MDU)optiontoHardwareMDU 4. SettheOnChipDebugSystem optiontoIncludeJTAGBasedOnChipDebug System 6. SettheBreakpointsonResetoptiontoDisableBreakpointsonHardReset

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3 WishboneInterconnectionArchitecture
AltiumDesignermakesextensiveuseoftheWishboneInterconnectionArchitecture.Acopy oftheWishbonestandardisavailablefromwww.opencores.orgorlocatedwithinthehelp systeminAltiumDesigner.Simplystated,Wishboneisanopensourcestandardthat specifiestheinterfacetoIPcores,thusmakingiteasiertoconnectblocksofIntellectual PropertycorestogetherinanFPGA/ASICdesign.TheintentbeingthatifallIPblockshave astandardinterface,blocksofIPwillthenbemoreeasilyreusable,moreeasily interchangeable,andthetimespentnegotiatingtransactionsbetweencoreswillbereduced oreliminated. WhatWishboneIsNot WishbonedoesnotspecifythebehaviororarchitectureoftheIPitself.Instead,Wishboneis intendedtobeGeneralPurposewithitsemphasisondataexchangeandnotacores function. Likediscretemicroprocessorswhichincludeanaddressbus,databus,andhandshaking lines,theWishboneInterconnectionArchitecturedefinesthesignalsrequiredtointerfaceIP blockstooneanotherandhowtheyoperate.Wishbonedoesnotimplytheelectrical characteristicsoftheinterconnectionsbutisintentionallyfocusedonthelogical implementationofacommonmechanismfortheinteractionbetweenIP.

3.1 Wishbonecompatiblecores
WiththeTSK3000Aconfigured,thenextstageinourprojectistospecifytheperipheralcores requiredandconnectthemtotheprocessor.ThereisarangeofWishbonecompatible peripheralcoresprovidedintheFPGAPeripherals.IntLiblibraryanditsthisWishbone compatibilitythatmakestheinterconnectionofthesecomponentsfastandeasy. Forexample,inthefigurebelow,noticetheuniformityofthevariousinterfacesofthesetwo components.
BT656Controller
VID_DATA[7..0] PCLK VBLK WBS_STB_I WBS_CYC_I WBS_ACK_O WBS_ADR_I[2..0] WBS_DAT_O[31..0] WBS_DAT_I[31..0] WBS_SEL_I[3..0] WBS_WE_I CLK_I RST_I INT_O[1..0] WBM_STB_O WBM_CYC_O WBM_ACK_I WBM_ADR_O[31..0] WBM_DAT_O[31..0] WBM_SEL_O[3..0] WBM_WE_O BT656 TSK3000A

TSK3000A32BitRISCProcessor
IO_STB_O IO_CYC_O IO_ACK_I IO_ADR_O[23..0] IO_DAT_I[31..0] IO_DAT_O[31..0] IO_SEL_O[3..0] IO_WE_O IO_CLK_O IO_RST_O INT_I[31..0] ME_STB_O ME_CYC_O ME_ACK_I ME_ADR_O[31..0] ME_DAT_I[31..0] ME_DAT_O[31..0] ME_SEL_O[3..0] ME_WE_O ME_CLK_O ME_RST_O

CurrentConfiguration
MDU:Installed DebugHardware:Installed InternalMemory:32KB

CLK_I RST_I

Figure5.AlookattheWishbonesignalpinsonschematicsymbols

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ThepinnamesarequitesimilarastheyarederivedfromtheWishbonestandardandtheir namesreferencetheWishboneinterfacesignalnames.Tofurthersimplifytheinterfacingof IPcomponentstooneanother,WishbonerequiresthatallWishbonesignalsareactivehigh. Thismakesrepresentingthesignalsinschematiccapturetoolseasierasiteliminatesthe challengeofuniformlyrepresentingactivelowlogic(graphically)inaschematicdesign(i.e. overbar,hashmarks,slashes,etc.)

3.2 Wishboneinterfacesignaldescriptions
ThewishbonesignalscanbegroupedaseitherMaster,Slave,commontobothSlaveand Master,orSYSCONmodulesignals(amoduleisSYSCONifitdrivesthesystemclock CLK_OandtheresetRST_Osignals). ThefollowingtableisalistofWishbonesignalsused inAltiumDesigner.ForacompletelistofWishbonesignalsandsignaldescriptions,referto theWishbonespecificationfoundat www.opencores.orgorinthehelpsystem.
WishboneSYSCONSignals

SignalName CLK_O

SignalDescription External(system)clocksignal(identicalto CLK_I)madeavailableforconnectingtothe CLK_Iinputofaslavedevice Resetsignalavailabletoconnecttoaslave device

RST_O

WishboneCommonSignals(MasterandSlave)

SignalName CLK_I DAT_I[x..y] DAT_O[x..y] RST_I[x..y]

WishboneMasterSignals

SignalDescription External(system)clocksignal Datainputarrayfromanexternaldevicesuchas memory.Maximumwidth64bits. Dataoutputarraytoanexternaldevicesuchas memory.Maximumwidth64bits. External(system)resetsignal

SignalName ACK_I

SignalDescription StandardWishboneacknowledgementsignal usedtoacknowledgethecompletionofa requestedaction. StandardWishboneaddressbus,usedtoselect anaddressinaconnectedWishboneslave deviceforwritingto/readingfrom. Cyclesignal.Whenasserted,indicatesthestart ofavalidWishbonebuscycle.Thissignal remainsasserteduntiltheendofthebuscycle, wheresuchacyclecanincludemultipledata transfers Errorinputsignal.Usedtoindicatetheabnormal terminationofacycle.

ADR_O[x..y]

CYC_O

ERR_I

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RTY_I

Retryinputsignal.InformstheWishboneMaster interfacethattheWishboneSlaveisnotreadyto sendorreceivedataatthistimeandthedata exchangeshouldberetried.

SEL_O[x..y]

Selectoutputsignal.Usedtoindicatewhere dataisplacedontheDAT_OlineduringaWrite cycleandfromwheredataisaccessedonthe DAT_IlineduringaReadcycle.Dataportshave bothawidthandagranularity.Forexamplea 32bitwidedataportwith8bitgranularitywould allowdatatransfersof816or32bits.The Selectbitsallowtargetingofeachofthebit rangeswith0correspondingtothelowestrange andincrementingfromthere. Strobesignal.Whenasserted,indicatesthe startofavalidWishbonedatatransfercycle. Writeenablesignal.Usedtoindicatewhether thelocalbusisaReadorWritecycle. 0=Read 1=Write

STB_O WE_O

WishboneSlaveSignals

SignalName ACK_O

SignalDescription StandardWishbonedeviceacknowledgement signal.Whenthissignalgoeshigh,the WishboneSlavehasfinishedexecutionofthe requestedactionandthecurrentbuscycleis terminated. StandardWishboneaddressbus,usedtoselect aninternalregisteroftheWishboneslavedevice forwritingto/readingfrom. Cyclesignal.Whenasserted,indicatesthestart ofavalidWishbonecycle Erroroutputsignal.Usedtoindicatethe abnormalterminationofacycle. Retryoutputsignal.InformstheWishbone MasterinterfacethattheWishboneSlaveisnot readytosendorreceivedataatthistimeandthe dataexchangeshouldberetried. Selectinputsignal.Usedtoindicatewheredata isplacedontheDAT_OlineduringaReadcycle andfromwheredataisaccessedontheDAT_I lineduringaWritecycle.Dataportshavebotha widthandagranularity.Forexamplea32bit widedataportwith8bitgranularitywouldallow datatransfersof816or32bits.TheSelect bitsallowtargetingofeachofthebitrangeswith 0correspondingtothelowestrangeand incrementingfromthere.

ADR_I[x..y]

CYC_I ERR_O RTY_O

SEL_I[x..y]

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STB_I WE_I

Strobesignal.Whenasserted,indicatesthestart ofavalidWishbonedatatransfercycle. Writeenablesignal.Usedtoindicatewhetherthe currentlocalbuscycleisaReadorWritecycle. 0=Read 1=Write

3.3 Pinnamingconventionsforwishbonesignalpins
AltiumDesignerutilizesseveralprefixeswhennamingschematicsymbolpinsthatareapart ofthewishboneinterface.TheseprefixesareintendedtomaketheconnectionofWishbone compatibledeviceseasierandmoreintuitive. Thefollowingtableprovidesalistofcommon prefixesusedinAltiumDesigner,thoughnotapartoftheWishboneInterfacestandard. Prefixeswillbeappliedfollowingtheconvention: <prefix>_<wishbonesignalname> Soforexample,theprefixMEindicatestheinterfacetothememorybusonthehost processor,thusthepinnameME_STB_OwouldindicatetheStrobeSignaloutputonthe memoryinterfaceofadevicesuchasTSK3000A.
CommonPrefixesUsedinWishboneInterfaceSignalPinNames

InterfacePrefix ME me IO io WBM WBS

PrefixDescription Processorinterfacetothememorybusofthe hostprocessor Peripheralinterfacetothememorybusofthe hostprocessor ProcessorinterfacetotheIObusofthehost processor PeripheralinterfacetotheIObusofthehost processor WishboneMasterinterfaceondeviceshaving bothMasterandSlaveinterfaces(e.g.BT656) WishboneSlaveInterfaceondeviceshaving bothMasterandSlaveinterfaces(e.g.BT656)

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CommonPrefixesUsedinWishboneInterfaceSignalPinNames(cont.)

InterfacePrefix m<number>_

PrefixDescription IndicatesaWishboneMasterinterfacetoa WishboneInterconnectorWishboneMulti Masterdevice.WishboneInterconnectdevices arerestrictedtoasinglemaster(typicallythe hostprocessor),thustheMasterinterfacename willalwaysbeprefixedbym0_.WishboneMulti Masterdevicesallowthemasterinterfacestobe renamedthusm1_,m2_,m3_mightberenamed toMCU_,ASP_,VID_inthedevices configurationdialog. Indicatesawishboneslaveinterfacetoa wishboneinterconnectdevice.The<number> attributeuniquelyidentifiesthevariousinterfaces whenconnectingmorethanoneslaveperipheral toagivenmaster.ForexampleS0,S1,S2,etc. wouldallcontainacompletewishboneinterface signalsforslavedevices1,2,&3respectively.

s<number>_

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4 PlacingtheFPGAPeripherals
TocompletetheFPGAportionofourdesign,severalperipheralsarerequiredtoroundoutthe overallsystem.Asourapplicationwillcapturevideoanddisplaythatvideoonatouch screen,itiseasytoassumethatwellneedataminimumavideocapturecontroller,avideo displaydriver,andsomememorybothfortheprocessor,aswellasforthecaptureand displaydevices.

4.1 Exercise3Placingtheperipherals
Inordertocompletethistaskyouwillneedtousethefollowingcomponentsfromtheir respectivelibraries: Component
U5

Library FPGAPeripherals.IntLib

NameInLibrary BT656

RefDes U5

BT656Controller
VID_DATA[7..0] PCLK VBLK WBS_STB_I WBS_CYC_I WBS_ACK_O WBS_ADR_I[2..0] WBS_DAT_O[31..0] WBS_DAT_I[31..0] WBS_SEL_I[3..0] WBS_WE_I CLK_I RST_I INT_O[1..0] WBM_STB_O WBM_CYC_O WBM_ACK_I WBM_ADR_O[31..0] WBM_DAT_O[31..0] WBM_SEL_O[3..0] WBM_WE_O BT656
U7

FPGAPeripherals.IntLib
I2CMasterWishbone
STB_I CYC_I ACK_O ADR_I[2..0] DAT_O[7..0] DAT_I[7..0] WE_I CLK_I RST_I INT_O

I2CM_W

U7

SDATA_EN SDATAO SDATAI SCLK_EN SCLKO SCLKI I2CM_W

U17

FPGAPeripherals.IntLib
io_STB_I io_CYC_I io_ACK_O io_ADR_I[11..0] io_DAT_O[31..0] io_DAT_I[31..0] io_SEL_I[3..0] io_WE_I io_CLK_I io_RST_I io_INT_O[2..0] me_STB_O me_CYC_O me_ACK_I me_ADR_O[19..0] me_DAT_I[31..0] me_SEL_O[3..0] me_WE_O

WB_VGA

U17

WishboneDisplay Driver
TFT_RED[4..0] TFT_GREEN[5..0] TFT_BLUE[4..0] TFT_CL[3..1] TFT_DISP_ON TFT_M TFT_POL TFT_STH TFT_STV

WB_VGA

417

Component
U9

Library FPGAGeneric.IntLib

NameInLibrary IOBUF

RefDes U9,U10

U10

U14

FPGAPeripherals.IntLib
PortWishbone
STB_I CYC_I ACK_O

WB_PRTIO

U14

PAO[7..0]

DAT_I[7..0] WE_I CLK_I RST_I WB_PRTIO

1. PlacetheBT656ControllercoreBT656thiswillbeusedtocapturethedigitalvideo signalfromthevideodecoder.DesignatethiscomponentU5 2. SelectandplacetheI2CMasterWishbonecoreI2CM_W.Thiswillprovidethe intermediateI2Ccontrollertocontrolthe videodecoder.DesignatethispartU7. 3. SelectandplacetheconfigurableWishboneDisplayDriverWB_VGA.Thiswillfetchthe 16bppformatteddatafromexternalmemoryanddisplayitontheTFTpanel. DesignatethispartU17. 4. RightclicktheWishboneDisplayDriverWB_VGAandselectConfigure.Configurethe componenttomatchthefigurebelow:

5. WewillalsorequiretwoI/ObuffersfortheI2CinterfacefromtheI2CMasterController coretotheSDAandSCLsignalsonthevideodecoder.SelecttheFPGA Generic.IntLib fromtheLibrariespanelandplacetwoIOBUFcomponents. DesignatethemU9andU10. 6. Thoughnotarequiredcomponentofoursystem,wewillalsomakeuseofa ConfigurableWishbonePortWB_PRTIOasameanstotestourcode.Designatethis componentU14. 7. Alignallofyourperipheralcomponentsalongtheleftsideofyourprocessorasseenin Figure6.

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Figure6.Placementofperipheralsinschematic

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5 BusInterconnectivityandArbitration
Unlikeofftheshelfmicroprocessorswhichhavetheirperipheralsfixedatthetimeof manufacture,FPGAbasedplatformshavetotalflexibility.Thechoiceinthenumberandtype ofperipheralsistotallyconfigurableandcanbetailoredtothespecificneedsofthe application. Thisalsoaddsalayerofcomplexityhowever,thatuntilAltiumDesignerandthe adventofinterconnectarchitecturessuchaswishbonewasdifficulttomanage. Specifically,thereexiststheproblemofhowtheperipheralsinteractwiththeprocessorwhen morethanoneperipheralneedsaccesstoasharedperipheralbus. Thisprocesshistorically washandledwithgluelogictodecodetheaddressoftheperipheralwithwhichtheprocessor wasintendedtocommunicate. Furtheraddingthecomplexityaredevicesthatrequiredirectmemoryaccess(DMA)andthe managementofmultipledeviceswhichagainneedshareasinglebuswheninterfacingto memory. AltiumDesigneraddressesbothoftheseissueswiththeConfigurableWishbone Interconnect,WB_INTERCON,andConfigurableWishboneDualMasterWB_DUALMASTER andMultiMasterWB_MULTIMASTERcomponents.

5.1 WishboneInterconnectComponentWB_INTERCON
TheWB_INTERCONperipheraldeviceprovidesameansofaccessingoneormore WishbonecompliantslavedevicesoverasingleWishboneinterface.Connectingdirectlyto eithertheExternalMemoryorPeripheralI/OInterfacesofaprocessor,thedevicefacilitates communicationwithphysicalmemorydevicesorI/Operipherals,respectively. TheWB_INTERCONfeatures: Completeconfigurabilityontheschematicsheet 1tonmultiplexing(!WishboneMasterinterface,multipleWishboneSlaveinterfaces) Abilitytocontroldecoderaddresswidth Automatichardwaredecodergeneration AbilitytodefinespecificmappingintoProcessoraddressspace 8,16,and32bitSlaveperipheralsupport Configurableaddressingmodesallowingaslavedevicetobeeitherbyteorword addressed
WishboneInterconnect
m0_STB_I m0_CYC_I m0_ACK_O m0_ADR_I[31..0] m0_DAT_O[31..0] m0_DAT_I[31..0] m0_SEL_I[3..0] m0_WE_I m0_CLK_I m0_RST_I s0_STB_O s0_CYC_O s0_ACK_I s0_ADR_O[19..0] s0_DAT_I[31..0] s0_DAT_O[31..0] s0_SEL_O[3..0] s0_WE_O s0_CLK_O s0_RST_O s1_STB_O s1_CYC_O s1_ACK_I s1_ADR_O[19..0] s1_DAT_I[31..0] s1_DAT_O[31..0] s1_SEL_O[3..0] s1_WE_O s1_CLK_O s1_RST_O

WB_INTERCON

Figure7.WishboneInterconnectComponent

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5.2 ConfiguringtheWishboneInterconnectcomponent
TheWishboneInterconnectcomponentcanbeconfiguredbyrightclickingthecomponentin schematicandselectingConfigure<RefDes>(WB_INTERCON)orbylaunchingthe componentpropertiesdialogandhittingtheconfigurebuttonatthelowerleft.

Figure8.WishboneInterconnectComponentconfigurationdialog

InthisdialogareoptionstoAdd,Remove,andEditthebanksofWishboneSlavedevice interfaces,aswellasoptionstoMoveUpandMoveDown,physicallyreorderingthelocation ofthebankswithrespecttotheschematicsymbol. TheUnusedInterruptsdropdownisusedtocontrolthebehaviorofanyunusedinterrupts onthehostprocessor.Theavailableoptionsare: AddSPAREINTinputpinusethisoptiontomaketheunusedinterruptsignals availableasanadditionalinputpin.Interruptsfromadditionalcircuitryinthedesign canbewiredintothispin. ConnecttoGNDusethisoptiontointernallyconnectallunusedinterruptsto GND.TheinterruptoutputsignalpatternthatissenttotheWishboneMasterdevice willcontain0foreachoftheseunusedinterrupts. NoInterruptoutputpinusethisoptiontoeffectivelydisablemarshallingof interruptstotheprocessor.Anyconfiguredinterruptinputpinsforslavedeviceswill beremovedfromthesymbol,aswellasthespareinterruptspin(whereapplicable) andtheoutputpintotheWishboneMaster.

TheMasterAddressSizedropdownisusedtospecifytheaddresssizedependingonthe
typeofslaveperipheral(s)beingconnected.The32Bit(Memory)optionisusedwhen connectingtoslavememorydevices.IfusingthedevicetoconnecttoslaveperipheralI/O devices,ensurethatthisoptionissetto24Bit(PeripheralI/O).

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Again,theorderinwhichthedevicesappearinthisdialogwilldeterminetheorderinwhich theWishboneInterfacepinswillappearontheschematicsymbol,fromtoptobottom.Using MoveUpandMoveDownintheConfigureU1(WishboneIntercon)dialogwillreorderthe groupsofsignalsastheyappearinschematic. TheAddDeviceoptionisusedtoaddanewwishboneslavedevice.Thiswilllaunchthe DevicePropertiesdialogthatappearsinfigure9.

Figure9.Addingadevicetothewishboneinterconnectcomponent

Thefollowingtabledescribesthevariouspropertiesthatcanbedefinedforawishboneslave interface.

InterfaceProperty
Name

Description
Thennameisauserdefinablefieldandshould meaningfulwhenlistedalongsideotherconnected devices. UsedtospecifythetypeofWishboneSlaveDeviceis beingconnected.

Type

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InterfaceProperty
AddressBusMode

Description
SelecteitherWordorByteaddressing.Inbyte addressingmode,alloftheloweraddresslinesare passedtotheslave,regardlessoftheresolutionofits databus.Theslavedevicewillhandlebytetoword management. Inwordaddressingmode,themapping oftheaddresslinesarepassedtotheslavedevices databuswidth: 32bitwidedevicesthetwolowestaddressbits arenotconnectedtotheslavedevice.ADR_I(2) fromthemasterismappedtoADR_O(0)ofthe slave,providingsequentialwordaddresses(or addressesatevery4bytes).Registers/address locationsinsuchdevicescanbereadandwritten usingtheLWandSW32bitload/storeinstructions 16bitwidedevicesthelowestaddressbitisnot connectedtotheslavedevice.ADR_I(1)fromthe masterismappedtoADR_O(0)oftheslave, providingsequentialhalfwordaddresses(or addressesatevery2bytes).Registers/address locationsinsuchdevicescanbereadandwritten usingtheLHUandSH16bitload/storeinstructions 8bitwidedevicesalladdressbitsare connectedthroughtotheslavedevice.ADR_I(0) fromthemasterismappedtoADR_O(0)ofthe slave,providingsequentialbyteaddresses.Thisis identicaltobyteaddressing.Registers/address locationsinsuchdevicescanbereadandwritten usingtheLBUandSB8bitload/storeinstructions.

AddressBase

UsedtospecifyadecoderbaseaddressforaSlave device.Aportionofthisaddressspecifiedbythe DecodeAddressingvaluewillbecomparedagainst thecorrespondingbitsoftheincomingm0_ADR_I signaltodeterminewhethertheslaveisbeing addressedorbytheprocessorornot. Definesthedecoderaddresswidth.Thisvalue determinesthenumberofupperaddressbitsonthe m0_ADR_Ilinethataredecodedtoselectthecorrect slavedevice.Thereinturnthisvaluealsodetermines thenumberofslavedevicesthatcanbeconnectedto theinterconnectdevice.

DecodeAddressing

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InterfaceProperty
AddressBusWidth

Description
Usedtospecifythenumberofaddressbits requiredtodrivetheconnectedslavedevice. Forslavememorydeviceswhichare connectedviatheMemoryControllerdevice youneedtosettheaddressbustothesame widthastheADR_IlinefortheMemory Controller.TheMemoryControllerwill automaticallysizeitsADR_Ilineaccordingtothe sizeofthephysicalmemoryitisconnectingto. Forslaveperipheraldevices,youneedtosetthe addressbustothesamewidthastheADR_Iline fortheperipheral.

DataBusWidth

Usedtospecifytheresolutionofthedatabusfor theslavedevice.8bit,16bitand32bitdata buswidthsaresupported. Usedtoselectwhichinterrupt(s)touseforthe slavedevice.Foreachinterruptline,youcan alsodefineitstypewhetheritislevelsensitive oredgetriggeredaswellasitspolarity. InterruptsgeneratedbyAltiumDesigner Wishboneperipheraldeviceshavepositive polarityandarelevelsensitive,andthisis thereforethedefaultsetting.Youcanalso specifytherequiredinterruptpinstobeusedby directlytypingwithintheavailabletextfieldin theDevicePropertiesdialog. Anydefinedinterruptswillappearaspartofthe overall32bitinterruptinputbussenttothe WishboneMaster(e.g.a32bithostprocessor).

UsedInterrupts

GraphicalAttributes

Alterstheamountofblankspaceinsertedaftera bankofpins. Anincreaseof+1unit=+10 schematicgridunitsor+100milspacing(1:1)

5.3 Exercise4ConnectingourPeripherals
Connectingthehostprocessortothevariousperipheralsweveplacedisaccomplishedusing theConfigurableWishboneInterconnectcomponent.Inthisexercisewewillseehowto configurethiscomponentforourdesign. 1. Fromthelibrariespanel,selecttheFPGAPeripherals.IntLib andplacethe ConfigurableWishboneInterconnectcomponentWB_INTERCON betweentheleftside ofthehostprocessorandtherightsideoftheperipheralsalreadyplaced.Designate thiscomponentU1. 2. NoticethatcurrentlythisdevicehasonlyonesetofWishbonesignalpins,prefixedm0. Them0prefixindicatestheMasterInterfaceandshouldbefacingtheleftsideofthe hostprocessor. 3. Toconfigurethisdevicefortheslavedevices,rightclickU1andselectConfigureU1 (WB_INTERCON) 4. ReferencingFigure10,configurethefollowingSlaveInterfaces.

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Figure10.Wishboneinterconnectcomponentinterfaces

Note:ThevideocaptureinterfacewillrequireWordaddressingwhileallother interfaceswilluseByteaddressing. 5. SettheUnusedInterruptsdropdowntoConnecttoGNDandtheMasterAddress Sizedropdownto24Bit(PeripheralI/O).

5.4 Managingmemoryaccess
LiketheirtraditionalhardprocessorcounterpartssystemsonFPGAsrequirememory resources. Whethertheseresourcesexistonchiporoffchipdependsontheneedsofthe systemandthedeviceselected.Generally,onchipmemoryisfasterbutconsumesdevice resources.Offchipmemoryontheotherhand,thoughgenerallyslower,haspotentially greaterstoragecapacity. ForourapplicationthebulkofourmemoryresourceswillexistoffchipasSRAMonthe Spartan3Daughtercard.Thememorycontrollershoweverwillexistonchip,aswillthe arbitersthatwillmanagememoryaccess.

5.5 Arbitrationofmultiplemasterssharingasingleslave
Inoursystem,weareagainfacedwithasinglebustoconnectmultiplesoftdevices,thoughin thecaseofmemorythechallengeissomewhatdifferentasratherthanmanagingasingle mastertomultipleslaves,weareinsteadmadetomanagemultiplemasterssharingasingle slaveinterface. Thesingle[slave]interfaceexistsonthememorycontrollersideand arbitrationmustoccurtoensurethatthereisnevermorethanonemasterdeviceaccessing memoryatatime.Likewise,thereareissuesofprioritythatarise.

Inourdesign,oneblockofmemorywillbesharedbytheCaptureControllerandtheHost Processor.AnotherwillbesharedbytheDisplayDriverandtheHostProcessor.The

525

processorwilleffectivelyaccessthevideodatafromtheCaptureMemoryandthenwritethat datatotheDisplayMemory,zoomedandrotatedpertheusersinput.

K6R4016V1DTC10

XRAM1
SAMSUNG

SRAMController

TSK3000

K6R4016V1DTC11

XRAM2
SAMSUNG

SRAMController

VGATFTController
Figure11.Blockdiagramshowingthelayoutofthememorysystem

Thismeansthatforeachofthetwoblocksofmemory,wewillrequireanarbitertocontrol memoryaccess.Thiswillensurethatboththehostprocessorandtheperipheral(whether theCaptureControllerortheDisplayDriver)arenotattemptingtoaccessthesamememory atthesametime.

5.6 WishboneDualandMultiMasterdevices
AltiumDesignerincludestwotypesofarbiters,theWishboneDualMaster(formanagingtwo MastersaccesstoasingleSlave)andthemoreextensibleWishboneMultiMaster component(formanagingupto8MastersaccesstoasingleSlavedevice).
WishboneMultiMaster
m1_STB_I STB_O NoDelay m1_CYC_I CYC_O m1_ACK_O ACK_I m1_ADR_I[31..0] ADR_O[31..0] m1_DAT_O[31..0] DAT_I[31..0] m1_DAT_I[31..0] DAT_O[31..0] m1_SEL_I[3..0] SEL_O[3..0] m1_WE_I WE_O m1_CLK_I CLK_O m1_RST_I RST_O

WishboneDualMaster
m0_STB_I m0_CYC_I m0_ACK_O m0_ADR_I[31..0] m0_DAT_O[31..0] m0_DAT_I[31..0] m0_SEL_I[3..0] m0_WE_I m0_CLK_I m0_RST_I STB_O CYC_O ACK_I ADR_O[31..0] DAT_I[31..0] DAT_O[31..0] SEL_O[3..0] WE_O CLK_O RST_O

Figure12.Wishbone dualandmultimaster components

m2_STB_I m2_CYC_I m2_ACK_O m2_ADR_I[31..0] m2_DAT_O[31..0] m2_DAT_I[31..0] m2_SEL_I[3..0] m2_WE_I m2_CLK_I m2_RST_I WB_MULTIMASTER

m1_STB_I m1_CYC_I m1_ACK_O m1_ADR_I[31..0] m1_DAT_O[31..0] m1_DAT_I[31..0] m1_SEL_I[3..0] m1_WE_I m1_CLK_I m1_RST_I WB_DUALMASTER

K6R4016V1DTC11

SAMSUNG

K6R4016V1DTC10

BT656Controller

SAMSUNG

526

AswewillbemakingchangeslaterthatwillrequiretheadditionofanotherMasteraccessing eachofthesetwomemories,wewillutilizetheWishboneMultiMastercomponentsinour design.TheWishboneMultiMasterfeatures: Supportforupto8WishboneMasters Abilitytocontroladdressanddatabuswidths AbilitytospecifyMasteraccessingmode: RoundRobingivingmastersaccesstotheslaveinsequence(topto bottom) Priorityallowingyoutodefineanorderofpriorityforaccesstotheslave

AbilitytograntoneMasterinstantaccesstothebuswhenin'idle'state SupportspassingofinterruptsfromaconnectedWishboneInterconnect,throughto allconnected32bitprocessors(whenusedtoshareslaveperipheralI/Odevices).

5.7 Configuringthewishbonemultimastercomponent
TheWishboneInterconnectcomponentcanbeconfiguredbyrightclickingthecomponentin schematicandselectingConfigure<RefDes>(WB_MULTIMASTER)orbylaunchingthe componentpropertiesdialogandhittingtheConfigurebuttonatthelowerleft.

Figure13.Wishbonemultimasterconfigurationdialog

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InthisdialogareoptionstoAdd,Remove,andEditthebanksofWishboneSlavedevice interfaces,aswellasoptionstoMoveUpandMoveDown,physicallyreorderingthelocation ofthebankswithrespecttotheschematicsymbol.Thefollowingtableliststhevarious optionsavailableforconfiguringmastersaccesstoaslavedevice. Option Type Description Enablesyoutospecifythewayinwhichthe WishboneMasterscontestfortheslave resource.Thefollowingoptionsareavailable: RoundRobin mastersaccesstheslavein sequence,fromfirst(top)tolast(bottom). Prioritymastersaccesstheslaveinthe specifiedorderofpriority. Allowsyoutospecifyhowmanymaster interfacesthedevicewillhave(upto8masters aresupported) DisplaystheTypeandnumberofmasters specified. IfTypeissettoRoundRobin,onlytheName andSpacesAfterPinscolumnswillbe displayed.Thesharedresourcewillbe accessedbyeachmasterinturn,fromthetopof thelistdown.IfTypeissettoPriority,athird Prioritycolumnwillbedisplayedallowingyouto specifyanexplicitpriority(1beinghighest priority). UsetheNamefieldtochangetheprefixforeach master.UsetheSpacesAfterPins fieldto determinetheamountofblankspacethatis insertedafterthebankofpinsforthatmaster interface. MastersWithNoDelay Allowsyoutospecifyonemastertobegranted instantaccesstothebuswhenthe WB_MULTIMASTERis'idle'.Thisreduces latencyasthenominatedmasterexperiencesno delayinacquiringaccess.Typically,when operatinginPrioritymode,themasterspecified herewillbetheoneassignedhighestpriority. Theinterfaceassignedtobethemasterwithno delayisdistinguishedontheschematicsymbol byinsertionofthetext"NoDelay".

Masters

RoundRobin/PriorityOrder

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Option AddressBusWidth

Description Allowsyoutospecifythenumberofaddressbits requiredtodrivetheconnectedslavedevice. Thewidthchosenisappliedtoallinterfacesof theWB_MULTIMASTER. Whenconnectingtoasingleslavememory deviceyouneedtosettheaddressbustothe samewidthastheADR_IlinefortheMemory Controller.TheMemoryControllerwill automaticallysizeitsADR_Ilineaccordingtothe sizeofthephysicalmemoryitisconnectingto. AWishboneInterconnectmustthenbeused betweentheMultiMasterandtheprocessor's ExternalMemoryInterface,tohandlethe addresslinemapping. Whenconnectingtoabankofphysicalmemory devicesthroughaWishboneInterconnect,the addressbusmustbesetto32BitsRange= 4GB,whichmatchestheADR_Ilineofthe Interconnect'smasterinterface. Whenconnectingtoasingleslaveperipheral device,youneedtosettheMultiMaster's addressbustothesamewidthastheADR_Iline fortheperipheral.AWishboneInterconnectmust thenbeusedbetweentheMultiMasterandthe processor'sPeripheralI/OInterface,tohandle theaddresslinemapping. Whenconnectingtoabankofperipheraldevices throughaWishboneInterconnect,theaddress busmustbesetto24BitsRange=16MB, whichmatchestheADR_Ilineofthe Interconnect'smasterinterface.

DataBusWidth

Allowsyoutospecifytheresolutionofthedata busfortheslavedevicebeingconnected.8bit, 16bitand32bitdatabuswidthsaresupported. Thewidthchosenisappliedtoallinterfacesof theWB_MULTIMASTER. EnabletheShowInterruptPinsoptioninthis regionofthedialogtoaddtheINT_O[31..0]and INT_I[31..0]pinstothemasterandslave interfacesrespectively.Theinterruptpinswould beaddedwhentheMultiMasterdeviceisused toconnectmultiple32bitprocessorstoabank ofperipheralI/Odevices,viaaWishbone Interconnect. Thisallowsinterruptsgeneratedbythose peripheralstobepassedfromtheInterconnect throughtotheprocessors.

Interrupts

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5.8 Exercise5DefiningourMultiMasterComponents
InthisexercisewewillplaceandconfiguretheWishboneMultiMastercomponentsrequired byourdesign. Thesecomponentswillfunctionasarbiterstomanageaccesstothe externalmemoryusedbyoursystem. 1. Fromthelibrariespanel,selecttheFPGAPeripherals.IntLib andplace2 WishboneMultiMastercomponentsWB_MULTIMASTER alongtherightsideofthehost processor.DesignatetheseU3andU12. 2. RightclickU3andselectConfigureU3(WB_MULTIMASTER) tolaunchthe configurationdialog.Wewillconfigurethisdeviceforboththehostprocessoraswell astheBT656VideoCaptureController. 3. ConfigureU3andU12asseeninthefigurebelow.

Figure14.U3andU12WishboneMultiMasterconfigurationdialogs

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6 InterfacingtoExternalMemory
AltiumDesignerincludesaWishboneCompatibleConfigurableMemoryController WB_MEM_CTRLthat,dependingonitsconfiguration,providesasimpleinterfacebetweena32 bitprocessorandeithersingledatarateSynchronousDRAM,AsynchronousStaticRAM,32 bitwideBlockRAM(singleordualport),orparallelFlashmemory.

SRAMController
STB_I SRAM0_D[15..0] CYC_I SRAM0_A[17..0] ACK_O SRAM0_CE ADR_I[19..0] SRAM0_WE DAT_O[31..0] SRAM0_OE DAT_I[31..0] SRAM0_UB SEL_I[3..0] SRAM0_LB WE_I CLK_I SRAM1_D[15..0] RST_I SRAM1_A[17..0] SRAM1_CE SRAM1_WE SRAM1_OE SRAM1_UB SRAM1_LB WB_MEM_CTRL
Figure15.WishboneConfigurableMemoryController

TheMemoryController(Figure15)features: SimplifiedconnectiontoprocessorsExternalMemoryinterfaceviaaWishbone Interconnect ConfigurableaseitherSRAM,SDRAM,orBRAMController SDRAMControllerinterfacesto8,16,or32bitwideSDRSDRAM SRAMControllerinterfacesto8,16,or32bitwideasynchronousSRAM BRAMControllerinterfacesto32bitwidesingleordualportBlockRAM FlashControllerinterfacesto8,16,or32bitwideparallelFlashmemory AutomaticsizingofADR_Iinputbus,basedonspecifiedphysicalmemorysize Wishbonecompliantinterface

6.1 ConfiguringtheSRAMController
TheSRAMControllercomponentcanbeconfiguredbyrightclickingthecomponentin schematicandselectingConfigure<RefDes>(WB_MEM_CTRL)orbylaunchingthe componentpropertiesdialogandhittingtheConfigurebuttonatthelowerleft.

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Figure16.WishboneConfigurableMemoryControllerconfigurationdialog

Inthisdialogareoptionstoconfigurethememorycontrollerforusewithavarietyofdifferent memorysizesandtypes.Thefollowingtableprovidesadescriptionofthevariousoptions availablewhenconfiguringthememorycontroller.

Option
MemoryType

Description
Specifiesthetypeofmemorythatyouwishto interfaceto.Choosefromeither: SynchronousDRAM AsynchronousSRAM BlockRAM ParallelFLASH

Theconfigurationoptionspresentedinthe dialogwillchangewithyourselection. SizeOf<MemoryType> SpecifiesthesizeofthephysicalRAMthatyou areinterfacingto.Thewidthoftheinterface addressbus(es)andalsotheADR_Iinputline willupdateaccordinglyuponleavingthedialog. Thisdialogwillupdatedynamicallyasthe MemoryTypechanges.

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Option SizeOf<MemoryType>

Description SpecifiesthesizeofthephysicalRAMthatyouare interfacingto.Thewidthoftheinterfaceaddress bus(es)andalsotheADR_Iinputlinewillupdate accordinglyuponleavingthedialog. ThisdialogwillupdatedynamicallyastheMemory Typechanges. Usedtoselectthelayoutforthephysicalmemory.The schematicsymbolfortheplacedMemoryController willautomaticallybeupdatedtoreflectyourselection, uponleavingthedialog. Inadditiontodeterminingtheinterfacepinoutfor connectiontothephysicalmemorydevice(s),the memorylayoutalsodeterminesthenumberof accessesrequiredtoreadorwriteasingle32bitword. InthecaseofBRAM,thisregionofthedialogisnon editableandreflectsthelayoutofphysicalBRAMthat canbeconnectedtotheController

MemoryLayout

ClockcyclesforReading

OnlyeditablewhenusingParallelFlash,thisoption allowsyoutospecifythenumberofclockcycles(of CLK_I)requiredtoperformareadoperation. OnlyeditablewhenusingParallelFlash,thisoption allowsyoutospecifythenumberofclockcycles(of CLK_I)requiredtoperformawriteoperation. OnlyvisiblewhenusingSDRAM,thisoptionallowsyou tospecifytheSDRAMsclockfrequencyinMHZ.The frequencyofthesignalarrivingatthecontrollers SDRAM_CLKinputmustmatchthisclockfrequency. TheKeepCurrentRowOptionallowsyoutokeepthe currentrowopenessentiallydisablingtheSDRAM devicesautoprechargefeaturewhichotherwise causesaprechargeoftheaddressedbank/rowupon completionofthecurrentReadorWrite. OnlyvisiblewhenusingSDRAM,theseoptionsallow youtospecifytheWriteRecoveryTime(tWR),Auto Refreshperiod(tRFC),ActivetoReadorWritedelay (tRCD),Prechargecommandperiod(tRP),andCAS latency(tCAS).Eachofthesevaluesisspecifiedin termsofthenumberofcyclesoftheSDRAM_CLK signal. Thedropdownallowsyoutodefinethesynchronization schemetobeusedwheninterfacingtoSDRAM. Ensurethatthefrequencyofthesignalwiredtothe Controller'sSDRAM_CLKinputisinaccordancewith thesynchronizationsettingyouhavechosen.

ClockcyclesforWriting

MemorySettings

TimerSettings

6.2 TheSharedMemoryController
AltiumDesigneralsoincludesaWishboneCompatibleSharedMemoryControllercore WB_SHARED_MEM_CTRLthat,dependingonitsconfiguration,providesasimpleinterface betweena32bitprocessorandmemoriesonasharedbus.

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SharedMemoryController
SRAM_STB_I SRAM_CYC_I SRAM_ACK_O SRAM_ADR_I[19..0] SRAM_DAT_O[31..0] SRAM_DAT_I[31..0] SRAM_SEL_I[3..0] SRAM_WE_I SRAM_CLK_I SRAM_RST_I MEM_D[31..0] MEM_A[23..0] MEM_W MEM_OE MEM_BE[3..0] MEM_SDRAM_CKE MEM_SDRAM_RAS MEM_SDRAM_CAS MEM_SDRAM_E MEM_FLASH_BUSY MEM_FLASH_RESET MEM_FLASH_E MEM_SRAM_E

WB_SHARED_MEM_CTRL

TheControllerprovidesaccessto,anduseof,thefollowingthreedifferenttypesofmemory, eachofwhichismultiplexedforaccessovershareddataandaddressbusses: AsynchronousStaticRAM SingledatarateSynchronousDRAM ParallelFlashmemory

TheControllerhandlesallmultiplexingforyou,negatingtheneedforcustomdemultiplexing logic. Note:TheWB_SHARED_MEM_CTRLisprimarilydesignedtobeusedwiththecommonbus memorieslocatedonAltium's3connectordaughterboards,suchastheXilinxSpartan3 DaughterBoardDB30.Providedthesamepinoutisused,theControllercouldbeusedto interfacetoothermemoriesofthetypessupported,andwhichareaccessedusingashared busarchitecture.

6.3 ConfiguringtheSharedMemoryController
TheSRAMControllercomponentcanbeconfiguredbyrightclickingthecomponentin schematicandselectingConfigure<RefDes>(WB_SHARED_MEM_CTRL)orbylaunching thecomponentpropertiesdialogandhittingtheConfigurebuttonatthelowerleft.

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Inthisdialogareoptionstoconfigurethememorycontrollerforusewithavarietyofdifferent memorysizesandtypes.Foracompletelistofconfigurationoptions,seethereference CR0176WB_SHARED_MEM_CTRLConfigurableSharedMemoryController.pdf foundundertheHelpmenuouravailablefromtheAltiumwebsite.Forourdesignwewillbe configuringthedeviceasAsynchronousRAMandthefollowingtableprovidesadescriptionof thevariousoptionsavailablewhenconfiguringthememorycontroller. Option MemorySize Description Usethisregionofthepagetospecifythesizeofthe physicalmemorythatyouareinterfacingto.For example,thecommonbusSRAMona3connector daughterboardisprovidedbytwo4Mbit,highspeed CMOSSRAMdevices.Eachdeviceisorganizedas 256Kx16bitscombinedtogethertogive256Kx32 bitstorage(1MByte). ThewidthoftheSRAM_ADR_Iinputlinewill automaticallychangeaccordingtomemorysize specified. MemoryLayout Usethedropdownavailableinthisregionofthepage toselectthelayoutforthephysicalmemory. Inadditiontodeterminingtheinterfacepinoutfor connectiontothephysicalmemorydevice(s),the memorylayoutalsodeterminesthenumberof accessesrequiredtoReadorWriteasingle32bit word. Thisregionofthepageenablesyoutospecify additionalclockcycles(cyclesofSRAM_CLK_I)tobe addedforeachstageofaReadandWriteoperation. Eachstagemustbeatleastoneclockcycle. Theminimumnumberofclockcyclesforeach operationare: Readtwoclockcycles.Ifthesystemclock (SRAM_CLK_I)is50MHz,thisequatesto 40ns.

TimingSettings

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Writethreeclockcycles.Withasystem clock(SRAM_CLK_I)of50MHz,thisequates to60ns. Thefollowingdefaulttimingsettingsareused: Clockcyclesforaddresssetup1cycle Clockcyclesforwritepulse1cycle Clockcyclesforpostwriteaddresshold1 cycle.

6.4 Exercise6Placingandconfiguringmemorycontrollers
InthisexercisewewillplaceandconfiguretheConfigurableWishboneMemoryController WB_MEM_CTRL andthe WishboneSharedMemoryControllerWB_SHARED_MEM_CTRL. ThesecontrollerswillserveastheFPGAsideinterfaceto2MBofAsynchronousSRAM locatedontheSpartan3FPGADaughterboard. 1. Fromthelibrariespanel,selecttheFPGAPeripherals.IntLib andplacethe ConfigurableMemoryControllercomponentsWB_MEM_CTRL alongtherightsideofthe WishboneMultiMastercomponent.DesignatethiscomponentU4. 2. RightclickU4andselectConfigureU4(WB_MEM_CTRL)tolaunchthe configurationdialog.ConfigureU4asitappearsinFigure17.

Figure17.ConfiguringthewishbonememorycontrollerU4

3. ReturntotheFPGAPeripherals.IntLib andplacetheSharedMemoryController componentsWB_SHARED_MEM_CTRL alongtherightsideoftheWishboneMultiMaster component.DesignatethiscomponentU13. 4. RightclickU13andselectConfigureU13(WB_SHARED_MEM_CTRL)tolaunch theconfigurationdialog.ConfigureU13asitappearsinFigure18.

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Figure18.ConfiguringthewishbonesharedmemorycontrollerU13

6.5 Exercise7Multiplememoriesasslaves
OurhostprocessorwillrequireasecondWishboneInterconnectcomponentaseachofthe twoarbitersappearsasslavestotheprocessorsmemoryinterface.Inthisexercisewewill addasecondConfigurableWishboneInterconnectcomponentandconfigureitforthetwo memoriesinourdesign. 1. Fromthelibrariespanel,selecttheFPGAPeripherals.IntLib andplacea ConfigurableWishboneInterconnectcomponentWB_INTERCON totherightsideofthe hostprocessor.DesignatethiscomponentU8. 2. RightclickthecomponentandselectConfigureU8(WB_INTERCON)tolaunchthe componentsconfigurationdialog. 3. Intheconfigurationdialog,configurethiscomponentasitappearsinFigure19.

Figure19.Configuringthewishboneinterconnecttosupportmultiplememoryslaves

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6.6 Exercise8PlacingthePortPlugInComponents
Eachoftheperipheralsthatwehaveplacedthusfarwillconnecttothecorresponding hardwareontheNanoBoardusingaPortPlugIncomponentlocatedinoneofthevarious PortPlugInlibrariesdetailedinourdiscussionsonDay1.Inthisexercisewewillplacethe requiredPortPlugIncomponentsandarrangethemsuchthatwemightsimplifythe connectivity. 1. LocatetheFPGAPB01PortPlugin.IntLibintheLibrariespanelandplacethefollowing componentsarrangedalongtheleftsideoftheFPGAperipheralsasseeninFigure20. VIDEO_INPUT VIDEO_INPUT_CTRL

2. LocatetheFPGANB2DSK01PortPlugin.IntLibintheLibrariespanelandplacethe followingcomponentsarrangedalongtheleftsideoftheFPGAperipheralsasseenin Figure20. CLOCK_BOARD TEST_BUTTON LED TFT_LCD NEXUS_JTAG_CONNECTOR

3. LocatetheFPGADBCommonPortPlugin.IntLibintheLibrariespanelandplacethe followingcomponentsarrangedalongtheleftsideoftheFPGAperipheralsasseenin Figure20. SRAM_DAUGHTER0 SRAM_DAUGHTER1 SHARED_SRAM_DAUGHTER

4. LocatetheFPGAGeneric.IntLibintheLibrariespanelandplacethefollowing components. NEXUS_JTAG_PORT INV

5. DesignatetheInverterU16. Noreferencedesignatorswillberequiredforanypartsotherthantheinverterasthe remainingpartsarenotcomponentsoftheFPGAbutratherportsreferencingcomponents externaltotheFPGAproject.Thefactthatthesehavebeencollectedintoalibraryandcan beplacedascomponentsisintendedonlytosimplifytheprocessofdevelopingFPGAsusing theDesktopNanoBoard. TheschematicinFigure20displayshowtoarrangethecomponentstoensureeaseinwiring. NoticethewayinwhicheachoftheWishboneInterfacescanbealignedtosimplifythis process.

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Figure20.Schematicincludingtherequiredportplugincomponents

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6.7 Exercise10WiringUpYourFPGADesign
Inthisexercisewewillwrapupthecaptureportionofourdesignbywiringupourschematic. AsinDay1,thesewiresrepresentphysicalconnectionsinsidetheFPGAwhetherbetween blocksofFPGAIPortopinsoftheFPGAdevice(asisthecaseoftheNanoBoardPortPlug Incomponents). Withtheassistanceofyourinstructor,wirethedesignasitappearsinFigure21. Snippets havebeenaddedtotheSnippetspaneltoassistyouinmakingthisprocessfaster. Besure toincludebusjoinersandbuspowerportsasrequired.

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U5 U2 U3

U1

U4

BT656Controller

WishboneInterconnect SRAMController

TSK3000A32BitRISCProcessor

WishboneMultiMaster

VIDIN_DATA[7..0] VIDIN_PCLK VIDIN_INTERQ_GPLC SAMSUNG SAMSUNG

K6R4016V1DTC10

VID_DATA[7..0] PCLK VBLK

VIDIN_AVID VIDIN_HSYNC VIDIN_VSYNC VIDIN_FID_CLCO

WBS_STB_I WBS_CYC_I WBS_ACK_O WBS_ADR_I[2..0] WBS_DAT_O[31..0] WBS_DAT_I[31..0] WBS_SEL_I[3..0] WBS_WE_I CLK_I RST_I INT_O[1..0] VID_STB VID_CYC VID_ACK VID_ADR[31..0]
MDU:Installed DebugHardware:Installed InternalMemory:32KB

s0_STB_O s0_CYC_O s0_ACK_I s0_ADR_O[2..0] s0_DAT_I[31..0] s0_DAT_O[31..0] s0_SEL_O[3..0] s0_WE_O s0_CLK_O s0_RST_O

m0_STB_I m0_CYC_I m0_ACK_O m0_ADR_I[23..0] m0_DAT_O[31..0] m0_DAT_I[31..0] m0_SEL_I[3..0] m0_WE_I m0_CLK_I m0_RST_I m0_INT_O[31..0] VID_STB VID_CYC VID_ACK VID_ADR[19..0] WB_MEM_CTRL SRAM1_D[15..0] SRAM1_A[17..0] SRAM1_E SRAM1_W SRAM1_OE SRAM1_UB SRAM1_LB SAMSUNG
K6R4016V1DTC10

IO_STB_O IO_CYC_O IO_ACK_I IO_ADR_O[23..0] IO_DAT_I[31..0] IO_DAT_O[31..0] IO_SEL_O[3..0] IO_WE_O IO_CLK_O IO_RST_O INT_I[31..0] CurrentConfiguration

ME_STB_O ME_CYC_O ME_ACK_I ME_ADR_O[31..0] ME_DAT_I[31..0] ME_DAT_O[31..0] ME_SEL_O[3..0] ME_WE_O ME_CLK_O ME_RST_O

MCU_STB MCU_CYC MCU_ACK MCU_ADR[31..0] MCU_DIN[31..0] MCU_DOUT[31..0] MCU_SEL[3..0] MCU_WE MCU_CLK MCU_RST MCU_STB_I STB_O MCU_CYC_I CYC_O NoDelay MCU_ACK_O ACK_I MCU_ADR_I[19..0] ADR_O[19..0] MCU_DAT_O[31..0] DAT_I[31..0] MCU_DAT_I[31..0] DAT_O[31..0] MCU_SEL_I[3..0] SEL_O[3..0] MCU_WE_I WE_O MCU_CLK_I CLK_O MCU_RST_I RST_O STB_I SRAM0_D[15..0] CYC_I SRAM0_A[17..0] ACK_O SRAM0_CE ADR_I[19..0] SRAM0_WE DAT_O[31..0] SRAM0_OE DAT_I[31..0] SRAM0_UB SEL_I[3..0] SRAM0_LB WE_I CLK_I SRAM1_D[15..0] RST_I SRAM1_A[17..0] SRAM1_CE SRAM1_WE SRAM1_OE SRAM1_UB SRAM1_LB SRAM0_D[15..0] SRAM0_A[17..0] SRAM0_E SRAM0_W SRAM0_OE SRAM0_UB SRAM0_LB
K6R4016V1DTC10

TVP5150AM1

MCU1_STB MCU1_CYC MCU1_ACK MCU1_ADR[19..0] MCU1_DIN[31..0] MCU1_DOUT[31..0] MCU1_SEL[3..0] MCU1_WE MCU1_CLK MCU1_RST

WBM_STB_O WBM_CYC_O WBM_ACK_I WBM_ADR_O[31..0] VID_DOUT[31..0] VID_SEL[3..0] VID_WE TSK3000A CLK RST CLK_I RST_I VID_DOUT[31..0] VID_SEL[3..0] VID_WE CLK RST

WBM_DAT_O[31..0] WBM_SEL_O[3..0] WBM_WE_O

BT656 U7 U8 WB_MULTIMASTER

VIDEO_STB_I HighPriority VIDEO_CYC_I VIDEO_ACK_O VIDEO_ADR_I[19..0] VIDEO_DAT_O[31..0] VIDEO_DAT_I[31..0] VIDEO_SEL_I[3..0] VIDEO_WE_I VIDEO_CLK_I VIDEO_RST_I

I2CMasterWhishbone WishboneInterconnect

U9

SDATA_EN

SDATAO

SDATAI

TVP5150AM1

SDA SCL

STB_I CYC_I ACK_O ADR_I[2..0] DAT_O[7..0] DAT_I[7..0]

U10

SCLK_EN

SCLKO

s1_STB_O s1_CYC_O s1_ACK_I s1_ADR_O[2..0] s1_DAT_I[7..0] s1_DAT_O[7..0] s1_SEL_O[3..0] s1_WE_O s1_CLK_O s1_RST_O MCU_STB MCU_CYC MCU_ACK MCU_ADR[31..0] MCU_DIN[31..0] MCU_DOUT[31..0] MCU_SEL[3..0] MCU_WE MCU_CLK MCU_RST m0_STB_I m0_CYC_I m0_ACK_O m0_ADR_I[31..0] m0_DAT_O[31..0] m0_DAT_I[31..0] m0_SEL_I[3..0] m0_WE_I m0_CLK_I m0_RST_I s0_STB_O s0_CYC_O s0_ACK_I s0_ADR_O[19..0] s0_DAT_I[31..0] s0_DAT_O[31..0] s0_SEL_O[3..0] s0_WE_O s0_CLK_O s0_RST_O MCU1_STB MCU1_CYC MCU1_ACK MCU1_ADR[19..0] MCU1_DIN[31..0] MCU1_DOUT[31..0] MCU1_SEL[3..0] MCU1_WE MCU1_CLK MCU1_RST

SCLKI

WE_I CLK_I RST_I INT_O

I2CM_W U14

PortWishbone
s2_STB_O s2_CYC_O s2_ACK_I GND

LEDS[7..0]

PAO[7..0]

STB_I CYC_I ACK_O

DAU_TFT_IRQ DAU_TFT_RED[4..0] DAU_TFT_GREEN[5..0] DAU_TFT_BLUE[4..0] DAU_TFT_CL[3..1] DAU_TFT_DISP_ON DAU_TFT_M DAU_TFT_POL DAU_TFT_STH DAU_TFT_STV DAU_TFT_MUX DAU_TFT_BLIGHT s3_STB_O s3_CYC_O s3_ACK_I s3_ADR_O[11..0] s3_DAT_I[31..0] s3_DAT_O[31..0] s3_SEL_O[3..0] s3_WE_O s3_CLK_O s3_RST_O WB_INTERCON

TFT_RED[4..0] io_STB_I TFT_GREEN[5..0] io_CYC_I TFT_BLUE[4..0] io_ACK_O TFT_CL[3..1] io_ADR_I[11..0] TFT_DISP_ON io_DAT_O[31..0] TFT_M io_DAT_I[31..0] TFT_POL io_SEL_I[3..0] TFT_STH io_WE_I TFT_STV io_CLK_I io_RST_I io_INT_O[2..0]

SRAM_STB_I MEM_D[31..0] SRAM_CYC_I MEM_A[23..0] SRAM_ACK_O MEM_W SRAM_ADR_I[19..0] MEM_OE SRAM_DAT_O[31..0] MEM_BE[3..0] SRAM_DAT_I[31..0] MEM_SDRAM_CKE SRAM_SEL_I[3..0] MEM_SDRAM_RAS SRAM_WE_I MEM_SDRAM_CAS SRAM_CLK_I MEM_SDRAM_E SRAM_RST_I MEM_FLASH_BUSY MEM_FLASH_RESET MEM_FLASH_E MEM_SRAM_E

BUS_D[31..0] BUS_A[24..1] BUS_NWE BUS_NOE BUS_NBE[3..0] BUS_SDRAM_CKE VCC BUS_SDRAM_NRAS VCC BUS_SDRAM_NCAS VCC BUS_SDRAM_NCS VCC BUS_FLASH_NBUSY X BUS_FLASH_NRESET VCC BUS_FLASH_NCS VCC BUS_RAM_NCS BUS_SDRAM_CLK GND

me_STB_O me_CYC_O me_ACK_I me_ADR_O[19..0] me_DAT_I[31..0] GND TFT_SEL[3..0] TFT_WE

TFT_STB TFT_CYC TFT_ACK TFT_ADR[19..0] TFT_DIN[31..0]

TFT_STB TFT_CYC TFT_ACK TFT_ADR[19..0] TFT_DIN[31..0] TFT_SEL[3..0] TFT_WE CLK RST

GND

WB_SHARED_MEM_CTRL

me_SEL_O[3..0] me_WE_O

TFT_STB_I HighPriority TFT_CYC_I TFT_ACK_O TFT_ADR_I[19..0] TFT_DAT_O[31..0] TFT_DAT_I[31..0] TFT_SEL_I[3..0] TFT_WE_I TFT_CLK_I TFT_RST_I WB_MULTIMASTER

WB_VGA

JTAG

JTAG

JTAG

JTAG

JTAG_NEXUS_TDI JTAG_NEXUS_TDO JTAG_NEXUS_TCK JTAG_NEXUS_TMS

TDI TDO TCK TMS

JTAG

. . .

JTAG

VCC

TRST

CLK_BRD

CLK

U16

TEST_BUTTON

RST

INV

SAMSUNG

K6R4016V1DTC10

Figure21.Completedschematicwiththerequiredwiring
s1_STB_O s1_CYC_O s1_ACK_I s1_ADR_O[19..0] s1_DAT_I[31..0] s1_DAT_O[31..0] s1_SEL_O[3..0] s1_WE_O s1_CLK_O s1_RST_O WB_INTERCON U12 U13 MCU2_STB MCU2_CYC MCU2_ACK MCU2_ADR[19..0] MCU2_DIN[31..0] MCU2_DOUT[31..0] MCU2_SEL[3..0] MCU2_WE MCU2_CLK MCU2_RST s2_DAT_I[7..0] s2_DAT_O[7..0] s2_SEL_O[3..0] s2_WE_O s2_CLK_O s2_RST_O

DAT_I[7..0]

WE_I CLK_I RST_I

WB_PRTIO

U17 MCU2_STB MCU2_CYC MCU2_ACK MCU2_ADR[19..0] MCU2_DIN[31..0] MCU1_DOUT[31..0] MCU2_SEL[3..0] MCU2_WE MCU2_CLK MCU2_RST

WishboneMultiMaster
MCU_STB_I STB_O MCU_CYC_I CYC_O NoDelay MCU_ACK_O ACK_I MCU_ADR_I[19..0] ADR_O[19..0] MCU_DAT_O[31..0] DAT_I[31..0] MCU_DAT_I[31..0] DAT_O[31..0] MCU_SEL_I[3..0] SEL_O[3..0] MCU_WE_I WE_O MCU_CLK_I CLK_O MCU_RST_I RST_O

SharedMemoryController

WishboneDisplayDriver

VCC

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7 ConfiguringProcessorMemory
AtthisstagewehavelargelycompletedtheFPGAportionofourdesignhoweveronekey stepremainsandthatistheconfigurationofourprocessormemoryfromwithintheprocessor. Inadditiontothememorythatismanagedbyeachoftheinterconnectcomponentswithinour designyoucanalsocentrallymanagememoryfromtheprocessorsmemoryandperipheral configurationdialogboxes.Theseareaccessedbyrightclickingtheprocessorandselecting ConfigureProcessorMemoryandConfigureProcessorPeripheral respectively. Alternatively,bothdialogsareaccessiblefromwithinthecomponentpropertiesdialogfor thesecomponents.

Figure22.Processormemoryconfigurationdialog

Belowisatablethatdescribesthevariousoptionswithinthisdialog.

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Option hardware.asm(AssemblyFile)

Description Usedtopassthememoryandperipheral definitioninformationtotheEmbeddedSoftware projectintheformofaHeaderFile.Aheader fileessentiallyprovideskeywordsubstitution. TheEmbeddedSoftwaredesignercansimply enteradefinitionintothecode,which,through theheaderfile,willbesubstitutedwiththe requiredinformationatcompiletime.Thisoption producesaHeaderfileinAssemblylanguage. Usedtopassthememoryandperipheral definitioninformationtotheEmbeddedSoftware projectintheformofaHeaderFile. Thisoption producedaHeaderfileasaClanguagefile. UsedtoResetthememoryconfigurationtoits defaultsettings.Thisoptionwouldonlybeused whenthecurrentmemoryconfigurationisoutof dateandneedstoberedone,orwhenthe designdoesnotcontainaspecialorexplicit configuration.Usecautionasthisoptiondoes notprovideaWarningdialogandcanonlybe undonebyhittingCancelpriortoclosingthe dialogorclosingandreopeningtheschematic. Usedwhenphysicalmemorydevicesare connectedtotheprocessorthroughaWishbone Interconnect.Thisisthesimplestwaytomake thesedevices'known'totheprocessorasit automaticallymapsthedevicesintothe processor'saddressspaceperthesettings definedintheWishboneInterconnect componentsconfigurationdialog(asseenwith theXRAMslaveinterfaceswhichhadcomeup predefinedinExercise10). Usedtodefineamemoryconfigurationspecific toaparticularapplication. LaunchestheConfigurePeripheralsdialogused tospecifytheperipheralsastheyareseenby theprocessorthroughitsProcessorI/Ospace.If usingWishbonecompliantperipheralsaccessed throughtheWishboneinterconnect,thisdialog maybepopulatedautomaticallyusingtheImport FromSchematicoption.

hardware.h(CHeaderFile)

SettoDefault

ImportFromSchematic

ConfigureApplicationMemory ConfigurePeripherals

7.1 Dividingtheprocessormemory
ThoughwehavealreadydefinedthesizeoftheInternalProcessorMemorywhenwed previouslyconfiguredthedevice(thiswas32KBytesor8Kx32bitWords)AltiumDesigner affordsustheabilityto furthercarveoutspecificmemoriestoappearinaparticularwaytothe hostprocessor.Soforexample,thoughwehave32Kbytesofmemory,wewillactually changethewaytheprocessorseesthismemory,carvingitinto2,16Kbytechunks.

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Forourapplication,wewillalsoneedtopartitiontheprocessorsinternalmemory,specifying halfoftheinternalmemory(16Kbytes)asROMandtheotherhalfasRAM.Todothis,we needfirsttorightclickintheDeviceMemorysectionoftheConfigureProcessorMemory dialogandremovethelarge,32KbytessectionlabeledU2.Wecanthenrightclickandadd thetwosmallersections,configuredforourapplication.ThiswilllaunchtheProcessor MemoryDefinitiondialogthatappearsinFigure23.

Figure23.Furtherconfiguringtheprocessormemory

FromtheConfigureProcessorMemorydialogwewillfurtherrefineourprocessormemoryby dividingthememoryintotwo16Kbytesections.Thetablebelowdescribesthevarious optionsavailablefromwithinthisdialog. Option Name Description Usedtospecifyauniqueidentifierforthedevice. Theidentifierusedforeachmemorydevicewill beusedwhengeneratingheaderfilesfor inclusionintheEmbeddedSoftwareproject. Theidentifierswillalsobeusedtouniquely identifythecorrespondingoutputHEX files.This fieldcannotcontainspaces. Usedtospecifythetypeandrelativespeedof thememorydevice.Thememorytypecanbe eitherROMorRAM(volatileornonvolatile). Speedrangesfrom0(fastest)to5(slowest). TheLinkerusesthespeedsettingsforall definedmemoriestobestoptimizetheoverall performanceandefficiencyofthecode.

Type

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Option AddressBase

Description Usedtospecifythebaseaddressofthememory device.Internalmemorywillalwaysbeginat baseaddress0000_0000h.Theprocessors internalmemoryrangeis16MBandtheactual sizeofthephysicalRAMmappedintothisrange willbedrivenbyhowmuchphysicalBRAMis availableinthetargetFPGA. Baseaddressescanbespecifiedasdecimalor Hexnotation(e.g.10000,0x10000,1k,64k,1M). Usedtospecifythesizeofthememory.This valuecanbespecifiedasdecimalorHex notation(e.g.10000,0x10000,1k,64k,1M).

Size

7.2 Exercise11Configuringtheprocessormemory
InthisexercisewewillconfiguretheinternalmemoryoftheTSK3000tosuitourdesign. 1. RightclickU2andselectConfigureProcessorMemory tolaunchtheConfigure ProcessorMemorydialog 2. Enabletheoptiontogenerateahardware.h(CHeaderFile). 3. RightclickU2 inthelistofmemoriesandselectDeleteMemory.Oncedeletedwewill needtoaddourinternalmemories,thistimepartitionedasbothROMandRAMforour application. 4. ToaddtheROMandRAMblocksrequired,rightclickthelistofmemoriesandselect AddMemory ThiswilllaunchtheProcessorMemoryDefinitiondialog. 5. Specifyanewinternalmemorywiththenameirom,asaROMtype,withaSpeed of0 Fastest,beginningatbaseaddress0x0 and16Kbytesinsize. 6. Createasecondnewinternalmemorywiththenameiram,asaRAMVolatile type,withaSpeed of0Fastest,beginningatbaseaddress16k,and16 Kbytesinsize. Onceconfiguredproperly,theConfigureProcessorMemorydialogshouldappearasitdoes inFigure24.

Figure24.Dividinguptheprocessormemory.

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7.3 Configuringprocessorperipherals
Thoughwevealreadyspecifiedthedetailsofeachperipheralincludingtheirbuswidths,base addresslocations,etc.whenwehadconfiguredtheWishboneInterconnectcomponentU1, westillneedtospecifythisinformationattheprocessorend. Toconfigureprocessorperipherals,simplyrightclickthehostprocessorintheschematicand selectConfigureProcessorPeripheral ThiswilllaunchtheConfigurePeripherals dialogseeninFigure25.

Figure25.Configuringtheprocessorperipheralsattheprocessorend

PeripheralscanbeimportedintotheprocessorsIOspacebyselectingtheoptionImport FromSchematic.Thiswillpromptyouwiththeoptiontodeleteexistingperipheralsbefore importing,afterwhich,itwilllaunchtheChooseWishboneItemsdialogseeninFigure26. SelectImportundertheImporttoBusoptionforanyitemsyouwishtoimport.

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Figure26.Choosethewishboneperipheralstoimport

7.4 Exercise12Specifyingprocessorperipherals
InthisexercisewewillconfiguretheperipheralmemoryoftheTSK3000tosuitour design. 1. RightclickU2andselectConfigureProcessorPeripheral tolaunchthe ConfigurePeripheralsdialog. 2. Enabletheoptiontogenerateahardware.h(CHeaderFile). 3. SelecttheoptionImportFromSchematictoimporttheperipheralsfromthedesign. Aswevenotexistingperipheralsinourdesignitissafetodeletethesebefore importing. 4. SelecttheoptionImportjustbesideU2intheChooseWishboneItemsdialog.Thiswill causethestatusofallitemstochangetoImport.ClickingOKwillclosethedialogand thememorylistedintheConfigurePeripheralsdialogshouldnowappearasitdoesin Figure27.

Figure27.Processorperipheralsproperlyconfiguredforourapplication.

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8 FinalizingtheDesign,Compilingand ResolvingErrors
AtthisstagewehavesuccessfullycompletedtheFPGAportionofourdesign.Itisnowtime tocompiletheFPGAprojectandcorrectanyerrorsyoumighthaveinyourdesign. Once completed,savetheFPGAschematicandFPGAprojectbeforecontinuing.

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9 CreatingEmbeddedSystemsonFPGAs
AltiumDesignersupportsahierarchicalapproachtodesign,evenattheprojectlevelwith supportforthelinkingofmultipleprojectstooneanother.Thisincludestheabilitytolinkone ormoreFPGAprojectstoaPCBproject,aswellastheabilitytolinkanembeddedprojectto anyFPGAprojectthatusesasoftcoreprocessor. Inthissectionofthecoursewewillexplorethecreationofembeddedprojects,thedebugging ofsoftwarecodeusingasoftwaresimulator,andsomeofthemanyoptionstheTASKING toolset,includingthebestinclassVipercompilertechnologyafforduswhendesigningour applications. LikewisewewilldiscusslinkingembeddedprojectstoanFPGAprojectandtheprocessof buildingandrunningapplicationsrunningonanFPGA.

9.1 Exercise13EditorBasics
Inthisexercisewewillcreateasimpleembeddedprojectthatwewillusetoexploresomeof editoroptionsavailableinAltiumDesigner.Wewillalsousethisprojectlateraswelearnthe basicsofCompilingandDebuggingourcode. 1. FromtheFilemenu,selectNewProjectEmbeddedProject. 2. SelectthenewlycreatedembeddedprojectEmbedded_Project1.PrjEmbinthe ProjectspanelandaddanewCsourcedocumentusingFileNewCSource Document,orrightclickingtheprojectdocumentintheProjects panelandselecting AddNewtoProjectCFile. Thiswilllaunchablanktexteditorthatwewillusetoenterourapplicationcode.The buttonsalongthebottomofthesystemtrayandthemenusalongthetopwillchangeto includeoptionsappropriatefordevelopingourapplication. 3. IntheCodeeditor,enterthefollowing:
#defineBase_WB_PRTIO_10xFF400000 #defineSize_WB_PRTIO_10x00000001 #include"hardware.h" #defineLEDS(*(unsignedchar*)Base_WB_PRTIO_1) voidmain(void) { LEDS=0x55 }

Noticehowthecodeisautomaticallyformattedandthesyntaxisproperlyhighlighted fortheClanguage.AltiumDesignerscodeeditorfeaturesabroadrangeofpowerful syntaxhighlightingcapabilitieswithvirtuallylimitlessuserconfigurabilityavailableunder ToolsFormattingOptions.

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CodeFormattingGeneral

CodeformattingSpacing

AdditionalCodeFormatting&HighlightingoptionsareavailableunderToolsEditor Preferences

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PreferencesGeneral

PreferencesDisplay

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PreferencesColors

4. Iftimepermits,experimentwithsomeoftheeditorsettingstoseetheireffectonthe sourcecode.UseToolsFormatSourceCodeaftermakingeachchangetoupdate yoursourcecodeinthecodeeditor.

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9.2 TheTASKINGtoolchain
ManylongtimeusersofAltiumDesignerarefamiliarwithitsadvancedschematicandPCB capabilitiesandcanunderstandhowschematicbasedFPGAdevelopmentisanatural extensionofAltiumscoretechnologies.Delvingintotheworldofembeddedsystems programminghoweverrepresentsasignificantdeparturefromthishardwarefocus. Altium,throughtheircorporateacquisitionofTASKING,areamajorplayerintheembedded systemsmarketplace.TASKINGproductsareworldleadingtoolsforembeddedsoftware development,bringingtogethertheadvancedsoftwaredesigntechnologyneededtocompete intheembeddedsystemsmarketplace.TheawardwinningTASKINGintegrateddevelopment environment,compiler,debugger,embeddedInternetandRTOSofferingssupportawide rangeofDSPsand8,16and32bitmicroprocessorsandmicrocontrollersforallareasof embeddeddevelopment.Withover100,000licensedusersofTASKINGproducts,including theworld'sleadingtelecom,datacom,wirelessandperipheralmanufacturers,theTASKING productrangehasalonghistoryoftechnologyleadershipandinnovation.

9.3 TheBuildflow

Figure28.AlookattheTASKINGbuildflow.

Buildinganapplicationistheprocessofcompilingallofthetoplevelsourcedocumentsintoa binaryfilethatcanbeexecutedbyatargetprocessor. Thisisamultistepprocessinvolvinga numberoftools.Inmanysituations,theuserwillbeshieldedfromthedetailoftheunderlying compilationprocesseshoweverinsomecircumstancesitwillbenecessarytodiagnosethesource ofbuildorcompilationerrorsandforthisitisimportanttounderstandthecompilationflow.

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TheCcompiler,assembleranddebuggeraretargetdependent,whereasthelinkerandthe librarianaretargetindependent.TheboldnamesinFigure28aretheexecutablenamesof thetools.Substitutetargetwithoneofthesupportedtargetnames,forexample,c3000isthe TSK3000Ccompilerandc51isthe8051Ccompiler.

9.4 TargetingtheProject
Priortocompilinganembeddedproject,itisnecessarytonotifythecompilerwhichprocessor weintendtouseandanyspecialcompilationfeatureswemaywishtoinclude.Thisisdone viatheProjectOptionsdialogueboxthatcanbeaccessedbyrightclickingtheEmbedded ProjectintheProjectspanelandselectingProjectOptionspanelorbyselectingProject ProjectOptionsfromthemainmenu.

9.5 Projectoptions
TheOptionsforEmbeddedProjectdialogcontainstheconfigurationoptionsspecifictothe processofcompiling,linking,andlocatingyourdesign.Thisdialogalsocontainsother optionssuchastheoptiontospecifywhatprocessorisbeingtargeted,whetherornotto includetheDeviceSoftwareFramework(moreonthatlaterinthissection),aswellasother options.

9.5.1 Device
Selectfromarangeof8and32bitprocessorsincludingFPGAbasedandnonFPGAbased devices.CurrentlyAltiumDesignersupportsthefollowinglistofhardandsoftprocessors.

Processor
TSK51

Description
TheTSK51xisthecoreofafast,singlechip,8 bitmicrocontroller,whichexecutesallASM51 instructionsandisinstructionsetcompatiblewith the80C31.TheTSK51xservessoftwareand hardwareinterrupts,providesaninterfacefor serialcommunicationsandincorporatesatimer system. TheTSK52xisan8bitembeddedcontrollerthat executesallASM51instructionsandis instructionsetcompatiblewiththe80C31. TheTSK80xisafullyfunctional8bitembedded processorwhichisinstructionsetcompatible withtheZilogZ80CPU. TheTSK80xsupportshardwareinterrupts,halt andwaitstatesforlowspeedmemoryandI/O devices.

TSK52

TSK80

TSK165x

TheTSK165xisafullyfunctional,8bitcontroller thatemploysRISCarchitecturewitha streamlinedsetofsinglewordinstructions. TheTSK165xisinstructionsetcompatiblewith thePIC16C5Xfamily.Allinstructionsaresingle cycle,exceptforprogrambrancheswhichtake twocycles.

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Processor
TSK3000

Description
TheTSK3000Aisa32bit,Wishbone compatible,RISCprocessor.Mostinstructions are32bitswideandexecuteinasingleclock cycle.Inadditiontofastregisteraccess,the TSK3000Afeaturesauserdefinableamountof zerowaitstateblockRAM,withtruedualport access. TheTSK3000Ahasbeenspecificallydesigned tosimplifythedevelopmentof32bitsystems targetedforFPGAimplementationandtoallow themigrationofexisting8bitsystemstothe32 bitdomainwithrelativeeaseandlowrisk.Asa result,complicationstypicallyassociatedwith32 bitsystemdesign,suchascomplexmemory management,areminimized.

ActelCOREMP7

AltiumDesigner'sCoreMP7componentisa32 bitWishbonecompatibleRISCprocessor,for useinFPGAdesignstargetingsupportedActel FusionorProASIC3familiesofphysicalFPGA devices. AlthoughplacedinanAltiumDesignerbased FPGAprojectasaCoreMP7,thisisessentiallya Wishbonecompliantwrapperthatallowsuseof Actel'scorresponding'soft'CoreMP7processor core. Similarto(andfullycompatiblewith)the ARM7TDMIScoreprocessor,theCoreMP7is animplementationoftheARMarchitecture v4T.ThisRISCarchitecturesupportsboththe 32bitARMinstructionset,aswellasthe16bit Thumbinstructionset.

AlteraNIOSII

TheAlteraNiosIIisafullyfunctional,32bit load/store,Wishbonecompliantprocessorthat employsRISCarchitecturewithastreamlined setofsinglewordinstructions.NiosIIisfor useinFPGAdesignstargetingsupportedAltera familiesofphysicalFPGAdevices. Theprocessorcomesinthreeflavorsfast, standardandeconomy.Althougheachisplaced inanAltiumDesignerbasedFPGAprojectasa NiosII,thisisessentiallyaWishbonecompliant wrapperthatallowsuseofAltera's corresponding'soft'NiosIIprocessorcore. Allinstructionsare32bitswideandmost executeinasingleclockcycle(standardandfast variantsonly).Inadditiontofastregisteraccess, theNiosIIfeaturesauserdefinableamountof zerowaitstateblockRAM,withtruedualport access. TheNiosIIcoremustbelicensedfromAltera andmustbepurchasedseparately.

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Processor
AMCCPPC405CR

Description
AltiumDesigner'sPPC405CRcomponentisa 32bitWishbonecompatibleRISCprocessor. AlthoughplacedinanAltiumDesignerbased FPGAprojectjustlikeanyother32bitprocessor component,thePPC405CRisessentiallya Wishbonecompliantwrapperthatallows communicationwith,anduseof,thediscrete PowerPC405processorencapsulatedwithinthe AMCCPPC405CRdevice. Youcanthinkofthewrapperasbeingthe 'means'bywhichtofacilitateuseofexternal memoryandperipheraldevicesdefinedwithin anFPGAwiththediscreteprocessor. Mostinstructionsare32bitswideandexecutein asingleclockcycle.Inadditiontofastregister access,thePPC405CRfeaturesauser definableamountofzerowaitstateblockRAM, withtruedualportaccess.

NXP LPC2100

TheNXPLPCxxxfamilyofMicroprocessorsare 32bitARMbasedhardprocessordevices availablefromNXP(foundedbyPhillips). AltiumDesignerincludesfullapplication developmentanddebuggingtoolsforthese devicesthoughthereisnoWishbonewrapperfor useinconjunctionwithanFPGAdesign.These devices,whenconnected,willappearinthe harddeviceschainhowevertheywouldnotbe includedasacomponentinyourFPGA schematic. Additionalinformationanddatasheetsforthese devicescanbefoundonlineat http://www.nxp.com/.

SharpBluestreak

AltiumDesigner'sARM720T_LH79520 componentisa32bitWishbonecompatible RISCprocessor. AlthoughplacedinanAltiumDesignerbased FPGAprojectjustlikeanyother32bitprocessor component,theARM720T_LH79520is essentiallyaWishbonecompliantwrapperthat allowscommunicationwith,anduseof,the discreteARM720Tprocessorencapsulated withintheSharpBluestreakLH79520device. ThisdiscreteSharpBluestreakLH79520isa fullyintegrated32bitSystemonChip(SoC), basedonanARM720T32bitRISCprocessor core. Youcanthinkofthewrapperasbeingthe 'means'bywhichtofacilitateuseofexternal memoryandperipheraldevicesdefinedwithin anFPGAwiththediscreteprocessor.

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Processor
XilinxMicroblaze

Description
TheXilinxMicroBlazeisafullyfunctional, 32bitload/store,Wishbonecompliantprocessor thatemploysRISCarchitecturewitha streamlinedsetofsinglewordinstructions. MicroBlazecanbeusedonlywithFPGAdesigns targetingsupportedXilinxSpartanorVirtex familiesofphysicalFPGAdevices. AlthoughplacedinanAltiumDesignerbased FPGAprojectasaMicroBlaze,thisisessentially aWishbonecompliantwrapperthatallowsuse ofthe'soft'MicroBlazeprocessorcore. Allinstructionsare32bitswideandmost executeinasingleclockcycle.Inadditiontofast registeraccess,theMicroBlazefeaturesauser definableamountofzerowaitstateblockRAM, withtruedualportaccess.TheMicroBlazecore islicensedaspartoftheXilinxEDK(Embedded DevelopmentKit)andmustbepurchased separately.

XilinxPPC405A

ThePPC405Aisafullyfunctional,32bit load/store,Wishbonecompliantprocessorthat employsRISCarchitecturewithastreamlined setofsinglewordinstructions. AsthePPC405isimmersedinaVirtexIIPro device,onlydesignstargetingthisdevicemay makeuseoftheprocessor.Shouldyouwishthe freedomofadeviceandFPGAVendor independent32bitsystemhardwareplatform, usetheavailableTSK3000A32bitRISC processor. AlthoughplacedinanAltiumDesignerbased FPGAprojectasaPPC405A,thisisessentiallya Wishbonecompliantwrapperthatallowsuseof the'hard'PowerPC(PPC405)processorcore immersedinthetargetphysicaldevice. Mostinstructionsare32bitswideandexecutein asingleclockcycle.Inadditiontofastregister access,thePPC405Afeaturesauserdefinable amountofzerowaitstateblockRAM,withtrue dualportaccess.

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9.5.2 Processor

Figure29.TheProcessoroptionsintheProjectOptionsdialog

TheProcessorbuildoptionhassettingsforProcessorDefinitionusedtospecifyaparticular derivativeofagivenprocessorfamily(forexample,NiosIIe,NiosIIf,NiosIIs)ifavailableas wellasprocessorspecificoptionstoincludesuchthingsasamultiply/divideunit,floating pointunit,etc.dependingonthecapabilityofagivenprocessor. SomeprocessorfamiliesalsoincludeoptionalcontroloftheStartupCode.TheStartupcode isusedtoinitializetheprocessorandanypreinitializedvariablesbeforeexecutionbeginsat voidmain(void).Thoughthedefaultsaregenerallyacceptableforthemajorityof projects,shouldyoueverchoosenottoincludethedefaultstartupcodeproducedbythe compileryoucandisablethisoption.Youwillthenhavetoassumetheresponsibilityof handlingtheresetinterrupt,initializingmemoryvariables,andpassingcontroltothemain functionintheCsourcecode.

9.5.3 CCompiler
TheCompilerisfunctionallyresponsibleforparsingthehighlevelCsourcecommandsand reducingthemtoatomicoperationsthatcanbeeasilymappedontothetargetprocessors instructionset.Thisprocessinvolvesanumberofphasesincluding(butnotlimitedto): 1. Preprocessing 2. HighlevelOptimization 3. Instructionselection 4. PeepholeOptimization/InstructionScheduling 5. RegisterAllocation 6. LowlevelOptimization

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Duetothevastvariationinrequirementsandoptimizationgoals,itisnotpossibletohavea onesettingsuitsallcompiler.Subsequentlyanumberofcompileroptionsaremadevisible totheusersothatthecompilationprocesscanbetunedtothespecificapplication.Belowis ashortlistofonlyafewoftheseoptions.Formoredetaileddescriptionsoftheseandmore buildrelatedcommands,refertotheEmbeddedToolsReferencefortheselectedprocessor familylocatedinthesoftwareHelpdirectoryorontheAltiumwebsite.

Figure30.TheCompileroptionsintheProjectOptionsdialog

9.5.3.1 Preprocessing
Thissectionishelpfulifitisnecessarytodefinepreprocessormacrosthatwilldirect conditionalcompilationinthesource.Forexampleyoumaywishtodeclareamacrocalled DEBUG_MODEanduseconditionalcompilationinyoursourcecodedependingonwhetherthis macrowasdefined:
#ifdefDEBUG_MODE dosomething... #else donormalprocessing... #endif

Thissectioncanalsobehelpfulwhenchangingsomethingacrosstheentireproject.

9.5.3.2 Optimization
TheTASKINGCcompileroffers fivepreconfiguredoptimizationlevelsaswellasacustom level. Ateachlevelaspecificsetofoptimizationsisenabled.Generallythetradeoffis betweenspeedandsize. Codecanbeoptimizedforeitherspeedorsizehoweverthatcode optimizedforspeedisgenerallylarger,whereascodeoptimizedforsizeisgenerallyslower. Applicationsthathavenotbeenoptimizedwillgenerallyexecutemorequicklyhoweverthe amountofspacerequiredinmemorywillbemoresubstantial.Thereisalsothetradeoffwith respecttotheabilitytodebug.Highlyoptimizedcodeisdifficulttodebugastherelationship betweenthesourcecodeandthecompiledcodebecomesprogressivelymoredifficultto understand.

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Itissuggestedtobeginwiththefewestpossibleoptimizationsenabledandafterensuringthe codeiscorrect,progressivelyoptimizeyourapplicationuntilachievingtheidealrelationship betweenspeedandsize. Level0:Nooptimizationsareperformed.Thecompilertriestoachievea1:1resemblance betweensourcecodeandcompiledcode.Expressionsareevaluatedintheorderwrittenin thesourcecode,associativeandcommutativepropertiesarenotused.Compiledcode willgenerallyrunfasteratthislevelofoptimizationandperformancewilldecreaseasthe softwareisfurtheroptimized. Level1:Enablesoptimizationsthatdonotaffectthedebugabilityofthesourcecode.Use thislevelwhenyouaredeveloping/debuggingnewsourcecode. Level2:Enablesmoreaggressiveoptimizationstoreducethememoryfootprintand/or executiontime.Thedebuggercanhandlethiscodebuttherelationshipbetweensource codeandgeneratedinstructionsmaybehardtounderstand.Usethislevelforthose modulesthatarealreadydebugged.Thisisthedefaultoptimizationlevel. Level3:Enablesaggressiveglobaloptimizationtechniques.Therelationshipbetween sourcecodeandgeneratedinstructionscanbeveryhardtounderstand.Usethislevel whenyourprogramdoesnotfitinthememoryprovidedbyyoursystem. Level4: Fullyoptimizeforsize.Thisisthemostaggressivelevelofoptimizationand shouldonlybeusedoncetheapplicationhasbeencompletelydebugged.Theapplication mayexecutemoreslowlyhoweveritsmemoryfootprintcanbefarlesssubstantial. Customlevel:youcanenable/disablespecificoptimizations.

9.5.3.3 Language
Defaultsettingsareusuallyadequatehoweveroccasionallyyoumaywishtobuildcodethatis preISOC99compatibleandwillthereforeneedtheoptionscontainedinthispanel. This panelalsocontainsoptionstoallowuseofGNUCextensionsifdesired.

9.5.3.4 Debuginformation
Ingeneralitishelpfultoalwaysgeneratedebuginformationunlessbuildingforafinal productionreleasewheredebuginformationwouldbesuperfluous.Youmightalsodisable thisoptionifyouintendtomakeyourcodeavailableasalibraryandwouldprefertoprotect yourIP.

9.5.3.5 Floatingpoint
IngeneralthedefaultsettingsareacceptablethoughtheoptiontoUsesingleprecision floatingpointonlycanaffectboththesizeandexecutionspeed.Whenchecked,variables ofthetypedoublewillbetreatedasfloat.Selectthisoptionintheeventyoudonotrequire doubleprecision.

9.5.3.6 Diagnostics
Thissectioncontrolshowcompilationwarningsarereported.Insomecasesitmaybe desirabletosuppressspecificwarningsiftheyarecreatingtoomuchnoiseintheMessages Panel.

9.5.3.7 MISRAC&MISRACRules
TheMotorIndustrySoftwareReliabilityAssociation(MISRA)isinexistenceToprovide assistancetotheautomotiveindustryintheapplicationandcreationwithinvehiclesystemsof safeandreliablesoftware.Throughextensiveconsultationwithintheautomotiveindustry, MISRAhascompletedthedevelopmentofguidelinesspecificallyaimedattheuseoftheC languageinsafetyrelatedsystems.TheseguidelinesprimarilyidentifythoseaspectsoftheC languagethatshouldbeavoidedinsafetyrelatedsystems,alongwithother

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recommendationsonhowotherfeaturesofthelanguageshouldbeused.Itisanticipatedthat theguidelineswillbeadoptedforembeddedCprogrammingthroughouttheautomotive industry. AltiumDesignerincludesanumberofcompilationoptionsthatcanflagasawarningcodethat doesnotcomplywithMISRArecommendations.

9.5.3.8 Miscellaneous
Usethissectiontopassanycompilerflagsorsettingsthathavenotbeencoveredinthe previouspanels.TheOptionsStringatthebaseofthecompilersettingspanelprovidesan indicationoftheoptionsthatwillbepassedtotheCcompiler.Furtherinformationabouteach individualsettingcanbefoundinGU0105EmbeddedToolsUsersGuide.pdforviathehelp systemunderEmbeddedSoftwareDevelopmentEmbeddedToolsOptionsReference CompilerOptions.

9.5.4 Assembler
Theassemblerconvertshandwrittenorcompilergeneratedassemblylanguageprograms intomachinelanguage,usingtheIEEE695objectformat.Thesefilesserveasinputforthe linker.

9.5.4.1 Phasesoftheassemblyprocess
1. 2. 3. 4. 5. Preprocessdirectives Checksyntaxofinstructions Instructiongroupingandreordering Optimization(instructionsizeandjumpstobranches) Generationoftherelocatableobjectfileandoptionallyalistfile

TheProjectOptionsdialogueboxcontainsanumberofassembleroptions.The subsectionsoftheassembleroptionsallowforadditionalcontrolovertheassemblerinmuch thesamewaythatthepreviouslymentionedcompileroptionsdo. Thedefaultoptionsaregenerallysufficientformostapplications.However,shouldyoufindit necessarytotunetheassemblerfurtherinformationcanbefoundintheEmbeddedTools ReferenceforthetargetprocessoravailableunderthehelpsystemorontheAltiumwebsite.

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Figure31.TheAssembleroptionsintheProjectOptionsdialog

9.5.5 Linker
Thelinkercombinesandtransformsrelocatableobjectfiles(.obj)intoasingleabsolute objectfile.Thisprocessconsistsoftwophases:thelinkingphaseandthelocatingphase. Inthefirstphasethelinkercombinesthesuppliedrelocatableobjectfiles(.objfiles, generatedbytheassembler)andlibrariesintoasinglerelocatableobjectfile.Inthesecond phase,thelinkerassignsabsoluteaddressestotheobjectfilesoitcanactuallybeloadedinto atarget. Thelinkercansimultaneouslylinkandlocateallprogramsforallcoresavailableonatarget board.Thetargetboardmaybeofarbitrarycomplexity.Asimpletargetboardmaycontain onestandardprocessorwithsomeexternalmemorythatexecutesonetask.Acomplextarget boardmaycontainmultiplestandardprocessorsandDSPscombinedwithconfigurableIP coresloadedinanFPGA.Eachcoremayexecuteadifferentprogram,andexternalmemory maybesharedbymultiplecores. Mostlinkeroptionscanbecontrolledviatheprojectoptionsdialogbutsomeoptionsareonly availableascommandlineswitches.Thedefaultoptionsaregenerallysufficientformost applicationshowevershouldyoufinditnecessarytotunethelinkerthenfurtherinformation canbefoundintheEmbeddedToolsReferenceforthetargetprocessoravailableunderthe helpsystemorontheAltiumwebsite.

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Figure32.TheLinkeroptionsintheProjectOptionsdialog

9.5.6 DeviceSoftwareFramework
AltiumDesignersDeviceSoftwareFramework(DSF)hasbeendesignedtodramatically simplifyembeddedapplicationdevelopmentintheAltiumDesignerenvironment. TheDeviceSoftwareFrameworkdelivers: ALowLevelPeripheralInterface(LLPI)layer,withtightintegrationbetweenthe FPGAperipheralsandtheirdrivercode. AProcessorAbstractionLayer(PAL)greatlysimplifiestheportabilityofyour embeddedapplicationacrossalltargetprocessors,bothembeddedanddiscrete32 bit,supportedbyAltiumDesigner. WhiletheDSFabstractsawaymostofthephysicallayerfromtheembedded applicationdevelopmentprocess,youcontinuetohavedirectaccesstothe processorsinterruptsystem.

IncludedintheDeviceSoftwareFrameworkarethelowleveldriversrequiredtosupportthe peripheralcoresbundledwithAltiumDesigner.TheavailabilityoftheProcessorAbstraction Layerensuresthatwhenutilizingtheseperipherals,itispossibletochange32bitprocessors withlimitedimpacttotheoverallsystem. DeviceSoftwareFrameworksourcefiles(thelowleveldriverssuppliedwithAltiumDesigner) arestoredintheapplicationdirectoryunderC:\ProgramFiles\AltiumDesigner 6\System\Tasking\dsf\ HereyouwillfindalloftheCsourcefilesaswellastheirassociatedheaderfiles.Though thesefileswillnotbecopiedtotheprojectuponcompile,theywillbeincludediftheoptionto utilizetheDeviceSoftwareFrameworkisenabled.

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TousetheDeviceSoftwareFrameworkandtheassociateddriverfiles,youmustincludethe followinglinesinaCsourcefilewithinyourembeddedproject:
#defineDSF_IMPLEMENT #include"dsf_system.h"

ThiswillenabletheLowLevelPeripheralInterface.ToenabletheProcessorAbstraction LayeryoumustchecktheembeddedprojectoptionUseProcessorAbstractionLayerin project.Thiswillmakethedesignmoreeasilyportablebetweenprocessorsasthiswill abstracttheinterfaceoftheprocessorfromtheperipheralsyouincludeinthedesign. Figure33highlightssomeofthedifferencesbetweentraditionalembeddedsystemsand thosewhichutilizeDSF.

Figure33.DifferencesbetweenatraditionalembeddedapplicationandDeviceSoftwareFramework

TheDSFallowstheembeddedapplicationtobeportablebetweenprocessors,insteadof beingtightlycoupledtothehardwareasitisinthetraditionalapproach.

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Figure34.TheDeviceSoftwareFrameworkoptionsintheProjectOptionsdialog

9.5.7 POSIXConfiguration
AltiumDesignerincludessupportforaPOSIXcompliantMinimalRealTimekernel, supportingthePOSIX.13PSE51RealTimeprofile.Thismeansthattheimplementation supportstherequiredinterfacesreferencedintheappropriatestandardizedprofile.These interfacessupportthefunctionalbehaviorandanyadditionalconstraintsoroptionsas describedintheappropriatebasestandard. ToutilizethePOSIXkernel,checktheoptionCompileprojectasaPOSIXapplicationand selecttheUnitsofFunctionality,OptionRequirements,andImplementationDefined Constantsrequiredbyyourapplication.

Figure35.ThePOSIXoptionsintheProjectOptionsdialog

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9.6 AttachinganembeddedprojecttoanFPGAproject
Creatingalinkbetweenthesoftcoreandits associatedembeddedcodeensuresthat correctcode/processorcouplingismade.It alsoensuresthatsubsequentprojectbuilds incorporateallhardwareandsoftwarechanges thathavebeenmade. TheprocessoflinkinganFPGAProjecttoits associatedembeddedcodefirstrequiresthat bothprojectsareopentogether.Figure36 showstwoprojectsopentogetherpriortobeing linked.Thesetwoprojectsarenotboundin anyway. TolinktheEmbeddedProjecttotheFPGA ProjectwemustutilizetheStructureEditor.

Figure36.Unlinkedprojects

FileView

StructureEditor

Figure37.Linkedprojects(FileView).

Figure38.Linkedprojects(StructureEditor).

IntheFileView,filesaregroupedprimarily accordingtowhichprojecttheyareapartof andsecondarilyaccordingtothefiletype schematic,PCB,settings,etc.

IntheStructureEditor,thehierarchicallinkage betweenprojectsisshowni.e.abovewesee thattheembeddedprojecthasbeenlinkedto U3(theTSK3000Acore)intheFPGAproject.

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9.6.1 Linkingtheprojects
Linkagebetweenprojectsiscreated andbrokenusingdraganddrop.By clickandholdingtheleftmouse buttononasubproject,allpossible droplocations(validlinkagepoints) willhighlightinblueandthesub projectcanbedraganddroppedonto theparentprojecttocreatethelink. Tobreakthelinkage,dragthesub projectawayfromtheparentproject anddropitonaclearregionofthe StructureEditor. Alternativelyyoucanrightclickonthe processorandspecifytheembedded projectusingtheSetEmbedded Projectmenuoption.

Figure39.Linkinganembeddedprojecttoitshardware

Figure40.Linkinganembeddedprojecttoaprocessorviatheschematicinterface

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9.7 Exercise13Linkingprojects
Inthisexercisewewilllinkourtwoprojectstooneanother. 1. WithbothyourFPGAandEmbeddedprojectsloadedintheProjectspanelchangeto theStructureEditorview. 2. Linkthetwoprojectsasdescribedintheprevioussection. 3. OncetheprojectshavebeencorrectlylinkedreturntotheFileViewandtheprojects shouldappearlinked. 4. Youcantryunlinkingthetwoprojectsagainbydraggingthelinkedembeddedproject offofU2inthestructureeditor. 5. Saveyourwork.

9.8 Exercise14Buildingourdesign
Inthissectionwewillconfigureourdesignforthebuildprocessandsubsequentlybuildboth ourFPGAprojectandembeddedprojects,programmingtheSpartan3FPGAontheDesktop NanoBoard. 1. AutoConfiguretheFPGAproject. 2. RightClicktheFPGAProjectintheProjectspanelandSelectAddNewto ProjectConstraintFiletoaddanewblankConstraintfiletotheproject. 3. Intheconstraintfile,addanewportconstraintthatconstraintsCLK_BRDwitha constraintkindofFPGA_CLOCK_FREQUENCYwithavalueof50MHz.

4. MakesureyourDesktopNanoBoardisconnectedtoyourPCandpoweredon. 5. EnsurethattheLivecheckboxischecked.YoushouldseeapictureoftheDesktop NanoBoardintheupperregionofthedisplayandaniconoftheSpartan3FPGAinthe middleregion. 6. InthedropdownlistjustbelowtheSpartan3icon,ensurethatthe CHC_image_rotation/NBD2DSK01_07_DB30_04project/configurationpairis selected. 7. ClickonceonthewordsProgramFPGAtobeginthebuildprocess. 8. Asthebuildprocessprogresses,thecoloredindicatorfromeachstagewillturnyellow whileitisprocessingandthengreenwhencompletedsuccessfully.Theprocessof buildingthedesignmaytakeseveralminutestocomplete.Youcanobservethe progressofthebuildfromtheMessagesandOutputpanelswhichcanbeaccessed fromtheSystemPaneltabinthelowerrightsectionoftheAltiumDesignerworkspace (seeFigure41).

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Figure41. BuildingtheFPGAdesign

9. Ifanyerrorsoccuryouwillneedtorectifythembeforeyoucanproceed.Trytolocate thesourceoftheerrorbyretracingyourstepsthroughtheinstructionsofthetutorial. 10. Asummarydialogwillbedisplayedoncethedesignhasbeenbuiltanddownloaded successfully.ClickOKtoclosethisdialog. OncetheFPGAdesignhas beendownloadedtothe DesktopNanoBoard,you shouldnoticethatthestatus oftheTSK3000processor haschangedfromMissing toRunning.

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11. Atthisstageourdesignhasbeendownloadedtothe NanoBoardandtheLEDsshoulddisplayabinary patternconsistentwiththehexvalue0x55thatwe hadspecifiedinoursourcecode(lefttorightthe LEDsshouldread01010101b or85dwiththeLSB beingtherightmostbitntherowofLEDs).

9.9 Exercise15UpdatingoursoftwareLive
Inthisexercisewewillmakechangestothesoftwarerunningonthehostprocessorinside theFPGAontheNanoBoard,thenupdatethesesoftwarechangestotheprocessorasit executesinsystem,inrealtime. 1. WiththeFPGAandProcessorsuccessfullyprogrammedonourNanoBoard,openthe main.CfileintheEmbeddedProject.PrjEmbfile. 2. Modifythefunction main toread:
voidmain(void) { LEDS=0xFF }

3. UpdatingthesoftwarerunningontheNanoBoarddoesnotrequireustoreprogramthe FPGA,onlytoupdatethesoftwareonrunningontheprocessor. PresstheCompileandDownloadbutton inthetoolbaratthetopofthescreento recompilethesoftwareandupdateyourchangestotheprocessorrunningonthe FPGA. ThisshouldchangethestateoftheLEDsontheNanoBoardsuchthattheyappeartoallbe on.

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10 UpdatingtheDesigntoDisplayVideo
Inthissectionwewillmodifythesoftwaretoreadvideofromthecompositevideoinputand outputthatvideoonthetouchscreendisplay.Wewillthenexploresomeofthesoftware debugcapabilitiesfoundintheAltiumDesignerenvironmentandemployourvirtual instrumentstotestourdesignLive,insystem.

10.1 DefiningSections
Itissometimesusefultodefinememorysectionsinembeddedsoftware.Sectionsarea referencetoaspecificlocationinmemorythatcanbepassedtothelocatortocontroltheway thataprogramislocatedorusesmemory. SectionsarecreatedfromtheProjectOptionsdialogfortheembeddedproject.Tocreatea section,launchtheProjectOptionsdialogandselectthetabSections/ReservedAreas. TheAddSectionbuttonisusedtoaddanewsectionandwilllaunchtheSectiondialog. TheAddReservedAreasbuttonisusedtocreatenewreservedareasthatorareasthatwill notbeusedduringtheLinkingandLocatingprocess.

Figure42. Creatingsectionsforthelocator

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ThefollowingtabledetailsthevariousoptionsintheSectiondialog. Option Name Location Description Thenamefieldisusedasalabelorreferencetothe sectiondefinedinthesourcecode. Thisistheprocessorsviewofwherethesectionappears intheaddressspace.Thesizeofthesectionis automaticallyallocated. Thelocationcanbespecifiedasadecimalorhexvalue, oramemory. LocateStaticData FillBitPattern UsedtolocatetheROMinitializationdataforthesection. Unchecktolocatethesectionitself. Usedtoinitializetheemptyspacesattheendofa sectionasaresultofanMAUalignment.Ifthesectionis inROM,leavingthisblankwillfillthesectionwithzeros. IfitisinRAM,thespacesarenotinitialized. Ifchecked,anydependenciesofthesectionwillalsobe locatedbythissectionlayoutdirective. Usedtoaddanyusernotesthatmighthelpexplainor describethesection.

Dependencies Notes

10.2 Exercise16UpdatingoursoftwareLive
Inthisexercisewewillcreatetwosections,thenamesofwhichwillbelabelsthatcanthenbe usedasaqualifierwhenwecreateanarrayforthevideocaptureandvideodisplaybuffers. TheadvantagetoSectionsisinthefinercontrolitgivesoverthewayinwhichaprogramis Locatedandusesmemory.Sectionscanbecreatedandevennestedtomakeanalmost hierarchicalpartitioningofadesignsmemoryresourcespossible. 1. RightclicktheembeddedprojectintheProjectspanelandselectProject>>Project Options. 2. SelecttheConfigureMemorytabandobservethatentriesforXRAM1(theVideo Capturesideofourdesign)andXRAM2(theVideoDisplaysideofourdesign)exist. 3. SelecttheSections/ReservedAreastaboftheOptionsforEmbeddedProject CHC_Image_Rotation.PrjEmbdialog. 4. ClicktheAddSectionbuttontolaunchtheSectiondialog. 5. IntheSectiondialogbox:

a. SettheNameto.bss.video b. SettheLocationtomem:XRAM1
6. ClickOKtoclosetheSectiondialogboxandobservethatthenewmemorysectionhas beenadded. 7. ClicktheAddSectionbuttonagain 8. IntheSectiondialogbox:

a. SettheNameto.bss.tft b. SettheLocationtomem:XRAM2
9. ClickOKtoclosetheOptionsforEmbeddedProjectCHC_Image_Rotation.PrjEmb dialog.

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10.3 Exercise17UpdatingourSoftwaretoCaptureVideo
Inthisexercisewewillupdateourapplicationcodewiththesoftwarerequiredtocaptureand displayvideo.UtilizingtheDeviceSoftwareFramework,muchoftheprocessofinitialization andthelowlevelinteractionwiththehardwarewillbesimplified.Weinsteadwill communicatewiththehardwarethroughitsLowLevelPeripheralInterfacelayerwed discussedearlier.Thisdramaticallyreducestheamountofeffortrequiredingettingour systemofftheground. 1. Openmain.Candremoveanyexistinglinesofcodethatmightbeinthefile. 2. LaunchtheSnippetspanelunderSystemSnippetsusingthebuttonsalongthelower rightcorneroftheworkspace. 3. LocateandAddtheSnippetVideo_Pass_Through_1tomain.C.Thiscontainsthe #definesthatspecifythebasiccharacteristicsofthevideoincludingitsheight,width, screenresolution(bothXandY)andtheattributesrequiredtoproperlycenterthe imageonthescreen. Thissectionalsocontains#pragmasforboththevideoanddisplaymemories,usedto definethesizeoftheSectionsrequiredbythesetwobuffers. 4. ReturntotheSnippetspanelandaddtheSnippetVideo_Pass_Through_2tomain.C (thepositionofthecursorinthetexteditorwilldeterminethepointatwhichtheSnippet isinserted). 5. Ifthecodeappearsunformatted,selectToolsFormatSourceCodeanditwillbe formattedautomaticallytomatchyourformattingstandardsspecifiedunder ToolsFormattingOptions Examinethesourcecodeinthefunctionvoidmain(void).Thecodeisquitesimple really. 6. HoldingtheCtrlkeyonyourkeyboard, hoveryourcursoroverthevarious functionnameslistedinthe initializationsections.Youwillseethe cursorchangetoasmallhand. 7. Clickingonthenameofoneofthese functionswhilstinthismodewillopen thesourceDeviceSoftware Frameworksourcefilecontainingthe functionbeingreferenced.Weare essentiallycallingaseriesofDSF functionsandpassingthem parametersthatsimplifythe initializationandcontrolofthe behavioroftheperipherals. 8. Rebuildanddownloadyoursourcecodebyhittingthe buttoninthetoolbaralong thetopoftheworkspace.Thiswillautomaticallysavethesourcefileatthesametime. VideoshouldnowdisplayfromyourcameraonthescreenonyourNanoBoard.Trymoving thecameraandhavealookaround.

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10.4 UtilizingtheVirtualInstruments
Toachieveanunderstandingofhowourdesignmightfunctioninitsfinalimplementationi.e.the realworld,AltiumDesignerprovidesahostofVirtualInstrumentsthatcan,utilizingFPGA resources,beusedtotestanddebugoursystemlive.Amajoradvantageofthisapproachisthat theinteractioniswiththerealhardwareandnotasoftwaresimulator.Thisallowsustofindand correctlogicerrors,aswellasissueswiththesoftware,onthephysicalhardware,inrealtime. Furthertothis,utilizingthismethodologyandtheinherentlyreprogrammablenatureofthe FPGAplatform,itiseasytoseehowwemightlateruseinstrumentationinourdesign,even afterithasbeenfullyimplemented,totestourdesign,insystem,andpossiblyevenother componentsofoursystem.

10.5 Usinginstrumentstocontrolourdesign
Theinstrumentswewillusewillprovideusamethodwithwhichtocontrolourdesignand affordusanunprecedentedviewintothesignalsinsideourdevice,inrealtime.Belowisa listoftheinstrumentswewillutilizeforthisnextsection:

Instrument
ConfigurableDigitalIO
ConfigurableDigitalIO InLEDs[7..0] Rot[7..0] SpareOutB[7..0] Zoom[7..0] SpareOutC[7..0] Flags[7..0] SpareOutD[7..0]

Role
WewillutilizetheConfigurableDigitalIO componenttocontroltherotationandscalingofour imageontheTFTdisplay.

LogicAnalyzer1kx8
U16 LogicAnalyser1kx8 CLK STATUS CLK_CAP EXT_TRIGGER Measure LEDS[7..0] LAX

WewillusetheLogicanalyzertomonitorthe signalscomingoutoftheWishbonePortIO componentspecificallythosebeingsenttothe LEDsontheNanoBoard.

FrequencyGenerator
U19 TIMEBASE FREQ

WewillusetheFrequencyGeneratortocreatea timebaseforourLogicAnalyzer.

FrequencyGenerator CLKGEN

FrequencyCounter
U18 FREQA FREQB TIMEBASE FrequencyCounter FRQCNT2

WewillusetheFrequencycountertowatchthe timebasegeneratedbyourFrequencyGenerator andthesignalbeingoutputtotheLEDs.

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10.6 Exercise18UpdatingtheWishbonePortIO
Priortoaddingtheinstruments,weneedtomakeamodificationtoourdesign.Specifically, weneedaddafewadditionalIOportstotheWishbonePortIOcomponent. TheseIOports willbeusedtointerfacetheinstrumentstoourdesign. Inthisexercisewewillupdateour WishbonePortIOthePeripheralInterconnectcomponents. TheseportswillbeusedbythehostprocessortoreadtheRotationandScalingvalues from theDigitalIOinstrument. WewillalsoincludesomeinputFlagsthatoursoftwarecanrigger offof. Additionaloutputswillalsobeusedtooptionallydisplaytherotation,scaling,andflag valuesasbinaryvaluesontheDigitalI/Ocomponent(thusgivingussomevisibilityintojust whatoursettingsare). 1. DoubleclicktheConfigurableWishbonePortI/OcomponentU14andhittheConfigure buttonintheComponentPropertiesdialogorrightclickU14intheschematicand selectConfigureU14(WB_PRTIO). 2. ChangethePortCountvalueto4.Thiswillgiveus4inputports,each8bitswide, and4outputports,also8bitswide. 3. WenowneedtoupdateourWishboneInterconnectcomponenttobeabletoaddress eachofthese4differentI/Oports.TodosodoubleclicktheWishboneInterconnect componentU1andhittheConfigurebuttonintheComponentPropertiesdialogor rightclickU1intheschematicandselectConfigureU1(WB_INTERCON). 4. HighlightGPIOinthelistofperipheralsandselecttheEditDevicebuttonatthebottom. 5. EdittheAddressBusWidthto2BitsRange=4.Thiswillallowustoaddresseach ofthe4I/Oportsfromtheprocessor. 6. AnewaddresspinwillappearontheWishboneInterconnectandtheWishbonePort I/Ocomponent(s2_ADR_O[1..0]andADR_I[1..0]respectively).UsingPlaceBus,wire thesetwopinstooneanother. 7. AdditionalpinshavealsobeenaddedtotheleftoftheWishbonePortIOcomponent. Wirethesepinsandverifythewiringmatchestheimagebelow.

Figure43.PlacingandwiringthewishboneportIO.

NowwiththeWishbonePortI/OandWishboneInterconnectcomponentsupdatedwecan begintheprocessofaddingtheVirtualInstrumentstoourdesign.Inthefollowingexercises wewilladdeachoftheinstrumentsweintendtouse.

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10.7 Exercise19AddingtheVirtualInstruments
1. GototheLibrariespanelandplacethecomponentDIGTAL_IO.Designatethis componentU11. 2. RightclickthiscomponentandselectConfigureU11(DIGITAL_IO) Configurethe componentasitappearsinFigure44.

Figure44.DigitalIOcomponentconfiguredforthedesign

3. WirethecomponentasindicatedinFigure45.Thiswilltietogetherthesignalsonour WishbonePortIOdeviceandtheConfigurableDigitalIOinstrument.

LEDs[7..0] SpareOutB[7..0] SpareOutC[7..0] SpareOutD[7..0]

ConfigurableDigitalIO InLEDs[7..0] Rot[7..0] SpareOutB[7..0] Zoom[7..0] SpareOutC[7..0] Flags[7..0] SpareOutD[7..0]

Rotation[7..0] Zoom[7..0] Flags[7..0]

Figure45. WiringfortheconfigurabledigitalIO

4. PlacetheclockgeneratorcomponentCLKGEN,designatingthiscomponentU19 5. PlacethefrequencycountercomponentFRQCNTanddesignatethiscomponentU18 6. WirebothcomponentsastheyappearinFigure46.

U18 U19 CLK TIMEBASE FREQ LEDs0 LAX_CLK CLK FREQA FREQB TIMEBASE FrequencyCounter FRQCNT2

FrequencyGenerator CLKGEN

Figure45. Wiringforthefrequencygeneratorandfrequencycounterinstruments

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7. PlacethelogicanalyzercomponentLAX,designatingthiscomponentU42. 8. ConfiguretheLAXwithonesignalsetMeasure,andasinglesignalLEDS[7..0]asseen inFigure46.

Figure46.LAXconfiguredtocaptureinputfromtheLEDS

9. WiretheLAXasitappearsinFigure47.

U16 CLK LAX_CLK LEDs0 LEDs[7..0] LogicAnalyser1kx8 CLK STATUS CLK_CAP EXT_TRIGGER Measure LEDS[7..0] LAX

Figure47. WiringfortheconfigurableLAX

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10.8 Exercise20Rebuildingtheprojectwithinstruments
1. MakesureyourDesktopNanoBoardisconnectedtoyourPCandpoweredon. 2. SelectView>>DevicesVieworclickontheDevicesViewicon inthetoolbar. 3. EnsurethattheLivecheckboxischecked.YoushouldseeapictureoftheDesktop NanoBoardintheupperregionofthedisplayandaniconoftheSpartan3FPGAinthe middleregion. 4. InthedropdownlistjustbelowtheSpartan3icon,ensurethatthe CHC_image_rotation/NBD2DSK01_07_DB30_04project/configurationpairis selected. 5. LocatetheCompile,Synthesize,Build,ProgramFPGAbuttonsrunninglefttoright justbelowtheDesktopNanoBoardicon.ClickonceonthewordsProgramFPGAto beginthebuildprocess.

10.9 Updatingourembeddedprojecttousetheinstruments
Tomakeuseofthevirtualinstrumentswewillrequiresomechangestotheapplicationcode inourembeddedproject.Thisincludesapieceofsoftwarethatmakeszoomingandscaling dependentonthetwoslidersweveaddedusingourConfigurableDigitalIOInstrument.In thissectionwewillmodifyoursoftwareandembeddedprojecttogetthevideoworkingwith ourinstruments.

10.10

Exercise21AddingAdditionalSourceFiles

Tofurthersimplifyourembeddedprojectwewilldosomesimplepartitioning.Thismakes thesourcefileseasiertoreadandmanageandmakesourfilesfarmorereusable. 1. RightclicktheembeddedprojectEmbeddedProject.PrjEmbandselectAddNewto Project.AddanewHFile. 2. AddthecontentsofthesnippetSpinning_Video_Defines_Header tothissource file. 3. Savethefileasdefines.h. 4. RightclicktheembeddedprojectEmbeddedProject.PrjEmbandselectAddNewto Project.AddanewHFile. 5. AddthecontentsofthesnippetSpinning_Video_DSF_Headertothissourcefile. 6. Savethefileasdsf.h. 7. RightclicktheembeddedprojectEmbeddedProject.PrjEmbandselectAddNewto Project.AddanewCFile. 8. AddthecontentsofthesnippetSpinning_Video_DSF_SourceFiletothissource file. 9. Savethefileasdsf.c.

10.11

Exercise22Updatingmain.c

Inthisexercisewewillupdatemain.ctoincludetheapplicationcodenecessarytorespond toourinputsandrotateandscaleourvideo. 1. Openthemain.csourcefileintheprojectEmbeddedProject.PrjEmb 2. Selectanddeleteallofthesourcecodelocatedinthisfile. 3. AddthecontentsofthesnippetSpinning_Video_main_SourceFile tothissource file. 4. Savethefileasmain.c 5. SavetheembeddedprojectEmbeddedProject.PrjEmbbyrightclickingtheproject documentintheProjectspanelandselectingSaveProject.

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6. Returntomain.candpresstheCompileandDownloadbutton inthetoolbarat thetopofthescreentorecompilethesoftwareandupdateyourchangestothe processorrunningontheFPGA. 7. Withtheaidofyourinstructor,havealookatthesourcecode.Thebulkofthe capabilityrestsinthemain.Cfile.

10.12 Exercise23Controllingourdesignwithinstruments
InthisexercisewewillfamiliarizeourselveswiththeinterfacetotheDigitalIOVirtual Instrument. 1. SwitchtotheDevicesViewunderViewDevicesViewsorbyhittingthe buttonin thetoolbaratthetopofthescreenSelectanddeleteallofthesourcecodelocatedin thisfile. 2. ThesoftnexusJTAGchainshoulddisplayalloftheinstrumentsweveaddedtoour design,aswellasthehostprocessor.

Figure48.Softdeviceschainshowstheinstrumentsinourdesign

3. RightclicktheU11DIGITAL_IOandselectInstrumenttolaunchtheInstrumentRack forthissoftdevice.

Figure49.InstrumentrackfortheconfigurableDigitalIO

TheINPUTSregionoftheinstrumentpanel allowsyoutomonitorthedigitalsignalsthat havebeenwiredtotheinputchannelsofthe DIGITAL_IOinstrument. 4. ClickontheOptionsbutton,atthebottom leftofthepanel,toaccesstheDigitalI/O ModuleOptionsdialog.Thedisplayfor eachinputisrefreshed(updated)inaccordancewiththevaluespecifiedintheUpdate DisplayFromCoreEveryfieldofthisdialog. 5. MovethesliderRot[7..0]totherightandobservetheimagerotatingontheTFT. 6. MovethesliderZoom[7..0]totherightandobservetheimagescalingontheTFT.

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7. Recallinoursourcecodewehascreated2conditionsforFlags[7..0].Thefirst conditionwasintheformofanIfElsestatementthatread:
if(Flags&0x01) alpha+=Rotation else alpha= Rotation<<1 alpha= alpha>=360?0:alpha

Ifbit0ofthearrayFlags[7..0]isset,theimagewillcontinuetorotate(thevariable Rotation referstotheBinputPBI[7..0]ofourWishbonePortIOcomponent). 8. Settherightmostbit(theLSB)ofFlags[7..0]toseetheimageontheTFTchangetoa stateinwhichitisrotatingcontinuously. 9. RecallinoursourcecodethatwehadasecondconditioncontrolledbyFlags[7..0],this timecontrollingourscalingoftheimage:

if(Flags&0x02) { scale+=delta*Zoom if(scale>1024) delta=1 if(scale<256) delta=1 } else scale=256+Zoom*3

Underthiscondition,thesecondbitofFlags[7..0]willcausethescalingtocontinueto bothincreaseanddecrease. 10. SetthesecondbitofFlags[7..0]andnoticetheimagechangestobothincreaseand decreaseinacontinuousmotion. 11. Timepermitting,experimentwithsomeoftheotherinstrumentsinthedesign.

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11 RealtimeDebuggingofaProcessor
AltiumDesignerincludesarangeoftoolstodebugoursoftprocessor.Thisincludesamore traditionalsimulationenvironmentaswellassupportfordebuggingrealsoftware,onreal hardware,inrealtime.ItisthiscapabilitythatcoupledwiththeVirtualInstruments,sets AltiumDesignerapart. InthissectionwewilldiscusssomeofthesoftwaredebuggingtoolsavailabletoyouinAltium Designer.

11.1 OnChipDebugging
Eachofthemicroprocessor/microcontrollercoressuppliedwithAltiumDesignerinclude supportforOnChipDebugging(OCD). The8bit microcontrollerswillutilizeaseparate schematicsymbolwithan_Dappendedtotheschematicsymbolnametodistinguishthe OCDandnonOCDversionsofthecomponent.Whereasthe32bitprocessorscontainan optionintheirrespectiveconfigurationdialogstoincludeOnChipDebuggingresources. TheOCDsystemisnecessaryifyouwishtomakeuseofAltiumDesignerslivedebugging features.Onenotabledifferencebetweenthetwovariationsofmicroprocessors/ microcontrollersistheexistenceofprogrammemory writeresourcesontheOCDversion. Thisisnecessarysincethedebuggerrequireswriteaccesstoprogrammemorysothatitcan placebreakpointsinprogrammemorywhenbreakingorsteppingthroughcode.Thuswhen usingtheOCDversion,programmemorymustbecomprisedofread/writememory.In generalitisadvisabletousetheOCDversionduringdevelopmentandswitchbacktothe nonOCDversionforproduction.

11.2 Awordaboutsimulation
Ingeneral,itisdesirabletointeractwithrealhardwarewhendebuggingratherthan performingsimulationsonly.ThepresenceoftheNanoBoardmeansthatmostdesignscan bedebuggedinrealhardware,i.e.LiveDesign,howevertheremaybetheoddoccasionwhen itisnecessarytosimulateadesign. TheAltiumDesignerdevelopmentenvironmentsupportsfullsimulationbaseddebuggingas wellasLiveDesignusingrealhardwaretheinterfaceisidentical.Switchingbetween LiveDesignandSimulationisachievedbychangingthedebuggermodeviatheDebug toolbaravailablewheneditinganembeddedprojectsourcedocument,orbyrightclickingthe EmbeddedProjectintheProjectspanelandselectingeitherDebug<processor designator>orSimulate. ForourdiscussionsweshallfocusontheLiveDesignenvironment,asthisisusuallythemost desirablemodeofdebugginghoweverallthatismentionedhereisapplicabletothe simulationenvironmentalso. Theeasiestwaytoinitiateadebugging/simulationsessionistorightclicktheembedded projectintheProjectspanelandselectingDebugorSimulate.Ofcourse,theDebugoptionis onlyavailableifaNanoBoardortargetplatformispresentandpoweredup.

11.2.1 TheDebugmenu
Debugcommandsareavailablewheneveranembeddedsourcefileisopeninthemain window.DebugcommandscanbeaccessedviatheDebugtoolbar:

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OrfromtheDebugmenu: Run(F9):Runthecurrentembeddedproject indebugmode. Afterlaunchingthe command,executionofthecodeinthe embeddedsoftwareprogramwillbegin.Ifany enabledbreakpointshavebeensetup,code executionwillhaltatthesepoints,if encountered RuntoCursor(Ctrl+F9):Executethe embeddedcodeuptothelinecontainingthe cursor. ToggleBreakpoint(F5):Thiscommandis usedtotoggleanenabledbreakpointforthe currentline.Afterlaunchingthecommand, thecurrentlinewillhaveanenabled breakpointaddedtoitorremovedfromit, dependingonwhetherornotanenabled breakpointcurrentlyexistsforthatline. Enabledbreakpointsareindicatedinthecode byaredhighlightoverthebreakpointlineand aredcirclewithacrossinthemargin. Disabledbreakpointsareindicatedinthecodebyagreenhighlightoverthebreakpointline andagreencirclewithacrossinthemargin.Adisabledbreakpointremainsdefinedbutwill notcauserunningcodetohaltwhenencountered. Ifadisabledbreakpointexistsforthelineandthiscommandisused,thebreakpointwillbe removed. Youcanviewalistofallbreakpointsthathavecurrentlybeendefinedinallopenembedded projectsourcecodefiles,intheBreakpointspanel. AddWatch:Thiscommandenablesyoutodefinewatchexpressionsforthecurrent embeddedsourcecodedocument.Awatchexpressioncanbeasinglevariableoran expressioncontainingoneormorevariablesandallowsyoutoviewthevalueofthe expressionasyoustepthroughthecode.Basicmathematicaloperationsaresupported (e.g.a+b,a*b,c+(ba)). StepInto(F7):Usethiscommandtoexecuteeachlineofthecurrentembeddedsource codesequentially,includingtheindividuallinesofcodecontainedwithinany procedures/functionsthatarecalled.Thenextexecutablelineofcodeishighlightedinblue andisindicatedbyabluecirclewithanarrowinthemargin. StepOver(F8):ThesameastheStepIntocommandexceptprocedure/functioncallsare treatedasasinglelineofcodeandexecutedasasinglestep. StepIntoInstruction(Shift+F7):Thiscommandisusedtoexecuteeachindividual instructionattheassemblycodelevel,inturn,includingtheinstructionscontainedwithin anyfunctionsthatarecalled. Whenthesourcecodedocumentisan.asmfile,thenextexecutableinstructionis highlightedinblueandisindicatedbyabluecirclewithanarrowinthemargin.This commandandtheStepIntoSourcecommandwillbehaveinthesameway. Whenthesourcecodeisahighlevellanguage(.cfile),useofthiscommandshouldideally bemadefromwithinoneofthetwodisassemblyviewsforthecodeeithertheextended mixedsourcedisassemblyview(accessedbyclickingtheShowDisassemblybuttonon thedebugtoolbarinthesourcecodeview),orthepuredisassemblyview(accessedby clickingtheToggleSourceCodebuttononthedisassemblystandardtoolbar,fromwithin themixedsourcedisassemblyview).

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Inbothmixedandpuredisassemblyviews,thenextexecutableinstructionishighlightedin darkblueandisindicatedbyadarkbluecirclewithanarrowinthemargin. StepOverInstruction(Shift+F8):ThesameastheStepIntoInstructioncommand exceptprocedure/functioncallsaretreatedasasinglelineofcodeandexecutedasa singlestep. StepOut:Thiscommandisusedtostepoutofthecurrentfunctionwithintheembedded sourcecode.Theremainingexecutablecodewithinthecurrentfunctionwillbeexecuted andtheexecutionwillbepassedontothenextsequentiallineofcodeafterthefunction's callingstatement. ShowDisassembly:Openanintermixedsourceanddisassemblyviewforthecurrent embeddedsoftwareproject.Anewviewwillopenastheactiveviewinthemaindesign window.Thisviewshowsamixtureofdisassembledinstructionsandsource(C)code.The sourceforallsourcecodefilesinthecurrentembeddedprojectwillbedisplayed. Inthisintermixeddisassemblyandsourceview,thenextexecutablesourcelineis highlightedinblueandisindicatedbyabluecirclewithanarrowinthemargin.Thenext executabledisassembledinstructionishighlightedindarkblueandisindicatedbyadark bluecirclewithanarrowinthemargin. Resynchronize:Usethiscommandtosynchronizethedebuggerexecutionpointwiththe externalhardware. ShowExecutionPoint:Positionthetextcursoratthestartofthenextlineofcodetobe executed.Ifthenextexecutablelineofcodeisoutsideofthevisibleareaofthemain displaywindow,thedocumentwillbepannedtobringitintoview. Break:Haltanexecutingprocessoratthenextexecutablelineofsourcecode. Reset(Ctrl+F2):Resettheexecutingprocessorcurrentlybeingdebugged,atanystage whensteppingthroughcodeorafterabreakpointhasbeenencountered,andreturnthe currentexecutionpointbacktothefirstlineofexecutablecode. StopDebugging(Ctrl+F3):Terminatethecurrentdebuggingsession.

11.3 Embeddedcontrolpanels
ClickingontheEmbeddedbuttonofthe workspacepanelswillopenthelistof embeddedcontrolpanels.Alternatively usethemenucommandsbyselecting ViewWorkspacePanelsEmbedded. SelectingF1whilstanitemwithinapanel hasthefocuswillbringupextensivehelp onthepanelsoperation.

Figure48.Debuggerpanels

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11.3.1

Breakpoints

Figure49.Thebreakpointspanel

TheBreakpointspanelprovidesinformationonallbreakpointsthatarecurrentlydefined eitherwithintheopensourcecodedocumentsforanyembeddedprojectorinoneofthe memoryaddressspacesassociatedwithaprocessorwhoseembeddedcodeiscurrently beingdebugged. Thefollowingtwotypesofbreakpointcanbedefined: Sourcecodebreakpointappliedtoaparticularlineofcodeinthesourcedocument ofanembeddedsoftwareproject Memoryaddressbreakpointspecifiedforaparticularaddressinamemoryspace associatedwiththeprocessoronwhichthecodeisrunning.

Anybreakpointsthatarecurrentlydefinedinanyopenembeddedprojectsourcecodedocuments(*.C, *.asm),orprocessormemoryspaceswillbelistedinthepanel.

11.3.2

CtoHardware

Figure50.CtoHardwarepanel.

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TheCtoHardwarepanelprovidesacontrolpanelforAltiumDesignersApplicationSpecific Processordiscussedlaterinthiscourse.FromthispanelGlobalVariablesandFunctionscan beoffloadedtohardwareprovidedtheymeetthecriteriarequiredtoinstantiatetheparticular variableorfunctionaslogic.ThiscapabilityisdetailedinthedocumentGU0122Cto

HardwareCompilerUserManual.pdf 11.3.3 CallStackPanel

TheCallStackpanelprovidesinformationaboutwhichlineofsourcecodethedebuggeris nextgoingtoexecuteandwhichfunctionthatlineofcoderesidesin.Ifasequenceoffunction callshavebeenmadetoreachthecurrentlineofcode,thesecallswillbedisplayedasa'call stack'. Asyoustepdebugyoursourcecode,thepanelwillshowthecurrentfunctionyouarein,the nameoftheactivesourcedocumentandthelineofsourcecodethatthedebuggerhas reached(i.e.thenextlineofexecutablecode). Whenacalltoanotherfunctionisencountered,thepanelwillshowthatfunction,alongwith thevaluesofanyparameterspassedintoitandthenextexecutablelineofcodewithinthat function.Asthefunctioniscalledfromwithinafunction,theoriginalfunctionisstilldisplayed, showingthelineofcodethatwillbeexecutedwhenprogramexecutionpassesbackintoit. A'callstack'iseffectivelysetup,showingtherelationshipbetweendescendantfunctioncalls. Theoriginalfunctionappearsatthebottomofthestack,witheachsubsequentlycalled functionaboveit,rightuptothecurrentlyenteredfunctiononthetopofthestack.Thecurrent functionisdistinguishedbyaredarrowtoitsimmediateleft.

Figure51.TheCallStackpanel.

11.3.4

CodeExplorer

TheCodeExplorerpanelprovidesavisual summaryofallidentifiers(Definestatements, Variables,Routines(functions)orLabels)that areusedintheactivesourcedocument(*.C, *.asm,*.h)foranembeddedsoftwareproject (*.PrjEmb). TheinformationthatappearsintheCode Explorerpaneldependsonthetypeofsource documentcurrentlyactiveinthedesigneditor window. Doubleclickingonanentryinthepanel(or selectingitandpressingENTER)willjumpto thecorrespondingareaofcodeinthedesign editorwindow,placingthetextcursortothe immediateleftoftheidentifier. Directfilteringisavailable,allowingyouto quicklyjumptoanentrybydirectlytyping withinthepanel. Tousethisfeature,simplyclickwithinthe panelandtypethefirstletteroftheentryyou
Figure52.Thecodeexplorerpanel

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wishtojumpto.Thefirstentryinthepanelstartingwiththeletteryoutypewillbecome selectedandtheletterwillbehighlighted.

11.3.5

CrossReferences

TheCrossReferencespanelenablesyoutoquicklylocatealloccurrencesofavariable, functionorprocedure,withinthesourcecodedocumentsofanembeddedproject. InformationintheCrossReferencespanelwillonlyappearafterrightclickingonanidentifier inthesourcecode(variable,functionorprocedure)andchoosingtheShowCross Referencescommandfromthesubsequentpopupmenuthatappears. Note:Crossreferencingmustbesetupforthesourcecodedocumentsforthisfeaturetobe available.EnableCreateCrossReferenceInfounder ToolsEmbedded PreferencesEmbeddedSystemLibraries. RefertothedocumentTR0104Altium DesignerPanelsReference.PDFforcompletedetailsonsettingupyour preferencestosupportcrossreferencing. Theupperregionofthepanellistsinstancesoftheselectedvariable,functionorprocedure namethathavebeenfoundwithinthescopeofthesearch.Asyouclickonaninstance,the lowerregionofthepanelwillshowwhereinthesourcecodethatinstanceexists.

Figure53.Thecrossreferencespanel

11.3.6

DebugConsole

TheDebugConsolepanelprovidesa historyofthecurrentdebugsession,in termsofthecommandsissuedandthe linesofcodeexecuted.Thepanelalso offerscommandlinedebuggingofthe embeddedcode. Asyoudebugthesourcecodeforthe activeembeddedproject,thepanelwill 'keeptrack'ofthedebugcommandsas

Figure54.Thedebugpanel.

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youissuethemandthecurrentexecutionpoint.Forexample,ifyouissueaStepInto commandfromthe Debug menuortoolbar,thepanelwillshowanentrythatreflectsthiscommand(>s)followed byanentrythatreflectsthenextlineofcodetobeexecuted. Thecontrolsatthebottomofthepanelallowyoutodrivethedebugsessionfromwithinthe panel. SimplyenterthesyntaxforthecommandyouwishtoissuetotheDebuggerandeither clicktheSendbuttonorpressENTER. Thefollowingtablecontainsexamplecommandlineentriesthatcorrespondtocommon debuggingcommandsavailablefromtheDebug menuortoolbar: PanelCommandline Entry C Cn(wheren=line number) s S si Si .dxpresync rst CorrespondingDebugCommand onDebugMenu Run RuntoCursor Correspondingentry inDebugtoolbar

StepInto StepOver StepIntoInstruction StepOverInstruction Resynchronize Reset

Inaddition,theHALTbuttonatthebottomrightofthepanelbehavesthesamewayasthe BreakcommandavailableontheDebug menuandtoolbar.

11.3.7

EvaluatePanel

TheEvaluatepanelisusedtoquicklydeterminethecurrentvalueofavariableorexpression intheactivehighlevelsourcecodedocument(*.C)currentlybeingdebugged. Usethefieldatthetopleftofthepaneltoenterthevariableorexpressionyouwishto evaluateandeitherclicktheEvaluatebuttonorpressENTER.Thevariable/expressionstring willappearinthemainregionofthepanel,withtheresultoftheevaluationappearingnextto it,undertheValuecolumn. Thevariable/expressionisnotupdatedwithrespecttoitsvalueasyoustepdebugthecode. Youcan,however,repeatedlyusetheEvaluatebuttontoupdatethevaluefortheentry. Ifyouwishtokeepaconstantwatchonthevariable/expression,wherethevalueisupdated asthecodeexecutes,usetheAddWatchbuttontoaddthevariable/expressionasanew watchentrytotheWatchespanel.

Figure55.Theevaluatepanel

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11.3.8

LocalsPanel

TheLocalspanelallowsyoutointerrogatethevaluesofvariableslocaltothefunctionthat thedebuggerhascurrentlyentered.Youcanalsochangethevaluesofvariablesontheflyas youdebug. Asyoustepdebugyoursourcecode,thepanelwilldisplayalllocalvariablesandpassed parametersastheyareencounteredforthecurrentfunction.Whenenteringaparametric function,theentrieswillappearinthepanelafterexecutionofthecallingstatement.

Figure56.Thelocalspanel

11.3.9

RegistersPanel

TheRegisterspanelallowsyoutointerrogatethecontentofregisterswithinthecore processorcurrentlybeingdebugged.Youcanalsochangethevaluesofregistersonthefly asyoudebug. Foreachregister,thefollowingdatafieldsareavailable: Registerthenameoftheregister Widththesizeoftheregister(e.g.8bit,16bit,32bit) Decimalthevaluecurrentlystoredintheregister,presentedindecimalformat(e.g. 30) Hexadecimalthevaluecurrentlystoredintheregister,presentedinhexadecimal format(e.g.1E) Binarythevaluecurrentlystoredintheregister,presentedinbinaryformat(e.g. 00011110) Charthevaluecurrentlystoredintheregister,presentedincharacterformat(e.g. decimal87wouldbecharacterW)

TheRegister,WidthandCharfieldsarenoneditable.Thenumberformatfieldsallowfor changingofregistervaluesasyoudebug.

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Figure57.Theregisterspanel

11.3.10

WatchesPanel

TheWatchespanelenablesyoutocreateanddisplayalistofwatchexpressions,allowing youtokeeptrackofvariable/expressionvaluesasyousinglestepdebugthesourcecodeof anembeddedsoftwareproject. Thepanellists,foreachwatchthatisadded,theExpression(whattowatchfor)andthe Value(theevaluationoftheexpressionatthecurrentlineinthesourcecode). Asmallicontotheleftofthewatchexpressionisusedtoindicatethestatusofthewatch: Sourcecodeexecutionhasenteredafunctionorprocedurewherethewatch expressionis valid Sourcecodeexecutionhasenteredafunctionorprocedurewherethewatch expressionisinvalid.Thisstatewillalsooccurifthewatchexpressionisnotvalid. Watchisdisabled

Figure58.Thewatchespanel

11.4 InstrumentRackNexusDebugger
Inadditiontothetraditionalsourcecodeleveldebugtoolsavailable,AltiumDesigneralso includesanInstrumentRackformicroprocessors/microcontrollersthatgivesyouan unparalleledviewoftheprocessorsregisters,andtheopcodesandinstructionsexecutingon thecurrentprocessor.Thisdialogwillalsoallowyoutopause,run,reset,andstepthe processor.

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Figure59.Instrumentrackforsoftdevices

ThisinstrumentrackisaccessedbyrightclickingtheprocessorintheDevicesviewand selectingNexusDebugger. ClickingontheNexusDebuggerbuttonwillaccessthecorrespondingdebugpanelforthe typeofprocessoryouareusing.Thispanelcontainsagreaterarrayofdebugcontrols, providingaccesstotheinternalregisters,memoryspacesandalsoshowsadisassembly viewoftheembeddedsourcecodeasyoudebug.

Figure60.Nexusdebuggerpanel

Thevariousmemorypanelsavailableforaprocessorenableyoutointerrogatethedifferent memoryspacesassociatedtothatprocessor,concurrently. Thebehaviorofeachoftheavailablememorypanelsisidentical,regardlessofthememory spacerepresented:

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addressspacetypicallystartsat00000000hwhendisplayedinthepanel,regardless ofwherethememoryphysicallyresidesintheprocessor'smemorymap memoryspaceisdividedintorowsof16cells,witheachcellrepresentinganaddress inmemoryspaceandthevaluecontainedtherein,inhexformat.TheDatacolumn reflectsthevalueateachaddress(intheassociatedrow)inASCIIformat afieldisincludedatthetopofeachpanelforfiltering,allowingyoutojumptorow containingthespecificaddressofinterestwithintherepresentedmemoryspace arefreshbuttonatthetopleftofthepanelenablesyoutomanuallyrefresh/update thecontentsofthememoryspace

11.4.1 ChangingtheContentsofMemory
Tochangethecontentsofanaddressinmemory,simplyclickonthedesiredcellandtypethe newhexadecimalvalueasrequired.Ifthememoryiswritable,itwillautomaticallybe refreshedwiththeenteredvalue.Ifitisreadonly,thenewvaluewillbediscardedandthe memorylocationwillremainunchanged. AdditionaleditingoptionsincludingoptionstoFillamemorywithzeros,ones,orahexvalue 0xFF,aswellasoptionstoSavethememorycontentstoafileorLoadmemorycontentsfrom afile.Simplyrightclickamemoryinthedialogtoviewafulllistofoptions.

11.4.2

DefiningBreakpointsinMemory

Memoryaddressbreakpointscanbeaddeddirectlytoaddressesfromwithintherelevant panelfortherequiredmemoryspace.Toaddabreakpointatasingleaddress,simplyright clickoverthataddressinmemoryandchoosewhenthebreakpointistobeapplied(onread, onwrite,onreadorwrite).

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12 CtoHardware
InthissectionwewillintroduceyoutotheCtoHardwarecapabilityfoundinAltiumDesigner. TheCtoHardwareCompiler(CHC)compilerresemblesanormaltoolset(compiler, assembler,linker,andlocator)butinsteadofproducingasoftwarefile,itproducesahardware filethatcanbeloadedontoanFPGA. TheCtoHardwareCompileracceptsstandarduntimedISOCsourcecodeasinputand producesasynthesizablehardwarefile.ThesynthesistoolsofAltiumDesignertranslatethis hardwarefileintoanelectroniccircuitwhichcanbeloadedontoanFPGAalongwiththerest ofthedesignandthesoftware. InAltiumDesigner,theCtoHardwareCompilerisusedincombinationwithatraditional embeddedcompiler.Thismeansyoucanwritean'ordinary'Cprogramforaprocessorcore. UsingAltiumDesigner,youcanmarkwhichfunctionsshouldbecompiledtohardware.Your FPGAdesignthenneedsanApplicationSpecificProcessor(ASP)toholdthesecompiled hardwarefunctions. Whencompilingandsynthesizingyourproject(embeddedsoftwareandhardware),eitherthe regularCcompilerortheCtoHardwarecompilerisinvokeddependingonwhetheryou markedfunctionsashardwareornot. Thefinalresult,afterhavingcompiledtheapplicationandhavingloadedbothsoftwareand hardwareontoanFPGA,isasystemwherethesoftwareandthesynthesizedhardware functionsformtheimplementationofyouroriginalCprogram.Thesoftwarepart'calls' hardwarefunctionsthatperformtheirtaskfarmoreefficientlythaniftheywerecompiledto software.

12.1 WhatarethebenefitsoftheCtoHardwareCompiler?
VirtuallyallCprograms(orfunctions)canbeconvertedtoanelectroniccircuitbytheCto HardwareCompiler.However,thecharacteristicsoftheprogramdeterminewhethertheCto HardwareCompilercancreateanefficienthardwarecomponentorwhetheritisbetterto executetheprogramonaprocessorcore.TheCtoHardwareCompilercanonlycreatea smallandfastelectroniccircuitiftheCsourcecodeisparallelizable.Insuchacasethe hardwareexecutesmanyoperationsinparallelwhereasaprocessorcorewouldfetchand executeinstructionssequentially. Graphics,signalprocessingandencryptionalgorithmstranslateverywellintohardwareand performanceimprovesbyordersofmagnitude.ForthesetypesofalgorithmsFPGA implementationsoutperformhighendDSPandRISCprocessorcores. SothemainbenefitoftheCtoHardwareCompileris,thatitletsyoudesignhardware modulestoperformspecifictasksbysimplyprogrammingtheminC.Normallythiswouldbea complexandtimeconsumingjobthatwouldhavetobeperformedbyspecializedhardware designers.

12.2 UsingtheCHCCompiler
Foraregularembeddedproject,theCHCcompilerwillnotbeinvoked.Inthissituationonly theFPGAdesignissynthesizedandloadedontoanFPGAtogetherwithareadycompiled embeddedproject. TheCtoHardwareCompilerisactuallyacompletetoolset,includingacompiler,assembler andlinker,conceptuallyverysimilartoaregularCtoolset.

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TheCHCcompilerisinvokedwhentheFPGAdesigngivescausetodoso: theFPGAdesigncontainsoneormoreApplicationSpecificProcessor(ASPs) components,whichareabletoholdthehardwareequivalentofaCsoftwarefunction theconfigurationoftheASPcomponentdescribesthatitcontainsatleastone hardwarecompiledCfunction

Whenbuildingtheproject,basedontheconfigurationsettingsoftheASPsontheschematic, alistoffunctionqualifiersisgeneratedthatmarkthefunctionstobecompiledtohardware. ThisfunctionqualifierfileissubmittedbothtotheregularembeddedtoolsetandtotheCHC toolset.Theembeddedtoolsetnow"knows"whichfunctionsshouldbecompiledtohardware. Itdoesnotcompilethesefunctions,butgeneratesawrapperwithjustenoughcodetocallthe hardwarefunction,topassanyvariables,andtoreceivethereturnvalue.Theresultisan absoluteELFobjectfile. ThesameCsourcesandfunctionqualifierfilearesubmittedtotheCHCtoolset.Basedonthe functionqualifierfile,theCHCtoolsetcompilesandassemblesthemarkedCfunctionsto hardware.TheresultisanabsoluteELFobjectfilewhichcontainsthehardwarefunctions. TheELFfilewiththehardwarefunctionswillbetranslatedintoVHDLorVerilogbytheHDL generator.Thenitissynthesized,alongwiththerestoftheFPGAdesign,resultinginaBIT filewhichcanbeloadedontotheFPGA.TheELFfilewiththesoftwarefunctionsisalreadyin itsfinalstateandwillbeloadedintotheprocessorsoftcoreontheFPGA.

12.3 ImplementingCtoHardwareinourDesign
Inthefollowingsectionwewillprovethatseeing,trulyisbelieving.Recalltheperformanceof therotatingvideo.UsingthesliderwesawthevideoscaleandrotateontheTFT.Aswe completethefollowingseriesofexerciseswewillseetheperformanceofthesetwo operationsincreaseconsiderably.

12.4 Exercise24MakingRoomforCtoHardware
InthisexercisewewilladdanadditionalinterfacetoourperipheralWishboneInterconnect componentU1.Thisprovidesusameansfortheprocessortoaccessthefunctionsthathave beenplacedinhardware. 1. RightclickU1intheschematicandselectConfigureU1(WB_INTERCON) 2. SelecttheAddDevicebuttonandconfigurethisdeviceasseeninthefigurebelow

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Figure60. AddingtheASPtothewishboneinterconnect

3. ClickOKtoclosetheDevicePropertiesdialog. 4. ClickOKtoclosetheConfigureU1(Wishbone_Intercon)dialog. 5. Saveyourwork.

12.5 Exercise25AddingtheApplicationSpecificProcessor
InthisexercisewewilladdanApplicationSpecificProcessor,WB_ASPtoourdesign.The WB_ASPperipheralisusedasa'container'forCsourcefunctionsthatareimplementedin hardwarethroughuseoftheCtoHardwareCompiler. WiredintoanFPGAdesignjustlikeanyotherperipheral,theWB_ASPenablesahost processoraccessandcontroloverhardwarecompiledfunctionswithin.Thesefunctionswill populatetheWB_ASPoncethedesignprojecthasbeencompiledandsynthesized. Whenahardwarefunctioniscalled,theprocessorsimplytransfers valuesforthefunction's parameterstotheWB_ASP,startsthefunctionandwaitsforittoreturn.Ifthehardware functiondeliversareturnvalue,thiswillbereadbackbythehostprocessor,tobeusedinthe callingsoftwareroutine. 1. FromtheLibrariespanel,selecttheFPGAPeripherals.IntLibfile. 2. LocatetheWB_ASPperipheralandselectPlaceWB_ASP

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3. DesignatethecomponentU6andplacethecomponentsotheio_setofsignalpins alignwiththenewlycreatedportontheWishboneInterconnectcomponentU1. 4. Wirethecomponentasitappearsinthefollowingfigure(youmayneedtoincreasethe sizeofyourschematicdocumenttomakeroomforyourwiring).

Theio_interfacerepresentstheinterfacetotheprocessor.Theme_interface representstheinterfacetomemory.Overthenextfewexerciseswewillcompletethe wiring,givingtheASPaccesstomemory. 5. UpdatetheprocessorperipheralmemorytoincludetheASPbyrightclickingthe processorandselectingConfigureProcessorPeripheral...thenselecting ImportFromSchematictoimportthenewconfigurationintheConfigure Peripheralsdialog.

12.6 Exercise26GivingtheASPAccesstoMemory(part1)
InthisexercisewewilladdanotherWishboneInterconnectonthememorysideofourdesign configuringitsuchthatwecanaccessbothmemoriesourvideocapture,andvideodisplay memories. 1. FromtheLibrariespanel,selecttheFPGAPeripherals.IntLibfile. 2. LocatetheWB_INTERCONperipheralandselectPlaceWB_INTERCON. 3. DesignatethecomponentU15 4. OpentheComponentPropertiesdialogandselectConfigure 5. SelectAddDeviceandaddanewslaveinterfaceconfiguredasithasbeeninthe followingfigure:

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Figure61. SpecifyingtheASPinterfacetoXRAM1

6. ClickOKtoreturntotheConfigureU15(WishboneIntercon)dialog. 7. SelectAddDeviceandaddanewslaveinterfaceconfiguredasithasbeeninthe followingfigure:

Figure62. SpecifyingtheASPinterfacetoXRAM2

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8. ClickOKtoreturntotheConfigureU15(WishboneIntercon)dialog. 9. ClickOKtoclosetheConfigureU15(WishboneIntercon)dialog. 10. WirethedesignasitappearsFigure63 11. Saveyourwork.

Figure63. WiringtheASPtointerconnecttobothmemories

12.7 Exercise27GivingtheASPAccesstoMemory(part2)
InthisexercisewewillgiveeachofthetwoWishboneMultiMastercomponentsan interfacethatallowstheASPaccesstothedisplayandcapturememories. 1. RightClicktheWishboneMultiMastercomponentU3andselectConfigureU3 (WB_MULTIMASTER) 2. WewillneedtoaddanadditionalmasterinterfacetocomponentU3.ConfigureU3asit appearsinthefollowingdialog.

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Figure64. UpdatingthemultimasterU3

3. ClickOKtoclosethedialog. 4. RightClicktheWishboneMultiMastercomponentU12andselectConfigureU12 (WB_MULTIMASTER) 5. WewillneedtoaddanadditionalmasterinterfacetocomponentU12.ConfigureU12 asitappearsinthefollowingdialog.

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Figure65. UpdatingthemultimasterU12

6. ClickOKtoclosethedialog. 7. WirethetwocomponentsastheyappearinFigure66andFigure67. 8. Saveyourwork.

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Figure66. UpdatedwiringforwishbonemultimasterU3

Figure67. UpdatedwiringforwishbonemultimasterU3

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12.8 ConfiguringtheASP
TobeginrealizingthebenefitsofCtoHardwarewemustfirstconfigureourWishboneASP component. Toconfigure,rightclickthecomponentinschematicandselectConfigureU6 (WB_ASP).ThiswilllaunchtheConfigureU6(WB_ASPProperties)dialogseeninFigure 68.

Figure68. Configuringthe wishboneASP

Thefollowingtabledescribesthevariousoptionsavailableintheconfigurationdialog.

Option
Processor

Description
Usethisfieldtospecifytheprocessor,by designator,thatisconnectedtotheWB_ASP andwhichcanthereforecallfunctionsthathave beengeneratedinhardware.

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Option
GenerateASP

Description
Thisoptionprovidestheabilitytoenableor disablegenerationofhardwarecompiled functions.Withthisoptionenabled,theCto HardwareCompilerwillbeinvokedwhenyou compileandsynthesizeyourdesignproject.All functionsthathavebeenenabledfor implementationinhardwarewillbecreatedas electroniccircuitsintheFPGAfabric. Thisoptionenablesyoutocontrol,onaglobal level,whetherfunctionscompiledintohardware willbecalledbysoftwarebasedfunctions runningwithintheprocessor.Ifthisoptionis disabled,theembeddedcompilerwillgenerate thefunctionsinsoftwareandthesewillbeused. Usethisfieldtospecifythewidthofthe WB_ASP'shostinterfaceaddressbus (io_ADR_I).Thisbusisusedbytheprocessorto accessandpassvaluestoparametersina hardwarefunction,andalsotoaccessandread backafunction'sreturnvalue,whereapplicable. Thewidthspecifiedhereshouldbelargeenough toincludeallparametersofthelargestfunction beingimplementedinhardware. Usethisfieldtospecifytheamountofblank spacebetweenthehostprocessorandexternal memoryinterfacestothedevice. Thislistreflectsallglobalvariablespresentinthe linkedembeddedsoftwareproject.Ifyouwantto haveavariableallocatedinhardware,simply enablethecorrespondingcheckboxinthe AllocateinHardwarecolumn.Suchavariable willbeallocatedinASPblockRAMbytheCHC Compiler.Accesstothismemoryismuchfaster, incomparisontostorageallocationinblockRAM outsideoftheASPbytheEmbeddedCompiler. Thelistsupportsstandardmultiselectfeatures, allowingyoutoquicklyselectmultiplevariables. Onceselected,usetheavailablerightclick contextmenucommandstoquicklyenable (PushtoHardware)ordisable(Removefrom Hardware)thecorrespondingAllocatein Hardwareoption. Notethataglobalvariablethatisallocatedin hardwarecanonlybeaccessedbyafunction thathasalsobeenimplementedinhardware. Suchavariablecannotbecalledfroma softwarebasedfunctionrunningonthehost processor.

UseASPfromSoftware

AddressBusWidth

ExtraSpace

SymbolsinHardware GlobalVariables

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Option
SymbolsInHardware Function

Description
Thislistreflectsallfunctionspresentinthelinked embeddedsoftwareproject.Ifyouwantto implementafunctioninhardwaregeneratedby theCHCCompileraspartoftheASPsimply enablethecorrespondingcheckboxinthe ImplementinHardwarecolumn.Shouldyouwish tobeabletocallthathardwarefunctionfrom withinthesoftwarerunningonthehost processor,ensurethatthecorrespondingcheck boxintheExporttoSoftwarecolumnisalso enabled. Thelistsupportsstandardmultiselectfeatures, allowingyoutoquicklyselectmultiplefunctions. Onceselected,usetheavailablerightclick contextmenucommandsto: PushtoHardwareenableImplementin Hardwareoptionforeachfunctioninthe selection RemovefromHardwaredisable ImplementinHardwareoptionforeach functionintheselection PushandExporttoHardwareenable ImplementinHardwareandExportto Softwareoptionsforeachfunctioninthe selection UnexportfromHardwaredisableExport toSoftwareoptionforeachfunctioninthe selection.

12.9 Exercise28AcceleratingourperformancewithASP
InthisexercisewewillconfiguretheASPtooffloadsomeofthefunctionalityofourdesign (previouslydoneinsoftware)intotheFPGAhardware. 1. RightclicktheWB_ASPcomponentU6intheschematicandselectConfigureU6 (WB_ASP)Thefollowingtabledescribesthevariousoptionsfoundinthisdialog. 2. ConfiguretheWB_ASPU6tomatchtheparametersinfigure69.

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Figure69. ConfiguringthewishboneASP

Whatwehavedoneismovethetwofunctions,rotate andset_tabs intohardware. Therotate functionperformstherotationofthevideo,andtheset_tabs function buildsourSineandCosinetables.Theglobalvariablescostabandsintabhave alsobeenmovedtohardwareastheseareusedbybothofthesefunctionsandcanbe accessedmorequicklywhenaccessedfromASPblockRAM. 3. ClickOKtoclosethedialog. 4. MakesureyourDesktopNanoBoardisconnectedtoyourPCandpoweredon. 5. SelectView>>DevicesVieworclickontheDevicesViewicon inthetoolbar. 6. EnsurethattheLivecheckboxischecked.YoushouldseeapictureoftheDesktop NanoBoardintheupperregionofthedisplayandaniconoftheSpartan3FPGAinthe middleregion. 7. InthedropdownlistjustbelowtheSpartan3icon,ensurethatthe CHC_image_rotation/NBD2DSK01_07_DB30_04project/configurationpairis selected.

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8. LocatetheCompile,Synthesize,Build,ProgramFPGAbuttonsrunninglefttoright justbelowtheDesktopNanoBoardicon.ClickonceonthewordsProgramFPGAto beginthebuildprocess. 9. Oncethedesignhascompletedthebuildprocess,returntotheDevices viewandright clicktheDigitalIOinstrumentandselectInstrument. 10. FromtheInstrumentRack,adjusttheRot[7..0]andZoom[7..0]sliderstoseethe performanceimprovementwhenutilizingCtoHardware.

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13 OpenBus
Untilnow,ourdiscussionsofFPGAdesignhasreallycenteredaroundschematic,withall devicesinthesystemlaidoutonaschematicsheetorcapturedinahardwaredescription languagesuchasVHDLorVerilog.Suchdesignssufferaninherentcomplexity,intermsof readabilityandasimportantly,fromawiring/connectivityandconfigurationperspective. UsingAltiumDesigner'sOpenBusSystemweaimtogreatlyreducesuchcomplexity.The fundamentalpurposeofthissystemistorepresenttheprocessorperipheralinterconnections inamuchmoreabstractway.Itachievesthisbyprovidinganenvironmentinwhichtocreate yoursystemthatishighlyintuitive,streamlined,andlesspronetoerror. OpenBusSystemiscreatedandmanagedusingAltiumDesigner'sOpenBusEditor.The OpenBusEditorhasthefamiliarlookandfeelofAltiumDesigner'sSchematicEditor,withits ownuniquesetofresourcesforcreationofanOpenBusSystem.Filteringandinspectionare providedcourtesyoftheOpenBusFilter,OpenBusInspectorandOpenBusListpanels, accessedfromtheOpenBuspanelaccessbutton,tothebottomrightofthemaindesign window.Theseresourcesprovidearaisedabstractionlevelforcreatingyourprocessorbased designinamorevisualandintuitiveway.

13.1 CreatinganOpenBusversionofourdesign
CreatinganOpenBusdesignbeginslikeanyotherFPGAdevelopmenteffortinAltium Designer,withthecreationofanewFPGAProject.Tothatproject,sourcedocumentsare addedandmayincludeanycombinationorSchematics,VHDLorVerilogfiles,aswellas OpenBusdocuments. AnyFPGAdesignprojectthatusesthissystemmusthaveatoplevelschematicasall interfacecircuitryremainsonthetopsheet.Themainprocessorsystemisdefinedina separate,OpenBusSystemdocument(*.OpenBus)andconnectivitybetweenthetwoismade throughasheetsymbolplacedontheschematic. InthissectionwewillcreateourequivalentdesignusingOpenBus,thoughwewill,for simplicityssake,eliminatethevirtualinstrumentsandinsteadsimplyfocusongettingthe imageontotheTFT.

13.2 Exercise29BeginninganFPGAProjectUsing OpenBus

1. SelectFileNewProjectFPGAProjecttocreateanew,blankFPGAproject 2. RightclicktheprojectFPGAprojectFPGA_Project1.PrjFpgintheProjects panelandselectAddNewtoProjectOpenBusSystemDocument 3. RightclicktheprojectFPGAprojectFPGA_Project1.PrjFpgintheProjects panelandselectAddNewtoProjectSchematic 4. RightclicktheprojectFPGAprojectFPGA_Project1.PrjFpg intheProjects panelandselectSaveProjectAs Thiswillpromptyoutofirstsavetheschematic, thentheOpenBusdocument,andlastlytheFPGAprojectdocument.Savetheseas Video_Capture_Schematic.SchDoc,Video_Capture_OpenBus.OpenBus,and Video_Capture.PrjFpgrespectively. 5. FromtheProjectspanel,selecttheOpenBusdocumenttogiveitfocusinthemain workspace.

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13.3 OpenBusDevices
ThestartingpointforanyOpenBus Systemdocumentistheplacementof therequireddevicesthatwill constitutethesystem.These OpenBuscomponents,astheyare called,areplacedfromtheOpenBus Palettepanel.Openthispanelfrom theOpenBusbuttontothebottom rightofthemaindesignwindow. Thepanelcontainsgraphical representationsofdevicesavailable forFPGAdesigninAltiumDesigner, groupedbyfunction: Connectors Processors ProcessorWrappers Memories Peripherals

PlacementofOpenBuscomponentsis simplyacaseofclickingtherequired entryintheOpenBusPalettepanel andthenplacingatthedesired locationintheworkspace.Familiar schematicplacementcontrols,such asflippingandrotatingallowforfine tuningasneeded.

Figure70.TheOpenBuspalette.

13.4 Exercise30PlacingOpenBusComponents(part1)
Recallthatinouroriginalschematicweusedonlyahandfulofcorestocreatethebasic functionalityrequiredbyourdesign.Thisincluded: BT656Controller 2 I CController WishbonePortIO WishboneDisplayDriver TSK3000A

2xSRAMControllers Wethenalsoused: 2xConfigurableWishboneInterconnectcomponents 2xWishboneMultiMastercomponents Tomanagethebasicinterconnectivityinourdesign.

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LastlyweusedahandfulofVirtualInstrumentsthatcompletedtheuserinterfacetoour design. InthisexercisewewillbegintoplacethebasiccomponentsofourOpenBussystem. 1. EnsuretheOpenBusdocumentVideoCapture.OpenBusisthecurrentlyfocused documentintheworkspace. 2. LocatetheOpenBuspaneleitherusingtheOpenBusbuttononthelowerrightofthe workspaceorbyselectingViewWorkspacePanelsOpenBusOpenBusPalette. 3. LocatetheTSK3000AintheProcessorssectionoftheOpenBusPaletteandsingle clickittoswitchtoplacementmode. 4. MovethecursoroverthecenteroftheOpenBusdocumentandclickoncetoplacethe componentintothedocument. 5. Singleclickthecomponenttext TSK3000A_1andhitF2toperformanInPlaceeditof thetext.ChangethistoMCUasseenintheFigure71.
Figure71. NamingtheTSK3000

TSK3000A_1

MCU

IO

MEM

IO

MEM

6. Thetworeddotsontheoutsideofthecomponentbodyrepresent thetwomasterinterfacestothehostprocessor.Thesecanbe movedwithrespecttothecomponentbodybysimplyclickingand dragging. RepositiontheIOandMemoryInterfacesastheyappearinthefollowingfigure.These willautomaticallysnapintopositionasrequired.

MCU

MCU

IO

MEM

Figure72. RepositioningtheOpenBusportsontheMCU

MEM

IO

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7. ReturntotheOpenBuspanelandlocatetheVideoCaptureControllercomponentin thePeripheralssection.SelectthiscomponentandplaceitintotheOpenBus document. 8. SingleclickthecomponenttextBT656_1andhitF2toperformanInPlaceeditofthe text.ChangethistoVIDEOasseeninFigure73.

BT656_1

VIDEO

Figure73. Renamingthevideocapturecontroller

9. TheRedOpenBusport representsaWishboneMasterinterface.Thisinterfaceis usedtoconnecttheVideoCapturecontrollertomemory. TheGreenOpenBusport representsaWishboneSlaveinterface.Thisinterface isusedtoconnectthedevicetothehostprocessor,viatheWishboneInterconnect component. RepositiontheGreenandRedOpenBusportsasseeninthefollowingfigure.

BT656_1

VIDEO

Figure74. RepositioningOpenBusportsonthecapturecontroller

10. ReturntotheOpenBuspanelandlocatetheASPcomponentinthePeripherals section.SelectthiscomponentandplaceitintotheOpenBusdocument. 11. SingleclickthecomponenttextWB_ASPandhitF2toperformanInPlaceeditofthe text.ChangethistoASP. 12. RepositiontheGreenandRedOpenBusportsconsistentwiththeVideoCapture Controller. 13. ReturntotheOpenBuspanelandlocatetheVGA32BitTFTControllercomponentin thePeripheralssection. SelectthiscomponentandplaceitintotheOpenBus document. 14. SingleclickthecomponenttextVGA32_TFT_1andhitF2toperformanInPlaceeditof thetext.ChangethistoTFT. 15.

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16. RepositiontheGreenandRedOpenBusportsconsistentwiththeVideoCapture Controller. 2 17. ReturntotheOpenBuspanelandlocatetheI CcomponentinthePeripheralssection. SelectthiscomponentandplaceitintotheOpenBusdocument. 18. SingleclickthecomponenttextI2CM_W_1andhitF2toperformanInPlaceeditofthe text.ChangethistoI2C. 19. PositiontheGreenOpenBusporttotherightofthecomponentasitappearsinthe followingfigure:

I2CM_W_1

I2C

Figure75. RenamingtheI2Ccontroller

20. ReturntotheOpenBuspanelandlocatethePortIOcomponentinthePeripherals section. SelectthiscomponentandplaceitintotheOpenBusdocument. 21. SingleclickthecomponenttextWB_PRTIO_2andhitF2toperformanInPlaceeditof thetext.ChangethistoGPIO. 22. Finally,repositiontheOpenBuscomponentsintheschematicastheyappearinthe followingFigure.

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GPIO

VIDEO

MCU

ASP

I2C

TFT

Figure76. Positioningtheprocessorandperipherals

ThealignmenttoolsusedinatraditionalAltiumDesignerschematicarealsoavailable underOpenBus.TheseareallaccessibleunderthesinglekeyshortcutA.These toolsmaketheprocessofplacingandaligningtheOpenBuscomponentsfasterand easier.

13.5 Exercise31UsinganInterconnect
Asinschematic,OpenBusdesignsutilizeInterconnectcomponentstointerconnectany numberofslavedevicestoasinglemaster.InthisexercisewewillplaceourInterconnect componentandconnectourperipheraldevicestothehostprocessor. Youwillfindthis processtobegreatlysimplifiedundertheOpenBusparadigm. 1. FromtheConnectorssectionoftheOpenBusPalette,selecttheInterconnect componentandplacethecomponentsuchthatthegreenSlaveinterfacealignsdirectly totheleftofthehostprocessorsredMasterinterfacelabeledIO. 2. SingleclickthecomponenttextWB_INTERCON_1andhitF2toperformanInPlace editofthetext.ChangethistoI_IO. 3. LocatetheOpenBustoolbaralongthetopofthe mainworkspace.Thefollowingtabledescribes eachoftheitemsinthistoolbar.

MEM

IO

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ToolbarItem

Command
LinkOpenBusPorts

Description
Usethiscommandtolinktheportsofdevices withinyourOpenBusSystem.Whenyouenter linkadditionmode,allcurrentlyunlinkedports willbefiltered,withallotherelementsinthe systemdimmed. Ifyouclicktostartalinkonamasterport,all currentlyunlinkedslaveportswillbefiltered andavailableforchoosingthetermination pointofthelink.Conversely,ifyouclicktostart alinkfromaslaveport,allcurrentlyunlinked masterportswillbefilteredandmade available. Toremovealink,simplyclicktoselectitinthe workspace,thenpresstheDeletekey.

AddOpenBusPorts

Usethiscommandtoaddoneormore additionalportstoanInterconnectorArbiter componentintheOpenBusSystemdocument. Afterlaunchingthecommand,adimmedport shapewillappearfloatingonthecursor.As youmovetheshapenexttotheperimeterofa component,itwillbecomesoliddarkergray withablueoutline.Positionthenewportas requiredandclicktoeffectplacement. WhenaddingtheporttoanInterconnect component,anewmasterportwillbeadded. WhenaddingtheporttoanArbitercomponent, anewslaveportwillbeadded. Continueaddingfurtherportsasrequired,or rightclickorpressEsctoexitportaddition mode.

NormalizeOpenBus Link(s)Shape

Thiscommandallowsyoutoquicklynormalize theshapeofoneormorelinksintheOpenBus Systemdocument.Ensurethatalllinkstobe normalizedareselectedpriortolaunchingthe command.Oncethecommandislaunched,all linksintheselectionwillrevertbacktothe standardshapestheyhadwhenfirstplaced.

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ToolbarItem

Command
FlipOpenBusLink(s) Shape

Description
Thiscommandallowsyoutoquicklyfliponeor morelinksintheOpenBusSystemdocument. Ensurethatalllinkstobeflippedareselected priortolaunchingthecommand. Allowsyoutoquicklystraightenoneormore linksintheOpenBusSystemdocument. Ensurethatalllinkstobestraightenedare selectedpriortolaunchingthecommand. Oncethecommandislaunched,alllinksinthe selectionwillbestraightened,goingfrom sourcemasterporttodestinationslaveport. UsethiscommandtoaccesstheOpenBus SignalManagerdialog.Thisdialogisusedto managetheclock,resetandinterruptlinesfor thesystem. Theexportofinterruptlinesoutsideofthe OpenBusSystemdocumentishandledusingthis dialog. ThedialogprovidesanExternalconnection summarytab.Thislistseachoftheperipheral ormemorydevicesusedinthesystem,and theexternalinterfacesignalsassociatedwith them.Thesesignalsaretheportsthat correspondtothesheetentriesofthesheet symbolonthetoplevelschematicsheetthe methodbywhichtheOpenBusSystemis hookedintotheoverallFPGAdesign.

StraightenOpenBus Link(s)Shape

ManageOpenBus SignalsandInterrupts

4. ForourdesignwewillneedtoaddadditionalMasterportstoourInterconnect component.Thesewillenableustoconnecttheadditionalperipheralstoourhost processor. PresstheAddOpenBusPortbutton intheOpenBustoolbarandclickonceover theredMasterportontheInterconnectcomponent.Noticehowtheportsare automaticallyaligned. 5. Place3additionalOpenBusportstobringthetotalto1SlavePort(theinterfacetothe hostprocessor)and5MasterPorts(theinterfacestoourvariousperipherals). 6. Simplyclickinganddraggingonanyportwillallowyoutorepositionitaroundthe outsideofthebodyoftheInterconnectdevice.Aligntheportstomatchthefollowing figure.
I_IO MCU

Figure77. Positioningtheportsontheinterconnectcomponent

7. Saveyourwork

MEM

IO

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13.6 Exercise32LinkingOpenBusPorts
InthisexercisewewillbelinkingtheOpenBusportstooneanotherontheperipheralhalfof ourdesign.ThiscanbestbelikenedtowiringtheWishboneInterfacesofschematic componentstooneanotherintheschematiceditorhoweverthisprocesshasbeeneven furthersimplifiedunderOpenBus. 1. FromtheOpenBustoolbar,selecttheLinkOpenBusPortscommand andthecursor willchangetoacrosshair. 2. ClickononeoftheMasterportsontheInterconnectcomponentI_IO.Noticehowonly thevalidSlaveinterfacesareavailableforselection.ClickingonaSlaveinterfacewill connectthetwodevicestooneanotherandthesignalsrequiredtoconnectthesetwo componentswillbemanagedautomaticallybythesoftware. ThisisakeycomponentoftheOpenBussystemandsomethingnottobetakenlightly. Andthoughwhatisunderthehoodisalwaysavailableforustoinspect,thereslittle needwhenusingthecoressuppliedwithAltiumDesigner. 3. Connecteachoftheperipheralstotheinterconnectcomponentasdisplayedinthe figurebelow.ExperimentusingtheOpenBustoolbaroptionstoNormalize andStraighten
GPIO

,Flip

theOpenBusconnections.
VIDEO

I_IO

MCU

ASP

I2C

TFT

Figure78.Connectingtheperipherals

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MEM

IO

13.7 Exercise33Configuringourprocessorunderopenbus
TheprocessofconfiguringthehostprocessorunderOpenBusisinmanywaysidenticalto thewayinwhichaprocessorisconfiguredinschematic.Inthisexercisewewillconfigurethe hostprocessorforuseinourdesign. 1. RightclickthehostprocessorintheOpenBusdocumentandselectConfigureMCU (TSK3000A) 2. ConfiguretheprocessoroptionsfoundintheConfigure(32bitProcessors)dialogas theyappearinFigure79.

Figure79. Configuringtheprocessor

3. ClickOKtoclosethedialog. 4. Saveyourwork.

13.8 Exercise34ConfiguringtheGPIOComponent
InthisexercisewewillconfigureourGPIOcomponenttoincludetheportsrequiredto connectourLEDsandVirtualInstrumentstothisdesign. 1. RightclicktheGPIOcomponentandselectConfigureGPIO(PortIO) 2. ConfigurethesettingsintheConfigureOpenBusPortI/OastheyappearinFigure80.

Figure80. ConfiguringthePortIO

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Eachoftheportsspecifiedinthedialogwillbeconvertedtoasheetentrylaterinthis design.WhenspecifyingInput/OutputastheKind,twoseparatesheetentrieswillbe created,onefortheinput,anotherfortheoutput. 3. ClickOKtoclosethedialog. 4. Saveyourwork.

13.9 Exercise35FinalizingtheInterconnectComponent
InthisexercisewewillconfiguretheInterconnectcomponent,definingthecharacteristicsof eachoftheperipheralsastheyexistintheprocessorsmemoryspace.Thisprocesshas beenstreamlinedunderOpenBusasmanyoftheseattributescanbeinferredfromthe peripherals. Forexample,wecaninferfromourPortIOthatwerewetoselect4portsintheGPIO configurationdialog,wewouldrequire2bitstoaddresseachofthe4ports.UnderOpenBus, thesevaluesarepopulatedautomaticallyandonlyrequireustospecifythenumberofbitsto decodeandthebaseaddressofeachoftheperipherals. 1. RightclicktheI_IOcomponentandselectConfigureI_IO(Interconnect) 2. ClickingonafieldandhittingF2willallowyoutomakeeditstothecontentsofeach field.ConfigurethesettingsintheConfigureOpenBusInterconnectdialogtomatch thefigurebelow.

Figure81.ConfiguringtheOpenBusInterconnect

3. ClickOKtoclosethedialog. 4. Saveyourwork.

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13.10

DefiningtheMemorySideofourSystem

Asweveseenintheschematicportionofthecourse,thisdesignrequiresexternalmemory. InthissectionwewilladdtheIPnecessarytoaccessmemoryresourcesontheDesktop NanoBoard.

13.11 Exercise36AddingtheRemainingComponents
InthisexercisewewilladdthefinalfewpartsfortheOpenBusportionofourdesign.Below isalistoftheseparts,allofwhichshouldseemfamiliargiventheearlierschematicbased approachwevealreadycompleted. 2xInterconnectcomponents(namedI_MCU,I_ASP) 2xArbitercomponents(namedMULTIMASTER_1,MULTIMASTER_2) 2xSRAMController(namedXRAM1,XRAM2)

FromtheOpenBusPalette,placetheabovenamedcomponentsastheyappearinthe followingfigure.NotetheadditionalMasterandSlaveportsontheInterconnectandArbiter componentsrespectively.

MULTIMASTER_1

XRAM1

I_MCU

XRAM2
1

I_ASP MULTIMASTER_2
0

Figure82. Placingthememoryandmemoryinterconnects/arbiters

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13.12 Exercise37CompletingtheConnectivity
Inthisexercisewewillcompletetheconnectivityrequiredbythememoryportionofour design.UsingthetoolbarcommandLinkOpenBusPorts,connecttheportsastheyappear inthefollowingfigure.

VIDEO

MULTIMASTER_1

XRAM1

MCU

I_MCU

ASP
2

MEM

IO

XRAM2
1

TFT

I_ASP MULTIMASTER_2
0

Figure83.Connectingthememorysideofthedesign

13.13 Exercise38ConfiguringtheSRAMControllers
InthisexercisewewillconfigurethetwoSRAMControllersforusebyourdesign.Ifyou recallfromtheschematicportionofthecourse,bothofthesecontrollersinterfacedto SRAMontheDesktopNanoBoard.Thesizesofthesememorieshadbeenconstrainedby thedevicesontheboard,andtherequirementsofthedesign. 1. RightclickXRAM1intheOpenBusdocumentandselectConfigureXRAM1(SRAM Controller)tolaunchthecomponentsconfigurationdialog. 2. Thisdialogmatchesexactlythedialogwehadusedinschematic.IntheConfigure (MemoryController)dialog,specifythesettingstomatchthefollowingfigure.

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Figure84.ConfiguringtheMemoryControllerXRAM1

3. ClickOKtoclosethedialogandreturntotheOpenBusdocument. 4. RightclickXRAM2intheOpenBusdocumentandselectConfigureXRAM2(SRAM Controller)tolaunchthecomponentsconfigurationdialog. 5. IntheConfigure(MemoryController)dialog,specifythesettingstomatchthe followingfigure.

Figure85.ConfiguringtheMemoryControllerXRAM2

6. ClickOKtoclosethedialogandreturntotheOpenBusdocument. 7. Saveyourwork.

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13.14 Exercise39ConfiguringtheArbiters
InthisexercisewewillconfigurethetwoArbitercomponentsforusebyourdesign.Ifyou recallfromtheschematicportionofthecourse,therewasonearbiterforeachofthetwo memories.Thesemanagetheprocessor,ASP,andcaptureanddisplaycoresaccessto memory. UndertheOpenBussystem,theinterfacetothearbitershasbeensimplifiedconsiderably. BecauseoftheadditionoftheOpenBusports,wearenolongerrequiredtoaddadditional itemstothearbiterandmanagenamingandpinspacing.Instead,weareonlyrequiredto selectthewaymasterscontestfortheslaveresourceandspecifythemasterwithnodelay. 1. RightclickMULTIMASTER_1intheOpenBusdocumentandselectConfigure MULTIMASTER_1(Arbiter)tolaunchthecomponentsconfigurationdialog. 2. IntheConfigureOpenBusArbiterdialog,specifythesettingstomatchthefollowing figure.

Figure86.ConfiguringtheOpenBusarbiter

3. ClickOKtoclosethedialogandreturntotheOpenBusdocument. 4. RightclickMULTIMASTER_2intheOpenBusdocumentandselectConfigure MULTIMASTER_2(Arbiter)tolaunchthecomponentsconfigurationdialog. 5. IntheConfigureOpenBusArbiterdialog,specifythesettingstomatchthefollowing figure.

Figure87.ConfiguringtheOpenBusarbiter

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13.15 Exercise40ConfiguringtheInterconnects
InthisexercisewewillconfigurethetwoInterconnectcomponentsforusebyourdesign. Ifyourecallfromtheschematicportionofthecourse,thereweretwointerconnects,onefor thememoryandanotherfortheASP.Theseallowedustosplittheinterfacesofthesetwo componentsacrosstwodifferentmemoriessuchthattheyeachhadaccesstobothofthe memories. 1. ConfigurebothoftheOpenBusInterconnectcomponentsI_MCUandI_ASPasit appearsinthefollowingdialog.

Figure88ConfiguringtheOpenBusInterconnect

2. ClickOKtoreturntotheOpenBusdocument. 3. Saveyourwork.

13.16 FinalizingtheOpenBusPortionoftheDesign
Atthisstage,wehavenearlycompletedtheOpenBusportionofourdesignanditshouldbe obviousthatbyusingOpenBus,theprocessofcapturingyourdesignbecomesfaster. Likewiseitsimportanttorecognizehowmuchmoreaccuratetheconnectivitycanbewhen itsrelegatedtothesoftwaretosortoutandnotahumanprocess. AswecompletetheOpenBusportionofourdesign,onethingremains,andthatisthe configurationoftheprocessormemory.Ifyourecallfromourschematicdiscussions,the processormemorywasbeingautodefinedbyahardware.hfile.Wehadselectedthisoption ratherthanrelyontheerrorproneprocessofhavingtomanuallykeyinthisdataeverytime wemadeachangetoourdesign. UnderOpenBus,thisprocessisnearlyidenticalandthenextexercisewillrevisitthis.

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13.17 Exercise41ConfiguringtheProcessorMemory
Inthisexercisewewillconfiguretheprocessorsperipheralandinternalmemories.Wewill alsoconfiguretheprocessortousetheautogeneratedhardware.hfile,ratherthantry maintainingthememoryconfigurationmanually. 1. RightclickthecomponentMCUintheOpenBusdocumentandselectConfigure ProcessorMemorytolaunchtheConfigureProcessorMemorydialog. 2. Ensurethatthehardware.H(CHeaderFile)checkboxischeckedandensurethatthe memoryconfigurationaboveappearsasitdoesinFigure89.

Figure89.Configuringtheprocessormemory

3. SelecttheConfigurePeripheralsbuttontolaunchtheConfigurePeripheralsdialog. 4. Ensurethatthehardware.H(CHeaderFile)checkboxischeckedandensurethatthe memoryconfigurationaboveappearsasitdoesinFigure90.

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Figure90. Configuringtheprocessorperipheralmemory

5. ClickOKtoreturntotheOpenBusdocument. 6. Saveyourwork.

13.18 Exercise42Creatingasheetsymbolfroman OpenBusDocument

TolinktheOpenBusdocumenttoaparentschematic,youneedtocreateasheetsymbol fromtheOpenBusdocumentandplaceitontheparentschematic. Inthisexercisewewill createsheetsymbolfromtheopenbusdocument. 1. OpenVideo_Capture_Schematic.SchDoc 2. SelectDesign>>CreateSheetSymbolFromSheetorHDL. 3. WhentheChooseDocumenttoPlacedialogboxappears,selectthe Video_Capture_OpenBus.OpenBusdocumentandclickOK. 4. Alargesheetsymbolwillbeattachedtothecursor.Positionitatthecenterofthe schematicpageandclickoncetocommittheplacement. Thesheetentriesonthenewlyplacedsheetsymbolhavebeenlooselygroupedwith inputsontheleftandoutputsontheright.Youmustnowgothroughaprocessof unravelingallofthesesheetentriessothatyoucanconnectthemtotheportpluginson theNanoBoardmoreeasily.

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5. Asheetsymbolwiththevarioussheetentriesproperlyorganizedislocatedinthe SnippetspanelasOpenBus_Sheet_Symbol.Ifyouintendtousethissymbolbe certainyourfilenamematchesthefilenameintheSheetSymbolproperties. 6. AsnippethasalsobeencreatedwiththebasicPortPlugIncomponents,placedand readytobewiredintoyoursheetsymbol.YoucanfindthisintheSnippetspanelunder listedasOpen_Bus_PortPlugIns.

13.19 Exercise43LinkinganEmbeddedProjecttoan OpenBusDesign

TheProcessofLinkinganOpenBusFPGADesigntoanEmbeddedProjectisidenticaltothe processwithwhichwelinkedthesetwoprojectswedcreatedthedesignusingaschematic onlyflow. 1. FromtheProjectspanel,switchtotheStructureEditormode. 2. LocatetheembeddedprojectEmbeddedProject.PrjEmbintheValidSubProjectsand Configurationssectionatthebottomofthedialog. 3. DraganddroptheembeddedprojectoverMCU(TSK3000A)inthetopsectionofthe panel.Thiswilllinkthetwoprojects. Note:EmbeddedprojectscanbelinkedtomorethanoneFPGAproject.Thismakes theprocessofportingcodefromonedesigntoanotherquiteeasy.

Figure91Linkingthetwoprojects

4. ReturntotheFileViewmodeintheProjectspanel. 5. Saveyourwork.

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13.20

Exercise44ProcessinganOpenBusDesign

TheProcessofConstrainingandBuildinganOpenBusFPGADesignisidenticaltothe processwedundergonewhenwedbuiltourdesignusingaschematiconlyflow.Inthis exercisewewillrevisittheprocessofconstrainingandbuildingourdesign. 1. Firstweneedtoconfigureourdesign.WiththeFPGAandEmbeddedProjectslinked, switchtotheDevicesViewunderViewDevicesViewsorbyhittingthe buttonin thetoolbaratthetopofthescreen. 2. RightClicktheimageoftheDesktopNanoBoardatthetopofthewindowinthe DevicesViewandselectConfigureFPGAProjectVideo_Capture.PrjFpg

Figure92AutoconfiguretheOpenBusdesign

ThiswillautomaticallyconfiguretheFPGAProjecttoincludetheconstraintfiles requiredtotargetthehardwareontheDesktopNanoBoardandwilllaunchthe ConfigurationManagerForVideo_Capture.PrjFpgdialog. 3. WithintheConfigurationManager,clicktheAddbuttontoaddaconstraintfiletothe existingconfiguration. 4. LocatetheMyConstraint.constraintfileandaddthistothecurrentconfiguration(thisfile hadbeenusedbyourpreviousschematiconlyimplementationofthisproject). 5. LocateMyConstraints.ConstraintintheConstraintFilescolumnsandchecktheboxin theConfigurationscolumntoaddittotheexistingconfiguration. 6. ClickOKtoclosethisdialogandtheHardJTAGChainshouldappearnowinthemain window.Likewise,theSoft,NexusJTAGChainshoulddisplaytheHostProcessor MCUandourVirtualInstruments. 7. Saveyourwork. 8. LocatetheCompile,Synthesize,Build,ProgramFPGAbuttonsrunninglefttoright justbelowtheDesktopNanoBoardicon.ClickonceonthewordsProgramFPGAto beginthebuildprocess.

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14 Review

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