An Integrated Low-Noise Sensing Circuit with Efficient Bias Stabilization for CMOS MEMS Accelerometers

by

P. Ashok Chakravarthi 11EC62R09

Guided By Prof. Tarun Kanti Bhattacharyya Prof.Prasanta Kumar Guha

Micro Electronics & VLSI Design Specialization Department of Electronics & Electrical Communication Engineering Indian Institute of Technology, Kharagpur West Bengal-721302, India.

Contents 1. Abstract. 2. Introduction. 3. Circuit structure. 4. Design considerations. 5. Results. 6. Conclusions. 7. References.

Abstract:

The design of sensing circuit for capacitive accelerometer with low cost, small size, high sensitivity, low power consumption and low offset is getting an increasingly challenging area. CMOS MEMS technology is used to implement sensing circuit for capacitive accelerometer. Because of miniaturization of MEMS technology, it is possible to implement best sensing circuit with CMOS MEMS technology. Whenever acceleration is applied to the capacitor finger plates, the change in the capacitance value is captured by the sensing circuit. Here the sensing circuit is implemented with 0.35m CMOS technology. In this case, the capacitance and the proof mass of the capacitive sensor structures is fabricated by surface micromachining technique. The overall architecture mainly consists of front end amplifier, demodulator and 3 bit gain controlled amplifier. To compensate the dc offsets, the trimming circuit is used. And for proper bias stabilization sub threshold NMOSFET is employed. The proposed structure provides low noise, low dc offsets, and excellent dc bias stability and reduces power also. Finally it gives better sensitivity with low dc offset values. And it consumes very small area, which is about 5.66mm and the current consumption is 1.56mA. It gives the better sensitivity, which is about 457mv/g.

2. INTRODUCTION:
Low cost, small-size MEMS accelerometers with high Sensitivity, low noise, low offset, and low power consumption are needed in numerous applications. While both bulk micromachining and surface micromachining can be used for fabricating MEMS devices, capacitive sensing structures made by Surface micromachining are often chosen because of lower manufacturing Cost. In recent years, standard CMOS processes have been extensively used to fabricate surface micro machined accelerometer Systemon-a-chips (SoCs) . However, accelerometers for practical use. challenges exist when designing such

The capacitances and the proof masses of the capacitive sensor structures fabricated by surface micromachining are usually much smaller than those of the sensors fabricated by bulk micromachining. The total capacitance of a surface micro machined sensor is usually smaller than 100 fF and, while sensing, the magnitude of capacitance change is usually less than 1 fF. With such small values, noise and other nonidealities must be minimized in the system so that satisfactory performance can be obtained. Many applications demand accelerometers with g resolution. However, except for a few cases , the noise floor present in most surface micro machined accelerometers is higher than 100 g Hz , in contrast with the value between 1 g Hz and 110 g Hz in typical bulk micro machined accelerometers . It is important to improve the noise performance of surface micro machined CMOS MEMS accelerometers.

3. CIRCUIT STRUCTURE:
Fig. 1 illustrates the overall architecture of the integrated sensing circuit. A continuous-time chopper stabilization technique was implemented. The sensor signal is first modulated to a higher frequency band before entering the band-pass, Closed-loop front-end amplifier. The fully differential circuit topology with a Fully bridged capacitive sensor was employed to reduce the effect of common mode interferences such as the noise coupled through substrate and power lines and to increase the signal dynamic range. The front-end amplifier converts the changing capacitance signal of the capacitive bridge to an amplified voltage signal representing the displacement of the proof mass. After amplification, the signal is demodulated by a demodulator (a mixer) back into the baseband. An on-chip, low-noise, 3-bit-gain-controlled instrumentation amplifier converts the differential signal to a single-ended output signal and provides an additional gain. The last section of the sensing circuit is a passive low-pass filter (LPF) that filters out the high-frequency

harmonic components from the modulation, to make the final Signal more band-limited.

Fig.1. the overall architecture of the sensing circuit. The overall architecture mainly consists of a. Front end amplifier b. Demodulator c. Instrumentation amplifier and low pass filter

A.FRONT END AMPLIFIER:

Fig. 2(a) shows a diagram of the full-bridge capacitive sensor and the differential, closed-loop front-end charge sensitive amplifier. Capacitors and represent the parasitic capacitances from the input nodes to the ground. and are the feedback capacitors. The detailed circuit of the core foldedcascode CMOS operational amplifier is shown in Fig. 2(b). The size parameters of all the transistors are clearly indicated in the figure. The operational amplifier includes a continuous-time common-mode feedback (CMFB) circuit. . The voltage at the

Fig.2. (a) differential front-end amplifier interfaced with the capacitive sensor. (b) the fully differential folded-cascode OPA with a continuous-time common mode feedback circuit. Output node was designed to be VDD/2.

B. DEMODULATOR:
A doubly balanced mixer based on a Gilbert cell topology, as shown in Fig, was used to transfer the high-frequency modulated sensing signal back to the baseband. The doubly balanced mixer has inherent port-to-port isolation capability making it Ideal for the use in integrated circuit design. The transconductance gains of the two input NMOS transistors, Mm1 and Mm2, convert the differential input voltage signal to a current signal. The other NMOS devices (Mm3-Mm6) form the section to mix the modulated current signal with the square-wave demodulation signal from the on-chip local oscillator (LO) and generate the demodulated output signal which includes the baseband sensing signal and the harmonics of the modulation frequency component. Source degeneration with resistors (Rm1 and Rm2) in the tail section of the mixer was applied to improve the linearity of the mixer.

Fig. The schematic of a doubly balanced mixer

C.INSTRUMENTATION AMPLIFIER AND LOW PASS FILTER

A low-noise programmable gain instrumentation amplifier (PGIA) converts the differential signal from the mixer into a single-ended signal. It

consists of three basic two-stage operational amplifiers which are connected as shown in Fig. Two of them (OPA and OPB) are arranged in a fully differential scheme and allow gain programmability, whereas the third one (OPC) performs the necessary differential-to-single-ended conversion while ensuring the required driving capability for the next stage. This structure provides high common-mode rejection ratio, high input impedance, dc gain adjustment by selecting different values of RGG, and adjustable dc offset by changing the control voltage Vcm. The value of RGG is adjusted through using the switches S1-S8 which are controlled by a 3-to-8 decoder, which results in a programmable gain of 19.574 V/V for the instrumentation amplifier

For the example CMOS MEMS surface micro machined accelerometer in this work, this gain range corresponds to system sensitivity range of 0.26 V/g0.983 V/g. Since both the baseband sensing signal and the harmonics of modulation frequency component from the mixer are amplified and appeared at the output of the instrumentation amplifier, the high-frequency harmonic components need to be removed by a low-pass filter.

4. DESIGN CONSIDERATIONS

1. MINIMIZING OFFSET. 2. DC BIAS STABILIZATION. 3. NOISE MINIMIZATION.

1. MINIMIZING OFFSET

Fig (a). The structure of trimming circuit. (b). the 4-bit controlled binaryweighted capacitor array used in (a). In CMOS MEMS capacitive accelerometers, process variation gradient causes position offset in the sensors. This sensor position offset in turn causes a capacitive offset signal indistinguishable from the actual sensor

signal. This offset cannot be automatically canceled by the amplifier. Therefore, some calibration to the sensor is needed before use. Since the sensor offsets are of capacitive mismatch in nature, they may be canceled at the interface between the sensors and the front-end amplifiers through adding small capacitors in parallel with the sensing capacitors. The CMOS MEMS capacitive sensor in the example of this work was designed to have 0.3 fF/g capacitance sensitivity for acceleration. It is impractical to build individual capacitors of this small size. Instead, four onchip 4-bit-controlled binary-weighted capacitor arrays were used for calibration in this work, as shown in Fig. The detailed structure of each array is shown in Fig. The effective value of capacitance of a 4-bit-controlled binary-weighted capacitor array was designed to range from 0.083fF to 1.24 fF, which corresponds to a sensing adjustment range from 0.276 g to 4.13 g.

2. DC BIAS STABILIZATION:

fig(a) .Single diode-connected NMOSFET connected to the output terminal of the front-end amplifier.

fig(b) .schematic illustration of the feedback NMOSFET (b). Dependence of the Ich and I sub,s in the sub threshold NMOSFET on the input node voltage. For the dc bias stabilization we use the sub threshold NMOSFET.In the above figure, the dc bias stabilization techniques are shown. In the above circuits the areas of the source body junction diode was designed to be large. At some particular point the value the Kirchhoffs law at node A is satisfied. So dc bias stabilization is done.

3. LOW NOISE DESIGN CONSSIDERATIONS:

A. Mechanical (Brownian) Noise:

For a sensor with proof mass and viscous damping coefficient, its Brownian noise corresponds to an equivalent acceleration noise according to the following equation.

Where is the Boltzmann constant J K and T is the absolute temperature. The above equation shows that increasing the mass of the sensor can lower the mechanical noise floor. B.Circuit Noise: Fig shows the simulated output noise spectrum of the differential closed-loop front-end amplifier. It is clear that at the modulation frequency (500 kHz), noise subsides and thermal noise dominates. As shown in Fig. 2(b), a fully differential folded-cascode CMOS operational amplifier (OPA) was chosen as the core of the closed-loop differential front-end amplifier. Transistors M2, M3, M4, M5, M10 and M11 contribute most of the thermal noise. At lower frequencies the 1/f noise is dominated one. In the internal circuit it produces the thermal noise.

Fig. output noise of the differential closed-loop front end amplifier

5. RESULTS:

6. CONCLUSION:
A complete sensing circuit that aims at reducing the noise, stabilizing the dc bias, and compensating the sensor offset of surface micro machined CMOSMEMS accelerometers has been presented in this work. The circuit employs an architecture of continuous-time, differential, closed-loop, voltage-sensing amplifier with chopper-stabilization. Each circuit block has been tailored for reducing noise. An on-chip trimming circuit is included for

cancelling the offset effect of the sensor. And a special efficient biasing scheme has been provided for stabilizing the input bias voltage. An example of the integrated surface micro machined CMOS MEMS accelerometer in TSMC 0.35 m 2P4M CMOS process was designed and implemented. Measurements showed good performance. The sensor offset was effectively compensated and the input dc bias voltage was well maintained. The sensitivity of the integrated accelerometer was measured to be 457 mV/g and the equivalent noise acceleration of the integrated system is 54 g Hz. The two-axis accelerometer system occupies only 5.66 mm chip area and consumes only 1.56 mA current at 3.3 V. 7. REFERENCES: [1] L. H. Zhang, G. G. K. Fedder, and L. R. Carley, A post-CMOS micro machined lateral accelerometer, J. Microelectromech. Syst., vol. 11, no. 3, pp. 188195, 2002. [2] G. K. Fedder, S. Santhanam, M. L. Reed, S. C. Eagle, D. F. Guillou, M. S.-C. Lu, and L. R. Carley, Laminated high-aspect-ratio microstructures in a conventional CMOS process, Sens. Actuators A, vol. 57, pp. 100103, 1996. [3] G. Zhang, H. Xie, L. E. de Rosset, and G. K. Fedder, A lateral capacitive CMOS accelerometer with structural curl compensation, in Tech. Dig. 12th IEEE Int. Conf. Micro Electro Mech. Syst. (MEMS 99), Orlando, FL, pp. 606 611. [4] J.Wu, G. K. Fedder, and L. R. Carley, A low-noise low-offset capacitive sensing amplifier for a 50 g/(Hz)^1/2 monolithic CMOS MEMS accelerometer, IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 722730, 2004.