Ec Manual New

Analog Electronics Circuits Laboratory Manual
EXPERIMENT NO. 1
RC COUPLED AMPLIFIER
AIM: To design and conduct of RC Coupled single stage (a) BJT (b) FET amplifier and determination of gain frequency response, input and output impedance COMPONENTS: Resistors, Capacitors, RPS, AFG, BJT SL100, FET BFW 10/11, DRB, Multimeter, Connecting Board and wires A. BJT RC COUPLED AMPLIFIER CIRCUIT DIAGRAM:
DESIGN:
a) To Find RE Assume VCC = 12V, VRE = 2V, IC = 4 mA, = 100(SL100) IE IC RE = VRE / IE = VRE/ IC = 2/4.0m = 470 RE = 470 (Std) b) To Find R1 and R2 VB = VBE + VRE = 0.7 + 2 = 2.7V IB = IC /= 4m/100 = 0.04mA
Dept of E&C, G.C.E., Ramanagaram
10IB
9IB
Assume 10IB flows in R1, 9IB flows in R2 R1 =( VCC VB)/ 10IB = (12 2.7)/ 10(0.04m) = 23.25K R1 = 22K (Std) VB = VR2 = 9IB * R2 R2 = VB /9IB = 2.7 / 9(0.04m) = 7.5K R2 = 6.8K (Std) c) To Find RC Choose VCE = VCC /2= 12/2 = 6V VCC ICRC VCE VRE = 0 12 (4m)RC 6 2 = 0 RC = 1K RC = 1K (Std) b) To Find CE, CC1 and CC2 XCE = RE /10 at f = 100Hz 1/2fCE = RE/10 CE = 10 / 2fRE = 10 /[2(100)(270)] CE = 47F (Electrolyte)
= 59F
Choose CC1 = CC2 = 0.47F. These are coupling capacitors to offer low reactance path for ac signal
B. FET RC COUPLED AMPLIFIER CIRCUIT DIAGRAM:
DESIGN: From data sheet of BFW 10/11 IDSS = 10 mA VP = - 3V or - 4V Let ID = 2mA a) To Find Rs : From the equation of the current ID = IDSS( 1 VGS/VP)2 ID / IDSS = ( 1 VGS/VP)2 Substituting for ID = IDSS and VD VGS = - 1.65 VGS = IDRS RS = VGS /ID =0.820K RS = 1K b) To Find RG : IGSRG = VGS RG = VGS/ IGS = 1.65 /1A = 1.65M RG = 2M c) To Find RD : Applying KVL VDD = IDRD +IDRS+VDS RD = (VDD-VDS IDRS)/ ID RD = 1.5K
Assume & set VDD = 10V then VDS = VDD = 5/2V
d) To Find Cs & CC Let f =100KHz XCS = RS /100 = 1000 /100= 10 XCS= 1/2fCS CS = 1/ 2fCE = 0.15f Cs= 0.15f Select C = 0.22f = CC1 = CC2
FOR BJT & FET AMPLIFIERS

PROCEDURE: a) To get frequency response: 1. The connection are made as shown in the circuit diagram 2. Before applying the input signal, the DC conditions are checked y setting Vcc = 12V. Vcc must be closed to 1/2Vcc = 6V. 3. Input sinusoidal signal (frequency = 1 KHz and voltage 50 mV peak-to-peak) should be applied using ASG. Care should be taken to get undistorted wave at the output, while applying input signal. 4. Keeping input signal Vin constant, the frequency of input is varied from 100Hz to 1MHz in suitable steps while measuring the output voltage for different frequencies. 5. The gain of the amplitude is calculated and tabulated. The graph of frequency Vs gain in dB is plotted on a semi log sheet. 6. Bandwidth is calculated from the frequency response. Also gain bandwidth product is computed. TABULAR COLUMN: Vs = _____________________mV Frequency(Hz) 100Hz Vo(P-P) (V) Gain Av = Vo/Vi Gain Av in dB = 20log10Av
1MHz
INPUT & OUTPUT WAVEFORM:

Vin (V)
V0(V) Vm t
FREQUENCY RESPONSE CURVE:
Gain in dB
b) To measure output impedance Zo:
1. DRB is connected as shown in the circuit and let the resistance of DRB be high in terms of several kilo ohms or mega ohms. 2. Keep the input frequency in the mid band region. 3. Output voltage Vo is measured 4. Resistance on DRB is decreased till Vo reduces to half of its value. The DRB value gives the output impedance Zo of an amplifier. c) To measure input impedance Zi:
1. DRB is connected as shown in the circuit and keep the resistance of DRB to zero. 2. Keep the input sine wave frequency in the mid band region. 3. Output voltage Vo is measured. 4. Resistance on DRB is increased till Vo reduces to half of its value. The DRB value gives the input impedance Zi of an amplifier. RESULT: 1. 2. 3. 4. 5. Bandwidth (BW) = _____________________Hz Midband gain = Amid = _____________________ Gain Bandwidth Product = BWxAmid = _______________ Input Impedance = _______________ Output Impedance = __________________
EXPERIMENT NO. 2
DARLINGTON EMITTER FOLLOWER

AIM: Designing and wiring of BJT Darlington emitter follower with & without bootstrapping and determination of gain, input and output impedances. COMPONENTS: Transistor SL100 (2 Nos), Resistors, Capacitors, RPS, 0-30 V RANGE, CRO, ASG, CRO probes CIRCUIT WITHOUT BOOTSTRAP CIRCUIT DIAGRAM:
DESIGN:
for SL 100, = 100 Let VCC=10V, IC1= 4mA, IC2=0 .4A VCE2= VCC /2= 5V Applying KVL to the output circuit VCC= VCE2+ ICE2 RE RE= VCC VCE2/IC2= 10-5/4m= 1.25k RE = 1 k (Std)
To find RE:
To find R1 & R2: Let, IB2= IC2/= 0.04ma IB1= IC1/= 0.4 A Let I1=10 I B1= (10)( 0.4A)= 4A I2= 9 IB1= 3.6 A R2= VR2/I2 = VRE+ VBE1+ V BE2/ I2= 5+0.6+0.6/3.6 = 1.7 M R2= 1M (Std) R1= VR1/I1= VCC V R2/ 4 = 10 6.2/4 = 0.75 M R1= 1M (Std)
CIRCUIT WITH BOOTSTRAP:
DESIGN: Let R3= 10K Bootstrap capacitor CB should be large. Select CB= 10f Zi (without bootstrap ) = hie + R3 = 11K Zi ( with bootstrap ) = Rs/ 1-Av = 10k/ 1- 0.95 = 200k PROCEDURE (for both with and without Bootstrap): 1) The circuit is connected as shown in the circuit diagram. 2) The DC condition is checked i e VCE = VCC/ 2 is measured which should be approximately 5V 3) A sine wave of 1V PEAK TO PEAK (1 KHz is applied to the input and output voltage is measured for different frequencies. The voltage gain = Vo/Vi should be approximately equal to 1 for different frequencies. 4) The same procedure is repeated with & without bootstrap. 5) Input and output impedances are measured for both the circuits. Procedure is same as RC coupled amplifier.
To measure output impedance Zo(for both with and without Bootstrap):
1. DRB is connected as shown in the circuit and let the resistance of DRB be high in terms of several kilo ohms or mega ohms. 2. Keep the input frequency in the mid band region. 3. Output voltage Vo is measured 4. Resistance on DRB is decreased till Vo reduces to half of its value. The DRB value gives the output impedance Zo of an amplifier. To measure input impedance Zi(for both with and without Bootstrap):
1. DRB is connected as shown in the circuit and keep the resistance of DRB to zero. 2. Keep the input sine wave frequency in the mid band region. 3. Output voltage Vo is measured. 4. Resistance on DRB is increased till Vo reduces to half of its value. The DRB value gives the input impedance Zi of an amplifier. EXPECTED INPUT & OUTPUT WAVEFORM (for both with & without Bootstrap):
Tabular column for without bootstrap: Vi = __________________ V Frequency (Hz) 100 HZ 1MHZ Tabular column for with bootstrap: Vi = __________________ V Frequency (Hz) 100 HZ 1MHZ RESULTS: 1. WITHOUT BOOTSTRAP : a) Voltage gain = A v = _______________________ b) Input impedance = Z i = ___________________ c) Output impedance = Zo = _______________________ 2. WITH BOOTSTRAP : a) Voltage gain = Av = ________________________ b) Input impedance = Z i = ________________________ c) Output impedance = Zo = ______________________
Vo(V)
A v= Vo/ Vi
Vo(V)
A v= Vo/ Vi
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EXPERIMENT NO. 3
VOLTAGE SERIES FEEDBACK AMPLIFIER

AIM: To design BJT voltage series feedback amplifier and determination of gain, frequency response, input and output impedance with and without feedback. COMPONENTS: Resistors, Capacitors, RPS, AFG, BJT SL100, DRB, Multimeter, Connecting Board and wires CIRCUIT DIAGRAM:
DESIGN: Assume Vcc = 12V VRE = VCC / 2 = 12/2 = 6V IC = 2mA = 115 (transistor Q1 & Q2 are BC1474 ) a) To Find RE Let VRE = 12/10 = 1.2V RE = VRE / IE = 1.2/2mA = 600 RE =600 (for the first stage alone, split the 600 resistance as 220 + 390) b) To Find R1 and R2 VB = VBE + VRE = 0.7 + 1.2 = 1.9V IB = IC / = 2m/115 = 17.35A Assume 10IB flows in R1, 9IB flows in R2 R1 = (VCC VB )/10IB = (12 1.9)/10(17.35) = 58.21K R1 = 56K
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VB = VR2 = 9IB * R2 R2 = VB /9IB = 1.9/ 9(17.35) R2 = 12K c) To Find RC Choose VCE = VCC/2 = 12/2 = 6V VCC ICRC VCE VRE = 0 12 (2m)RC 6 -1.2 = 0 RC = 2.4K RC = 2.2K b) To Find CE, CC1 and CC2
= 12.16 K
XCE = RE / 10 at f = 100Hz 1/2fCE = RE/10 CE = 10 / 2fRE = 10 / 2(100)(270) = 59F CE = 47F (Electrolyte) Choose CC1 = CC2 = 0.47F. These are coupling capacitors to offer low reactance path for ac signal II STAGE: Design of second stage is same as that of the first stage Let RF = 10K Calculation of feedback factor () theoretical The feedback amplifier is given by, = RE / (RE + Rf ) = 390 / (10K+390) = 0.037 (The value of is usually chosen between 0.01 to 0.1) PROCEDURE: a) To get frequency response: 1. The connection are made as shown in the circuit diagram 2. Before applying the input signal, the DC conditions are checked y setting Vcc = 12V. VCC must be closed to 1/2VCC = 6V. 3. Input sinusoidal signal (frequency = 1 KHz and voltage 50 mV peak-to-peak) should be applied using ASG. Care should be taken to get undistorted wave at the output, while applying input signal. 4. Keeping input signal Vin constant, the frequency of input is varied from 100Hz to 1MHz in suitable steps while measuring the output voltage for different frequencies. 5. The gain of the amplitude is calculated and tabulated. The graph of frequency Vs gain in Db (=20log Vo/Vin) is plotted on a semi log sheet. 6. Bandwidth is calculated from the frequency response. Also gain bandwidth product is computed.
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TABULAR COLUMN: Vi = _____________________mV Frequency(Hz) 100Hz Vo(P-P) (V) Gain Av = Vo/Vi Gain Av in dB = 20log10Av
1MHz EXPECTED WAVEFORM:
FREQUENCY RESPONSE CURVE:

W o t fe db c ith u e a k
G in a ind B
Whfe db c it e a k
f1 f1 1
f2
f2 2
F(H ) z
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b) To measure output impedance Zo:
1. DRB is connected as shown in the circuit and let the resistance of DRB be high in terms of several kilo ohms or mega ohms. 2. Keep the input frequency in the mid band region. 3. Output voltage Vo is measured 4. Resistance on DRB is decreased till Vo reduces to half of its value. The DRB value gives the output impedance Zo of an amplifier. c) To measure input impedance Zi:
1. DRB is connected as shown in the circuit and keep the resistance of DRB to zero. 2. Keep the input sine wave frequency in the mid band region. 3. Output voltage Vo is measured. 4. Resistance on DRB is increased till Vo reduces to half of its value. The DRB value gives the input impedance Zi of an amplifier. RESULT: A. WITH FEEDBACK 1. 2. 3. 4. 5. Bandwidth (BW) = _____________________Hz Midband gain = Amid = _____________________ Gain Bandwidth Product = BWxAmid = _______________ Input Impedance = _______________ Output Impedance = __________________
B. WITHOUT FEEDBACK 1. 2. 3. 4. 5. Bandwidth (BW) = _____________________Hz Midband gain = Amid = _____________________ Gain Bandwidth Product = BWxAmid = _______________ Input Impedance = _______________ Output Impedance = __________________
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EXPERIMENT NO. 4
RC PHASE SHIFT OSCILLATOR

AIM: Wiring and testing for the performance of BJT-RC phase shift Oscillator for f0 10 KHz COMPONENTS: Transistor SL100 (1 number), Resistor, capacitors, RPS (0-30 range), CRO, ASG, CRO probes, Multimeter, Connecting wires and board. CIRCUIT DIAGRAM:
VC C 1 V 2
0.1 F R1 2 K 2 RC 1K V0 0.0 7 4 f
1
1K S 10 L 0 P T O 1k R2 6.8K RE 40 7
0.0 7 4 f
0.0 7 4 f
4
1K o r 5K pt o
1K
CE 4 7 F
NOTE: Point 1, 2, 3 & 4 are to observe the different phase shift of the RC phase shift oscillator. Design For tank circuit: f0= 1/[2RC(6+4k)] Where k = RC/R
Assume f0 = 1 KHz, R = 1K From design RC = 1K k = RC /R = 1 C = 1/[2R f0(6+4k)] C = 1/[2 (1K)(1K)(6+4)] = 0.0503 f Select C 0.047 f (Std)
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NOTE: The hfe of SL100/BC107 is 100. The value of 4k +23 +29/k is 56. Hence, Condition for sustained Oscillation i.e. hfe 4k +23 +29/k is satisfied. Design of an amplifier: a) To Find RE Assume VCC = 12V, VRE = 2V, IC = 4 mA, = 100(SL100) IE IC RE = VRE / IE = VRE/ IC = 2/4.0m = 470 RE = 470 (Std) b) To Find R1 and R2 VB = VBE + VRE = 0.7 + 2 = 2.7V IB = IC /= 4m/100 = 0.04mA Assume 10IB flows in R1, 9IB flows in R2 R1 =( VCC VB)/ 10IB = (12 2.7)/ 10(0.04m) = 23.25K R1 = 22K (Std) VB = VR2 = 9IB * R2 R2 = VB /9IB = 2.7 / 9(0.04m) = 7.5K R2 = 6.8K (Std) c) To Find RC Choose VCE = VCC /2= 12/2 = 6V VCC ICRC VCE VRE = 0 12 (4m)RC 6 2 = 0 RC = 1K RC = 1K (Std) d) To Find CE XCE = RE /10 at f = 100Hz 1/2fCE = RE/10 CE = 10 / 2fRE = 10 /[2(100)(270)] CE = 47f (Electrolyte)
= 59F
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EXPECTED WAVEFORMS: 1. Output Waveform: V0
2. Lissageous Pattern
Point1, 1 = 0
point 2, 2 = 60
A B
point 3, 3 = 120 2 = tan-1 ( B/A ) 3 = 180- tan-1 ( B/A)
point 4, 4 = 180
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PROCEDURE: 1. The amplifier is rigged up as per the circuit and DC conditions is checked i.e. VCE = VCC 2. After getting the above DC condition, the entire circuit has to be rigged up. 3. 4. CRO (1st channel) has to be connected between points(1) and ground to observe Sinusoidal waveform. For proper undistorted output, the 1K or 5 K pot has to be adjusted.
5. The frequency & amplitude of the sine wave is noted at the output. 6. Theoretical frequency should be compared with practical frequency.
Procedure to observe Lissageous pattern (or phase shift): 1. Keep the time/sec knob in X-Y position & output voltage VO point to channel1 fixed. 2. To observe the different angles , keep the channel 2 to different points 1, 2, 3 & 4 respectively, one at a time as shown in the table below: Angle (Degree) 0 60 120 180 RESULT: 1. 2. 3. 4. 5. 6. f pract= 1/T Hz = .. Hz & fth.. Hz VOP-P =. Volts 1= . Degree 2 = Degree 3 =.Degree 4 =.Degree Channel 2 point 1 point 2 point 3 point 4
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EXPERIMENT N0. 5
HARTLEY & COLPITTS OSCILLATORS

AIM: To test the performance of BJT Hartley and Collpitt Osicillator for RF range f0 100KHz COMPONENTS: Resistors, capacitors and Inductors, RPS( 0 -30V ), Multimeter, CRO, CRO probes, SL100/BC107, Connecting wires & Board.
A. HARTLEY OSCILLATOR
CIRCUIT DIAGRAM:
Vc c 1 V 2
R1 2 K 2 0.1 f RC 1K 0.1 f V
o
0.1 f
S 10 L 0
R2 6.8K RE 40 7 PT O 1K CE 4 f 7
L1 5m H C 30 p 3 f
L2 2.6m H
DESIGN OF TANK CIRCUIT Assume fo = 100KHz C = 330 pf fo = 1 / 2 ( LeqC) Leq = 1 / (2fo)2C =1 / [(2x 100K)2330p] = 7.68 mH Leq = L1 + L2 = (5 + 2.6)mHz L1 = 5mH, L2 = 2.6mH NOTE: The hfe of SL100/BC107 is 100 and ratio of L1 / L2 is 2. Hence, Condition for sustained Oscillation i.e. hfe L1 / L2 is satisfied.
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B. COLPITTS OSCILLATOR
CIRCUIT DIAGRAM:
Vcc 12 V 0.1f R1 22K 0.1f RC 1k 0.1f V
o
SL 100
R2 6.8K RE 470 POT 1K CE 47 f
C1 1000 pf L 3.6mH
C2 2200 pf
DESIGN OF TANK CIRCUIT Assume fo = 100KHz Assume C1 = 1000pF C2 = 2200pF fo = 1 / 2 ( LeqC) Ceq = ( C1* C2 )/ (C1 + C2) = 687.801 L = 1 / ( (2fo)2C ) = 1 / [(2x 100K)2687.8] L = 3.6 mH NOTE: The hfe of SL100/BC107 is 100 and ratio of C2 / C1 is 2.2. Hence Condition for sustained Oscillation i.e. hfe C2 / C1 is satisfied.
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AMPLIFIER DESIGN OF BOTH THE OSCILLATORS a) To Find RE Assume VCC = 12V, VRE = 2V, IC = 4 mA, = 100(SL100) IE IC RE = VRE / IE = VRE/ IC = 2/4.0m = 470 RE = 470 (Std) b) To Find R1 and R2 VB = VBE + VRE = 0.7 + 2 = 2.7V IB = IC /= 4m/100 = 0.04mA Assume 10IB flows in R1, 9IB flows in R2 R1 =( VCC VB)/ 10IB = (12 2.7)/ 10(0.04m) = 23.25K R1 = 22K (Std) VB = VR2 = 9IB * R2 R2 = VB /9IB = 2.7 / 9(0.04m) = 7.5K R2 = 6.8K (Std) c) To Find RC Choose VCE = VCC /2= 12/2 = 6V VCC ICRC VCE VRE = 0 12 (4m)RC 6 2 = 0 RC = 1K RC = 1K (Std) d) To Find CE, CC1 and CC2 XCE = RE /10 at f = 100Hz 1/2fCE = RE/10 CE = 10 / 2fRE = 10 /[2(100)(270)] = 59F CE = 47f (Electrolyte) Choose CC1 = CC2 = 0.47f. These are coupling capacitors to offer low reactance path for ac signal
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EXPECTED OUTPUT: Vo(V)
PROCEDURE: 1) The amplifier circuit is rigged up as shown in the circuit diagram & the DC condition is checked i.e. VCE = VCC 2) After checking the above condition, tank circuit is also connected and the output is observed between collector and the ground. 3) Undistorted sine wave is obtained by adjusting the variable inductor /capacitor 4) The amplitude and frequency of the sine wave is noted. 5) Practical frequency is compared with theoretical frequency. RESULT: Hartley oscillator: 1) VOP-P = ________________V 2) F(theo) = ________________ KHz 3) f( pract) = _______________KHz Colpitts Oscillator: 1) VOP-P = _______________V 2) f (theor) = _______________ KHz 3) f ( pract) = ______________ KHz
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EXPERIMENT NO. 6
BJT CRYSTAL OSCILLATOR

AIM: Testing for the performance of BJT crystal oscillator for f0 > 100 KHz
COMPONENTS: Resistor, SL100 (NPN), 1MHz or 2MHz crystal, Capacitors, RPS(0-30V range),1K Potentiometer, Connecting wires and board. CIRCUIT DIAGRAM:
Vcc 12V 0.1f V
o
R1
22 K
CRYSTAL 2 MHz
RC 1K
0.1f SL 100 R2 6.8K 1000 pf RE 470 CE 47f POT 1K
EXPECTED OUTPUT WAVEFORM: Vo(V) ftheo = 2 MHz f = 1/T T(Sec)

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AMPLIFIER DESIGN: a) To Find RE Assume VCC = 12V, VRE = 2V, IC = 4 mA, = 100(SL100) IE IC RE = VRE / IE = VRE/ IC = 2/4.0m = 470 RE = 470 (Std) b) To Find R1 and R2 VB = VBE + VRE = 0.7 + 2 = 2.7V IB = IC /= 4m/100 = 0.04mA Assume 10IB flows in R1, 9IB flows in R2 R1 =( VCC VB)/ 10IB = (12 2.7)/ 10(0.04m) = 23.25K R1 = 22K (Std) VB = VR2 = 9IB * R2 R2 = VB /9IB = 2.7 / 9(0.04m) = 7.5K R2 = 6.8K (Std) c) To Find RC Choose VCE = VCC /2= 12/2 = 6V VCC ICRC VCE VRE = 0 12 (4m)RC 6 2 = 0 RC = 1K RC = 1K (Std) d) To Find CE XCE = RE /10 at f = 100Hz 1/2fCE = RE/10 CE = 10 / 2fRE = 10 /[2(100)(270)] CE = 47f (Electrolyte) (Std)
= 59F
24
PROCEDURE: 1. The circuit (amplifier part) has to be rigged up as per the diagram. 2. DC condition should be checked (VCE =1/2Vcc = 5V) 3. By connecting the tank circuit, the oscillations are observed at the collector. 4. To get undistorted sine wave output, 1K pot can be slightly be adjusted. 5. The frequency of the sine wave (f =1/T) is calculated and noted. RESULT: 1. f pract =. Hz 2. V o(p-p) =.. Volts
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EXPERIMENT NO 7 DIODE CLIPPING CIRCUITS

AIM: To test the diode clipping (single/double ended) circuits for peak clipping and peak detection COMPONENTS: Diode BY127, Resistors, DC Regulated Power Supply, Connecting Wires and Board, ASG, CRO Probes. 1. POSITIVE CLIPPER: Circuit Diagram:
1 K 0
A FG V i 1 Vp 0 p 1K z H
+ + -
B 1 Y 27 VR
1.4V
V o
Design: Let the output be clipped to say +2V Vo(max) = +2V Vo(max) = Vf+Vref (Assume Vf = 0.6) Vref = Vo(max) Vf Vref = 1.4V The value of resistor R is chosen is R = RfRr where Rf =10 R = 10K Rr = 10M Waveform:
Vin (V) 1 Vp 0 p
Vm = 5V
t
Transfer Characteristic:
V0(V)
2V
t
T F = 1/T
26
VO (V) 2V 2V Vin (V)
2. NEGATIVE CLIPPER: Circuit Diagram:

1 K 0
AG F V i 1 Vp 0 p 1K z H
B 17 Y 2
VR
1.4V
V o
Design: Let the output be clipped to say -2V Vo(min) = -2V Vo(min) = Vf + Vref (without sign) (Assume Vf = 0.6) Vref = Vo(min) Vf = -2 (-0.6) = -1.4V The value of resistor R is chosen is R = RfRr where Rf =10 = 10K Rr = 10M Waveform:
Vin (V) 1 Vp 0 p
V0(V) Vm -2V T F = 1/T 5 V
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VO (V)
-2V -2V Vin (V)
3. DOUBLE ENDED CLIPPER (i) Clipping at independent levels: Circuit Diagram:

1 K 0
B 12 Y 7
B 12 Y 7
Vref 2
2.6V
V o Vref 1
3.4V
Design: Let the output be clipped to say below 2V and 4V level Vo(max) = 4V Vo(min) = 2V Vo(max) = Vf+Vref1 (Assume Vf = 0.6) Vref1 = Vo(max) Vf = 4 0.6 = 3.4V Vref1 = 3.4V Vo(min) = -Vf+Vref 2 Vref2 = Vo(min) + Vf = 2 + 0.6 = 2.6 V Vref2 = 2.6 V The value of resistor R is chosen is R = RfRr R = 10K where Rf =10 Rr = 10M
Waveform:
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Vin (V) 1 Vp 0 p
t
V0(V) 4V 2V
t
Vm 5V
T F = 1/T
VO(V) 4V 2V 0 2V 4V Vin (V)
(ii) Square Wave Generator: Circuit Diagram:

1 K 0
B 17 Y 2
B 17 Y 2
Vref 2
1.4V
+ Vref 1
V o
1.4V
Design: Let the output be clipped to say below +2V and -2V level Vo(max) = +2V Vo(min) = -2V Vo(max) = Vf+Vref1 (Assume Vf = 0.6) Vref1 = Vo(max) Vf = 2 0.6 = 1.4V -Vo(min) = -(Vf+Vref 2 ) Vref2 = Vo(min) - Vf = -2 (- 0.6)
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= -1.4 V The value of resistor R is chosen is R = RfRr where Rf =10 = 10K Rr = 10M Waveform:
Vin (V) 1 Vp 0 p
t
V0(V) Vm 5V
t
2 V -2 V
T F = 1/T
VO (V) 2V -2V 2V -2V Vin (V)
PROCEDURE: 1. The circuits are connected as per the diagrams. 2. By giving input as 10V peak-to-peak outputs are observed and compared with the actual waveforms (i.e. Vin(peak) > Vref). 3. Different clipping levels are noted for all circuits by connecting input to 1st channel of the CRO and output to 2nd channel. 4. The corresponding transfer characteristics are observed using X via Y mode. RESULTS: The following different clippers are verified: 1. Positive Clipper 2. Negative Clipper 3. Double Ended Clipper
a. Slice Circuit
b. Square wave generator
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EXPERIMENT NO 8
DIODE CLAMPING CIRCUITS

AIM: To design and test positive and negative clamping circuits. COMPONENTS: Diode BY127, Resistors, Capacitor, DC Regulated Power Supply, Connecting Wires and Board, ASG, CRO Probes. DESIGN: For all the circuits, the time constant RC>>T Let RC = 100T (Condition for Stiff Clamper) Assume T = 1msec i.e. F =1KHz R = 10K 100T (100) (1msec) C = -------- = -------------- = 10 f R 10K C = 10 f 1. NEGATIVE PEAK CLAMPER OR POSITIVE CLAMPER A) WITH POSITIVE REFERENECE Circuit Diagram:
C
1 f 0
AG F V i
1 Vp 0 p 1K z H
B 17 Y 2
VR
2.6V
R V o 1 K 0
Design: The value of resistor R is chosen is R = RfRr where Rf =10 R = 10K Rr = 10M Design for Vo(min) = +2V Vo(min) = +Vref - Vf (Assume Vf = 0.6) Vref = Vo(min) + Vf = 2 + 0.6 Vref = +2.6V Capacitor voltage, Vc = Vm + Vref - Vf
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Vo = +Vi + Vc = +Vi + [ Vm - Vf + Vref ] From equation (1) Vi Vo 0 Vm - Vf + Vref Vm 2Vm - Vf + Vref -Vm - Vf + Vref Waveform:
Vin (V) 5V 10 Vp-p 0 -5V VO(V) 12V
t(sec )
(1)
Vo(V) Vi(V) Theoretical Practical 0 7 5 12 -5 2
2V 0
t(sec ) T f=1/T
B) WITH NO REFERENCE Circuit Diagram:

C 1 f 0
AG F V i
1 Vp 0 p 1K z H
+
B 17 Y 2
R 1 K V 0 o
Design: The value of resistor R is chosen is R = RfRr where Rf =10 R = 10K Rr = 10M Design for Vo(min) = 0V From equation (1) Vo = +Vi + Vc = +Vi + [ Vm - Vf + Vref ]
(1) 32
Vref = 0V Assume Vf = 0.6V Vi Vo 0 Vm - Vf Vm 2Vm - Vf -Vm - Vf Waveform:

Vin (V) 5V 1 Vp-p 0 0 -5V VO(V) 9.4V
t(s c ) e
Vo(V) Vi(V) Theoretical Practical 0 4.4 5 9.4 -5 -0.6
0 -0.6V
T f =1/T t(s c ) e
C) WITH NEGATIVE REFERENCE Circuit Diagram:

C
1 f 0
AG F V i
1 Vp 0 p 1K z H
B 17 Y 2
VR
1.4V
R 1 K 0
V o
Design: The value of resistor R is chosen is R = RfRr where Rf =10 R = 10K Rr = 10M Design for Vo(min) = - 2V Vo(min) = -Vref - Vf (Assume Vf = 0.6) Vref = - Vo(min) - Vf = - 2 - 0.6 = -1.4V Capacitor voltage, Vc = Vm - Vref - Vf
33
Vo = +Vi + Vc = +Vi + [ Vm - Vf - Vref ] From equation (1) Vi Vo 0 Vm - Vf - Vref Vm 2Vm - Vf - Vref -Vm - (Vf + Vref) Waveform:
Vin(V) 5V 10Vp-p 0 -5V VO(V) 8V
t(sec )
(1)
Vo(V) Vi(V) Theoretical Practical 0 5.8 5 8 -5 -2
0
t(sec )
-2V
T f =1/T
2. POSITIVE PEAK CLAMPER OR NEGATIVE CLAMPER A) WITH POSITIVE REFERENCE Circuit Diagram:
C
1 f 0
AG F V i
1 Vp 0 p 1K z H
B 17 Y 2
+ VR
R o 1 K V 0
1.4V
Design: The value of resistor R is chosen is R = RfRr where Rf =10 = 10K Rr = 10M Design Vo(max) = +2V
34
Vo(min) = +Vref + Vf (Assume Vf = 0.6) Vref = Vo(max) - Vf = 2 - 0.6 = 1.4 V Vref = 1.4V Capacitor voltage is considered when diode conducting Vi - Vc - Vref - Vf = 0 Vc = Vi - Vref - Vf Output voltage +Vi - Vc Vo = 0 Vo = Vi - Vc = +Vi - [Vi - Vref - Vf] = +Vi - [ Vm - Vf - Vref ] (2) From equation (2) Vi Vo 0 -Vm +Vf + Vref Vm + Vf + Vref -Vm -2Vm + Vf + Vref Waveform:
Vin(V) 5V 10 Vp-p 0 -5V VO(V) 2V 0
t(sec ) t(sec )
Vo(V) Vi(V) Theoretical Practical 0 -3 5 2 -5 -8
-8V
T f =1/T
B) WITH NO REFERENCE Circuit Diagram:

C
1 0 f
AG F V i
1 Vp 0 p 1Kz H
B 17 Y 2
R 1 K 0
V o
35
Design: The value of resistor R is chosen is R = RfRr where Rf =10 R = 10K Rr = 10M From equation (2) Design for Vo(max) = 0V Vo = Vi - Vc = +Vi - [Vi - Vref - Vf] = +Vi - [ Vm - Vf - Vref ] Vref = 0V Assume Vf = 0.6V Truth Table: Vi 0 Vm -Vm Waveform:
Vin (V) 5V 1 Vp-p 0 0 -5V VO(V) 0.6V 0
t(s c ) e t(s c ) e
(2)
Vo(V) Vo Vi(V) Theoretical Practical - Vm + Vf 0 -4.4 + Vf 5 0.6 - 2Vm + Vf -5 -9.4
-9.4V
T f =1/T
C) WITH NEGATIVE REFERENCE Circuit Diagram:

C
1 f 0
AG F V i
1 Vp 0 p 1K z H
B 17 Y 2
VR
2.6V
R 1 K 0
V o
36
Design: The value of resistor R is chosen is R = RfRr where Rf =10 R = 10K Rr = 10M Design for Vo(max) = - 2V Vo(max) = -Vref + Vf (Assume Vf = 0.6) Vref = - Vo(max) - Vf = - (- 2) + 0.6 Vref = +2.6V (magnitude) Capacitor voltage, Vc = Vm - Vref - Vf Vo = +Vi - Vc = +Vi - [ Vm - Vf + Vref ] From equation (1) Vi 0 Vm -Vm Waveform:
Vin (V) 5V 1 Vp-p 0 0 -5V
T f =1/T t(se ) c
(1)
Vo - [Vm - Vf + Vref] Vf - Vref - 2Vm + Vf - Vref
Vo(V) Vi(V) Theoretical Practical 0 -7 5 -2 -5 -12
0 -2V
t(se ) c
-1 V 2 VO(V)
PROCEDURE: 1. The circuit is rigged up as shown in the circuit diagram. 2. A square wave of amplitude 10V peak-to-peak is given as input. (sine wave can also be input) 3. Output is observed on the CRO for each circuit by putting the amplitude knob to DC and should be compared with theoretical waveform. 4. The different clamping levels should be noted for each circuit. RESULT: The given waveform for both the positive and negative clamping is verified. OBSERVATION: 1. Only dc shift is observed at the output. 2. The shape, time period and peak-to-peak amplitude of the output is same as input
37
EXPERIMENT NO 9
CLASS-B PUSH PULL AMPLIFIER

AIM: To determine the conversion efficiency of Transformer less Class-B Push Pull amplifier. COMPONENTS: AFG, Load resistor (75, 10Watts), CRO, Power supplies, transistors (SL100, SK100) CIRCUIT DIAGRAM:
1 V 2 RS P
S 10 L 0 0.1f 0.1f 1 V -P 0 P 1K z H
A C
Vi
S 10 K 0
V o(P-P)
7 5 1 W 0
-1 V 2 RS P
DESIGN: Assume RL as 75 (10Watts) and VCC = 12V When Power developed is maximum Vm = VCC RL = V m / Im Im = Vm /RL =Vcc/RL = 12/75 = 0.16 A Pdc = (2/)(VCC*Im)Watt = (2/)( 12 x 0.16) = 1.22W Pac = V2CC/2RL = 122 / 2 x 75 = 0.96W % = Pac /Pdc*100 % = 0.96/1.22 * 100% = 78.6%
38
Theoretical value of % is also 78.5% Hence choose RL as 75 (10Watts) CALCULATIONS: Take Vm across the load resistor RL through CRO. Vm = VO(P-P)/2 Im = Vm /RL Pdc = (2/)(Vm*Im)Watt Pac = V2m/2RL Conversion Efficiency, % = (Pac /Pdc) * 100% OUTPUT WAVEFORM: V0(V) Vm
PROCEDURE: 1. Connect the circuit as shown in the fig and switch on the power supply. 2. AFG is set to 10V,1KHz sine wave applied to the input of the circuit 3. Measure output across the RL and not the value of Vm 4. Calculate the conversion efficiency RESULT: Conversion Efficiency of Class-B Push Pull amplifier is =_______%
39
EXPERIMENT NO 10
RECTIFIER CIRCUITS
AIM: To test half wave, full wave, bridge wave rectifier circuits with and without capacitor filter. Determination of ripple factor, regulation and efficiency, COMPONENTS: Transformer (12-0-12)V, Diodes (BY127), Power Resistor (75, 10W), Connecting Wires and Board, CRO Probes. THEORY: For Half Wave Rectifier Vdc = Vm / Vrms = Vm / 2 Ripple factor, = Vac / Vdc Vac = (V2rms V2dc ) /Vdc = [( Vm/ 2) 2 (Vm/ ) 2 ] / (Vm/ ) = [( 1/ 2) 2 (1/ ) 2 ] / (1/ ) = 1.21 Efficiency, % = (V2dc / V2rms) * 100 = [I2dc R / I2rms (R+Rf)] * 100 = [(Im/ ) 2R / (Im/ 2)2 (R+Rf)] * 100 = [(1/ ) 2 R / (1/ 2)2 (R+Rf)] * 100 = [(1/ ) 2 / (1/ 2)2] * [R/ (R+Rf)] * 100 = [(1/ ) 2 / (1/ 2)2] ( If Rf << R, Rf can be neglected ) 2 = 4 / * 100 = 40.5 %
% Voltage regulation, %R = (Rf +Rs)/RL* 100% Rf & Rs is very small compared to RL, hence voltage regulation is very small.
For Full Wave Rectifier Vdc = 2Vm / Vrms = Vm / 2 Ripple factor, = Vac / Vdc Vac = (V2rms V2dc ) = [( Vm/ 2) 2 (2Vm/ ) 2 ] / (2Vm/ ) = [( 1/ 2) 2 (2/ ) 2 ] / (2/ ) = 0.483
40
Efficiency, % = (V2dc / V2rms) * 100 = [I2dc R / I2rms (R+Rf)] * 100 = [(2Im/ ) 2R / (Im/ 2)2 (R+Rf)] * 100 = [(2/ ) 2 R / (1/ 2)2 (R+Rf)] * 100 = [(2/ ) 2 / (1/ 2)2] * [R/ (R+Rf)] * 100 = [(4/ 2) / (1/ 2)] ( If Rf << R, Rf can be neglected ) 2 = 8 / * 100 = 81.1 % Theortical Values: Parameters Efficiency, % Ripple factor, Half wave rectifier 40.6% 1.21 Full wave rectifier (Center tap and Bridge) 81.2% 0.48
1. HALF WAVE RECTIFIER (HWR) with out Filter:

a) CIRCUIT DESIGN: Load Resistor, RL: Assume Vdc = 5.5V, Idc = IL = 75mA; Rf = 8 RL = Vdc / Idc = 5 / 75m RL = 75 RL = 75 , 10Watts (Std) Transformer:
Vdc = (Vm / ) - Idc Rf Vm = (Vdc + Idc Rf) Vm = 16.96 V Vrms = Vm / 2 = 16.96 / 2 = 11.96 12V is required as input voltage to the rectifier. Use 12 0 12V Transformer
b) CIRCUIT DIAGRAM:
12V
BY127
RL 75 10W
230V 50Hz
Ac supply 0V
V0
41
c) PRACTICAL DESIGN: Vm from output figure Average or DC value of voltage, Vdc = Vm/ rms value of voltage, Vrms = Vm/ 2 Vac = (V2rms V2dc ) Ripple factor, = Vac / Vdc Efficiency, % = (V2dc / V2rms) * 100
% Voltage regulation, %R = [(VNL VmFL) / VmFL ]* 100

d) EXPECTED OUTPUT WAVEFORM:
Vin (V)
V0(V) Vm t
e)TABULAR COLUMN: VNL =_________V VmFL =_________V Vm =_________V Vrms(V) Vdc(V) Vac(V) Ripple factor Efficiency Voltage regulation % %R
2. HALF WAVE RECTIFIER (HWR) with C- Filter:

a) CIRCUIT DESIGN: Load Resistor: Assume Vdc = 17V, Idc = IL = 775mA; Rf = 8 RL = Vdc / Idc = 5 / 225m RL = 75 RL = 75 , 10Watts (Std)
42
Transformer:
Vdc = (Vm / ) + Idc Rf Vm = (Vdc - Idc Rf) Vm = 16.99 V Vrms = Vm / 2 = 16.99 / 2 = 12 12V is required as input voltage to the rectifier. Use 12 0 12V Transformer
Capacitor: Choose C = 470 f
Assume f = 50Hz, RL =75 , 10Watts

= 1 / 23fRLC = 0.163 = 0.163 Also the theoretically the value of is 0.163 b) CIRCUIT DIAGRAM:
BY127
12V
230 V 50Hz
Ac supply 0V
RL 75, 10W
470 f
V0
c) PRACTICAL DESIGN:
Vr (p-p) , Vm is taken from the output wave form

Vdc = Vm (Vr (p-p) / 2) Vrms = Vr (p-p) / 23 = Vrms / Vdc
%R = [(VNL VmFL) / VmFL ]* 100

43
Vin(V)
V0(V) W ith out filter t Vr(P-P) Vm t
V0(V) W ith C-filter
e) TABULAR COLUMN: VmFL =_________V VNL =_________V Vm =_________V Vr(P-P)(V) VDC(V) Vrms(V) Ripple factor Voltage regulation %R
3. CENTER-TAPPED FULL WAVE RECTIFIER with out filter:

a) CIRCUIT DESIGN: Load Resistor: Assume Vdc = 11V, Idc = IL = 150mA; Rf = 8 RL = Vdc / Idc = 5 / 150m RL = 73.33 Choose RL = 75 , 10Watts Transformer:
Vdc = (2Vm / ) - Idc Rf Vm = (Vdc + Idc Rf)/2 Vm = 16.96 V Vrms = Vm / 2 = 16.96 / 2 = 11.96 12V is required as input voltage to the rectifier.
44
Use 12 0 12V Transformer

b) CIRCUIT DIAGRAM:
1 V 2
B 17 Y 2
RL 7 5 1 W 0
20 V 3 5 H 0 z
A c s p ly up
V0
0V
1 V 2
B 17 Y 2
c) PRACTICAL DESIGN: Vm is taken from the output wave form Vdc = 2Vm / ) Vrms = Vm / 2 Vac = (V2rms V2dc ) = Vac / Vdc % = (V2dc / V2rms) * 100

Vin(V)
V0(V) Vm t
45
e) TABULAR COLUMN:
VmFL =_________V
VNL =_________V Vm =_________V Vrms(V) Vdc(V) Vac(V) Ripple factor Efficiency Voltage regulation % %R
4. CENTER-TAPPED FULL WAVE RECTIFIER with C - filter:

Vdc = (2Vm / ) - Idc Rf Vm = (Vdc + Idc Rf)/2 Vm = 16.96 V Vrms = Vm / 2 = 16.96 / 2 = 11.96 12V is required as input voltage to the rectifier. Use 12 0 12V Transformer
Assume f = 50Hz, RL =75

= 1 / 43fRLC = 0.082 = 0.082 Also the theoretically the value of is 0.082
46
b) CIRCUIT DIAGRAM:
B Y127 12V RL 75 10W
230 V 5 0H z
Ac su p p ly
0V
470 f
V0
12V B Y127
Vr (p-p) ,Vm is taken from the output wave form

Vdc = Vm (Vr(p-p) / 2) Vrms = Vr(p-p) / (23) Ripple factor, = Vrms / Vdc
Voltage regulation, %R = [(VNL VmFL) / VmFL ]* 100

47
Vin(V)
V0(V) With out filter
Vm t
V0(V) With Cfilter t
Vr(P-P)
e) TABULAR COLUMN:
VmFL =_________V
VNL =_________V Vm =_________V Vr(p-p) (V) VDC(V) Vrms(V) Ripple factor Voltage regulation %R
5. FULL WAVE BRIDGE RECTIFIER without filter:

Vdc = (2Vm / ) - Idc Rf

48
Vm = 16.96 V Vrms = Vm / 2 = 16.96 / 2 = 11.96 12V is required as input voltage to the rectifier. Use 12 0 12V Transformer
b) CIRCUIT DIAGRAM:
12 V
Vm = (Vdc + Idc Rf)/2
230 V 50 Hz
Ac supply
D1
D3
RL 75 10W
D2
12 V
V0
D4
D 1, D2, D3, D4 -- BY 127
c) PRACTICAL DESIGN: Vm is taken from the output wave form Vdc = 2Vm / Vrms = Vm / 2 Vac = (V2rms V2dc ) = Vac / Vdc % = (V2dc / V2rms) * 100

Vin (V)
V0(V) Vm t
e) TABULAR COLUMN:
VmFL =_________V
49
VNL =_________V Vm =_________V Vrms(V) VDC(V) Vac(V) Ripple factor Efficiency Voltage regulation % %R
6. FULL WAVE BRIDGE RECTIFIER with C - filter:

a) CIRCUIT DESIGN: Load Resistor: Assume Vdc = 17V, Idc = IL = 225mA; Rf = 8 RL = Vdc / Idc = 5 / 225m RL = 75.5 Choose RL = 75 , 10Watts (Std) Transformer:
Vdc = (2Vm / ) - Idc Rf Vm = (Vdc + Idc Rf)/2 Vm = 16.96 V Vrms = Vm / 2 = 16.96 / 2 = 11.96 12V is required as input voltage to the rectifier. Use 12 0 12V Transformer
Assume f = 50Hz, RL =75

= 1 / 43fRLC = 0.082 = 0.082 Also the theoretically the value of is 0.082 b) CIRCUIT DIAGRAM:
12 V
230 V 50 H z
A c supply
D1
D3 RL 75 10 W D4 470 f
V0
D2 12 V
D 1, D 2, D3 ,D4 -- BY 127
Vr (p-p) ,Vm is taken from the output wave form

50
Vdc = Vm (Vr(p-p) / 2) Vrms = Vr(p-p) / (23) = Vrms / Vdc % = (V2dc / V2rms) * 100

Vin (V)
V0(V) Wh it ot u f e ilt r
Vm t
V0(V) Wh it Cf e ilt r t
Vr(P-P)
e) TABULAR COLUMN:
VmFL =_________V
VNL =_________V Vm =_________V Vr(p-p) (V) VDC(V) Vrms(V) Ripple factor Voltage regulation %R
PROCEDURE: 1. The circuit is rigged up as per the circuit diagram. 2. Input AC is applied & output waveform should be noted. 3. Output voltage Vm is noted for rectifier without filter from CRO or multimeter. Output voltage Vr (p-p) is noted for rectifier with filter from CRO or multimeter , 4. With load resistor (RL), output voltage VNL is measured. The output voltage is with RL is denoted by VFL. %R is calculated 5. With C filter output waveform should be noted down % , % R & is calculated. RESULT: The output waveform of Half wave rectifier, Center tapped full wave rectifier and Bridge full wave rectifier is tested and respective % , and %R is calculated.
51
EXPERIMENT NO 11 THEVENINS THEOREM & MAXIMUM POWER TRANSFER THEOREM 1. THEVENINS THEOREM:
AIM: To verify THEVENINS THEOREM using DC circuit COMPONENTS: Resistors, RPS, multimeter & milliammeter. Circuit diagram:
R1 470 R2 680 I 0-1 0 0m A A RPS V in DC
R3 1K
RL 1K VL B
Fig.1 Vin (V) 2 3 4 5 6 7 IL(mA) VL(V)
52
R1 470
R2 680
RPS Vin DC
R3 1K B
Vth
Fig2 Vin (V) 2 3 4 5 6 7

R1 470 R2 680 R2 680
Vth(V)
R3 1K B
R th
R1 // R3 320
R th
Fig 3 Rth = ( R1 // R3 ) + R2 = ( 470 // 1K ) + 680 = 1K

Rth 1K I'L 0-1 0 m 0 A A RS P Vth D C
Fig 4
Rth 1K B
V'L
Fig 5
53
Vth (V)
I'L(mA)
V'L(V)
PROCEDURE: 1. Connect the components as shown in fig. (1). Vary the DC power supply set the voltage to 2V load current IL & load voltage VL are measured & tabulated. Then vary power supply to 3V, 4V, 5V, 6V and the corresponding values of IL & VL are noted. 2. The RL is removed as in fig (2) & voltage across the terminals A & B is measured, which is the thevenins voltage (Vth).The Vth are measured for different values of input voltage & are tabulated. 3. The voltage source is removed & terminals A &B are shorted as in fig (3). The resistance of the circuit is measured across the terminals P & Q using a multimeter or by using a ohms law. The resistance in the thevinins resistance (Rth). 4. The circuit is connected as shown in the fig (4). The values of DC supply voltage are adjusted to thevenins voltage. The corresponding values of load current & load voltage are noted. The experiment is repeated for different values of thevenins voltage & the corresponding valuesm of I'L & V'L are tabulated. RESULT: It is found that VL & IL are obtained from the complex network are equal to I'L & V'L are obtained from the thevenins equivalent network. B. MAXIMUM POWER TRANSFER THEOREM: AIM: To verify maximum transfer power transfer theorem. COMPONENTS: Resistance in the range of 100 to 300, a DC power supply, multimeter, a potentiometer or a resistance box and connecting wires. CIRCUIT DIAGRAM:
54
+
RPS Vin 5V DC
I 0-100 mA
RL
EXPECTED GRAPH:
Pm ax
Pw o er in W atts
RL= R
RL inO m h s
TABULAR COLUMN: 1. When R = 1K SL No RL() I (mA) P = I2 RL (Watts)
2. When R= 470 SL no RL() I (mA) P = I2 RL(Watts)
PROCEDURE: 1. The circuit is connected as shown in the fig(1) for R=1K. And set the power supply to 5V.
55
2. The load resistance RL is varied and the corresponding values of current are noted and tabulated. Power transferred to load is calculated using the relation P= I2 RL.A plot of load resistor VS power is drawn as in figure (2) 3. The experiment is repeated for different values of R (= 470). RESULT: Maximum power is transferred when RL = R
EXPERIMENT NO 12
SERIES & PARALLEL RESONANT CIRCUIT

1. SERIES RESONANT CIRCUIT AIM: To find the resonant frequency, band width and Q-factor of the given Series Resonant circuit. COMPONENTS: ASG, DIB, DCB, Millimeter (0- 100A) A, Multimeter & connecting wires. CIRCUIT DIAGRAM:
AFG Vin 10Vpp 1KHz C1
0.47f
L 8.86 mH I 0-100 mA
Fig 1: Circuit diagram for f = 2.5 KHz FORMULAS: At resonance, XL = XC Wr L= 1/ Wr C Wr2 = 1/LC fr = 1 / 2 DESIGN: For fr =2.5KHz
LC
56
Assume C = 0.47f L = 1/ (2 fr) 2 C = 1/(2 x2.5m) 2(0.47) L = 8.86 mH EXPECTED GRAPH:

Imax 0.707Imax I in mA
f1
fr
f2
Frequency in Hz
TABULAR COLUMN: Vi = ________________V Frequency (Hz) 0.5K 1.0K 1.5K 2.0K 2.1K 2.2K . . . . 2.8K 2.9K 3.0K 3.5K 4.0K PROCEDURE: 1. The connections are made as shown in the figure. 2. The values of L, C are fixed. 3. For each frequency, current is noted and the frequency Vs current is plotted. The frequency at which current is maximum is known as the resonant frequency (fr) 4. From the graph, bandwidth is calculated 5. The same procedure is repeated to calculate the resonance frequency by varying L & C (keeping frequency and voltage constant)
I (mA)
57
RESULT: 1. fr(practical) = ____________________ Hz 2. fr(theoretical) = 1/2 (LC) = _____________Hz 3. Band width = f2 f1 = ___________________Hz 4. Q-factor = fr / (f2 f1 ) =_________________ 2. PARALLEL RESONANT CIRCUIT : AIM: To find the resonant frequency, band width and Q-factor of the given Parallel Resonant circuit. COMPONENTS: ASG, DIB, DCB, Millimeter (0- 100A) A, Multimeter & connecting wires. CIRCUIT DIAGRAM:
L 8.86 mH
AFG Vin 10Vpp 1KHz
C1
0.47f
I 0-100 mA
Fig 2: Circuit diagram for f = 2.5 KHz FORMULAE: At resonance, XL = XC Wr L= 1/ Wr C Wr2 = 1/LC fr = 1 / 2 DESIGN: For fr =2.5KHz Assume C = 0.47f L = 1/ (2 fr) 2 C = 1/(2 x2.5K) 2(0.47) = 8.86mH EXPECTED GRAPH:
LC
58
I in mA
1.414 Imin
Imin
f1 fr f2
Frequency in Hz
TABULAR COLUMN: V = ___________________ V Frequency (Hz) 0.5K 1.0K 1.5K 2.0K 2.1K 2.2K . . . . 2.8K 2.9K 3.0K 3.5K 4.0K PROCEDURE: 1. The connections are made as shown in the figure. 2. The values of L, C are fixed. 3. For each frequency, current is noted and the frequency Vs current is plotted. The frequency at which current is maximum is known as the resonant frequency (fr). 4. From the graph, bandwidth is calculated. 5. The same procedure is repeated to calculate the resonance frequency by varying L & C (keeping frequency and voltage constant). RESULT: 1. fr(practical) = ____________________ Hz 2. fr(theoretical) = 1/2 (LC) = _____________Hz 3. Band width = f2 f1 = ___________________Hz 4. Q-factor = fr / (f2 f1 ) =_________________
I (mA)
59

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Analog Electronics Circuits Laboratory Manual

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

B. FET RC COUPLED AMPLIFIER CIRCUIT DIAGRAM:

Assume & set VDD = 10V then VDS = VDD = 5/2V

Analog Electronics Circuits Laboratory Manual

FOR BJT & FET AMPLIFIERS

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

INPUT & OUTPUT WAVEFORM:

FREQUENCY RESPONSE CURVE:

b) To measure output impedance Zo:

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

DARLINGTON EMITTER FOLLOWER

Analog Electronics Circuits Laboratory Manual

CIRCUIT WITH BOOTSTRAP:

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

To measure output impedance Zo(for both with and without Bootstrap):

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

Analog Electronics Circuits Laboratory Manual

VOLTAGE SERIES FEEDBACK AMPLIFIER

Analog Electronics Circuits Laboratory Manual

Analog Electronics Circuits Laboratory Manual

1MHz EXPECTED WAVEFORM:

FREQUENCY RESPONSE CURVE:

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

b) To measure output impedance Zo:

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

RC PHASE SHIFT OSCILLATOR

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

EXPECTED WAVEFORMS: 1. Output Waveform: V0

point 3, 3 = 120 2 = tan-1 ( B/A ) 3 = 180- tan-1 ( B/A)

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

HARTLEY & COLPITTS OSCILLATORS

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

Analog Electronics Circuits Laboratory Manual

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

EXPECTED OUTPUT: Vo(V)

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual

BJT CRYSTAL OSCILLATOR

0.1f SL 100 R2 6.8K 1000 pf RE 470 CE 47f POT 1K

EXPECTED OUTPUT WAVEFORM: Vo(V) ftheo = 2 MHz f = 1/T T(Sec)

Analog Electronics Circuits Laboratory Manual

Dept of E&C, G.C.E., Ramanagaram

Analog Electronics Circuits Laboratory Manual