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3
12.3 A 150MS/s 133W 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous BinarySearch sub-ADC
the comparator decides lower than. The non-activated comparators on each layer have a high-Z output. When the comparator is reset, the outputs remain on the bitlines, so the output of the ADC is available after the quantization has finished and the comparators are reset. The die micrograph with core layout superimposed is shown in Fig. 12.3.7. The comparator array is implemented in 2 columns. The 1b MSB comparator and the LSB+5 to LSB+1 CABS comparators, in total 32 comparators, are placed in the left column. The CABS root comparator is placed at the central position, the second layer at , , and so on, to minimize the total routing of the triggering signals. In the right column, the 32 LSB CABS comparators are placed, with the bitlines of the encoder in between. The dimensions of this part are 20060m2. At the bottom the sampling switch and the clock buffers are placed (3020m2). The capacitive DAC is implemented using MOM capacitors (8025m2). The total input capacitance is 250fF (single-ended) and consists of DAC capacitance, MOS gate capacitance, and parasitic capacitance (this value is based on parasitic extraction). The total area of the ADC is 250250m2 including shift registers, without decoupling. The converter is implemented in a 1V 90nm digital CMOS using low- and regular-VT devices only. The ADC is calibrated as follows [2, 5]: for each comparator, the desired threshold is applied at the input and the digital calibration code is found with a binarysearch algorithm where the ADC output toggles 50% between the 2 codes. The capacitive DAC is calibrated similarly, by applying 2 thresholds and using a comparator to determine when the step is exactly of full scale. Both feedback capacitances Cin-DA (coarse steps) as well as Cin (fine steps) are calibrated in this way (Fig. 12.3.1). Once calibrated, the ADC is characterized for different clock frequencies. A maximum INL and DNL of 0.48 and 0.93LSB are obtained (Fig. 12.3.4) where the LSB size is 6mV. At clock frequencies up to 150MS/s, the ADC achieves 40dB SNDR over the whole Nyquist band, the ERBW is 270MHz (Fig. 12.3.5). Because of the fully dynamic implementation, the power consumption scales linearly with the sampling rate and is equal to 0.89W per MHz of clock rate. This gives a FOM of 10fJ/conversion-step. For comparison, the FOM of the ADC above 100MS/s and for 6 bits and more has been improved from 220fJ [6] to 10fJ/Conversion step. The power spectra of a full-scale low-frequency and Nyquist input signal at 150MS/s are shown in Fig. 12.3.6, the SFDR is 55.4dB for a low-frequency input and 53.9dB for a Nyquist frequency input.
Acknowledgments: The authors acknowledge the Europractice IC service of IMEC for the fabrication of the circuit, Cathleen De Tandt and Danny Frederickx for bonding, Luc Pauwels and Michael Libois for their help in assembling the PCB. References: [1] J. Craninckx and G. Van der Plas, A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS, ISSCC Dig. Tech. Papers, pp. 246-247, Feb. 2007. [2] G. Van der Plas, S. Decoutere and S. Donnay, A 0.16pF/conversion-step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process, ISSCC Dig. Tech. Papers, pp. 566-567, Feb. 2006. [3] T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, A CurrentControlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture, IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 523-527, Apr. 1993. [4] B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier, IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, Jul. 2004. [5] P. Nuzzo, F. De Bernardinis, P. Terreni, and G.Van der Plas, Efficient Calibration Through Statistical Behavioral Modeling of a High-Speed LowPower ADC, Proc. of PRIME, pp. 297-300, Jun. 2006. [6] S. Chen and R. Brodersen, A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13m CMOS, ISSCC Dig. Tech. Papers, pp. 574-575, Feb. 2006.

Geert Van der Plas1, Bob Verbruggen1,2

1

IMEC, Leuven, Belgium, 2Vrije Universiteit Brussel, Brussels, Belgium

In recent years, significant progress is made in lowering the power consumption in medium- to high-speed (10s of MS/s to a few GS/s) and medium- to low-resolution (4b to 9b) A/D converters. Current state-of-the-art FOM is 65fJ [1]. These efficiency improvements are primarily driven by mobile, wireless applications and sensor networks. In this paper, a 2-step 7b ADC consists of a T/H, followed by a 1b comparison and D/A conversion, and a 6b comparator-based asynchronous binary-search (CABS) conversion (Fig. 12.3.1). The 7b ADC operates as follows: the passive T/H samples the input signal on a capacitance, the 1b comparator determines the sign of the input (MSB, B[6]) and steers a capacitive DAC. The DAC subtracts of the full-scale range in charge from one of the input nodes, changing simultaneously differential signal and common-mode level to be in range of the 6b CABS converter. The clock buffer generates the 1b coarse A/D clock signal and starts the 6b fine conversion after the 1b D/A conversion has finished. The 6b CABS converter consists of a self-clocked (asynchronous) binary tree of comparators with embedded threshold; a conceptual block diagram is shown in Fig. 12.3.2 (2 MSBs only). The input signal is applied in parallel to all comparators as is the case with flash converters [2], but the clock is applied to the root comparator only. This comparator determines if the sampled signal is above or below 0 and outputs this on either its < (lower than) or > (greater than) pin. One of the comparators in the next layer of the binary tree is then triggered asynchronously, either the or the - scale comparator (waveforms shown in Fig. 12.3.2). An unsigned binary code is obtained by taking an OR of all > output pins of the activated comparators on each layer. For an n-bit ADC, this architecture contains 2n-1 comparators, similar to a flash ADC, but of which, only n comparators are activated during quantization, with n OR encoder functions to determine the outputs. This drastically lowers the power consumption. A clock signal starts and resets the level-triggered quantization process. Note that in contrast to standard asynchronous SAR implementations, in this architecture, a comparator is not reset immediately. Only when the whole quantization process is finished, the n activated comparators are reset from the root comparator following the same path as during quantization. This reset phase overlaps with the tracking phase of the T/H. The comparator is implemented using the dynamic latch of [3, 4] (Fig. 12.3.3). When the Comp pin is low, the comparator is reset and both outputs are low. In contrast to the implementation of [4], there is an additional NMOS device (indicated on Fig. 12.3.3) pulling down node M, to drive the PMOS input pair in accumulation. This is done to reduce the non-linearity of the input capacitance of the comparators since the input signal is sampled on this capacitance. A rising edge on Comp turns on the PMOS input pair (which contains intentional imbalance to set its threshold level [2]) and the cross-coupled regenerative latch amplifies the input signal to a full logic level. This comparator circuit is sized as small as possible, thermal noise being the limiting performance metric. To compensate for the increased mismatch, calibration capacitances are added on all internal nodes of the comparator [1, 2]. The inverter stages at both outputs have a high input threshold to avoid causing a trigger event on both outputs. They also buffer the signal to drive the next comparator in the binary tree and the encoder transistors. The OR encoder function is implemented by driving the bitline B[i] (of the ith layer) by a pull-up transistor if the comparator decides greater than, and a pull-down transistor if

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Figure 12.3.1: Architecture of the 2-step 7b ADC, 1b coarse A/D and D/A are shown in detail.

Figure 12.3.2: Comparator-based asynchronous binary-search operating principle of the 6b fine converter (2 bits shown) and waveforms.
0.5 INL [LSB]

12
0

-0.5 0 1 DNL [LSB] 0.5 0 -0.5 -1 0

16

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48

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48 64 80 Output code [-]

96

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127

Figure 12.3.3: Circuit schematic of comparator and encoder.

Figure 12.3.4: INL/DNL of ADC after calibration.

0 Power [dBFS]
Input Freq = 13 MHz Clock Freq = 150MS/s SFDR = 55.4 dB SNDR = 40.4 dB # pts. = 6000

45 SNDR [dBFS] 40 35 30 0 45 SNDR [dBFS] 40 35 30 1 10

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fin=10MHz fin=Nyquist

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fclock=150MS/s

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Input Freq = 85 MHz Clock Freq = 150MS/s SFDR = 53.9 dB SNDR = 39.7 dB # pts. = 6000

10 Signal Frequency [MHz]

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-100 0

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Figure 12.3.5: SNDR versus clock frequency for a low frequency and Nyquist input frequency at different clock rates and SNDR versus signal frequency at 150MS/s clock rate.

Figure 12.3.6: Low frequency and Nyquist power spectra at 150MS/s.

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600 m

decoupling shift reg 60 m 95 m 200um D/A T/H & Clock LSB comparators shift reg

510 m

MSBLSB+1 comparators

Figure 12.3.7: Die micrograph of 7b ADC.

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