CHAPTER - 1

INTRODUCTION

Here Write one page of intrduction about ur project

ABSTRACT
The use of a graphical LCD in embedded systems is an excellent way to present and they drastically change its look & feel. Now a days embedded system manufactures develop their products most user friendly in nature. They prefer to give the embedded product with high end features. Unfortunately graphic LCDs are real resource-hungry devices, both in terms of memory and CPU power. So the embedded-systems designer is forced to leave its lovely minimalist designs and either select an intelligent LCD display (with on-board LCD controller and memory), or swap its usual micro-controller for a more classic

microprocessor/memory/display-controller set. In this project a graphical LCD (128x64) is interfaced with the LPC21xx 32-bit microcontroller. ARM is advanced 32 bit architecture has been specifically designed to be small to reduce the power consumption, high code density and extended battery operation-essential for applications such as personal digital assistants (PDAs).We are interfacing serial communication to display the text that we are entering through key board on GLCD. We are also interfacing user switches for displaying different images on GLCD. GNU GCC/Keil U Vision 4 compiler will be used for building the applications on LPC21xx ARM7 micro controller. C coding will be developed for the applications and Flash utility is used as programmer. Graphical LCD, ARM7 LPC21xx controller , user switches are used to implement this mini project.

Block Diagram

SW 1 ARM7TDMI SW 2 BASED LPC21XX Microcontroller RS 232

GPIO

GRAPHICAL LIQUID CRYSTAL DISPLAY

SW 3

PC

CHAPTER -2

EMBEDDED SYSTEM HARDWARE

2.1 Introduction to Microcontroller: A microprocessor system consists of a microprocessor with memory, input ports and output ports connected to it externally. A microcontroller is a single chip containing a microprocessor, memory, input ports and output ports. Since all four blocks reside on the one chip, a microcontroller is much faster than a microprocessor system. We have several other basic microcontroller families such as PIC, M68HCXX, and AVR etc. All these basic microcontrollers are useful for implementing basic interfacing and control mechanisms for simple applications. There are several applications which require lot of computation and high speed data processing. In such applications advanced microcontrollers and microprocessors are used. One such advanced architecture is ARM. 2.2 History of ARM: ARM stands for Advanced RISC machine. The first processor in ARM family was developed at Acorn Computers Ltd between October 1983 and April 1985. Acorn Computers was a British computer company established in Cambridge, England, in 1978. The company worked for Reduced Instruction Set Computer (RISC) processor design. The company produced a variety of computers which were very popular in the United Kingdom. These

included the Acorn Electron, the BBC Micro and the Acorn Archimedes. Particularly BBC Micro computer dominated the UK educational computer market during the 1980s and early 1990s. 2.3 ARM Architecture: The ARM core uses RISC architecture. Its design philosophy is aimed at delivering simple but powerful instructions that execute within a single cycle at a high clock speed. The RISC philosophy concentrates on reducing the complexity of instructions performed by the hardware because it is easier to provide greater flexibility and intelligence in software rather than hardware. As, a result RISC design plays greater demands on the compiler. In contrast, the traditional complex instruction set computer (CISC) relies more on the hardware for instruction functionality, AND consequently the CISC instructions are more complicated. Certain design features have been characteristic of most RISC processors: One cycle execution time: RISC processors have a CPI (clock per instruction) of one cycle. This is due to the optimization of each instruction on the CPU. Each instruction is of a fixed length to allow the pipeline to fetch future instructions before decoding the current instruction. Pipelining: The processing of instructions is broken down into smaller units that can be executed in parallel by pipelines. Ideally the pipeline advances by one step on each cycle for maximum throughput. Instructions can be decoded in one pipeline stage. Large number of registers: The RISC design philosophy generally incorporates a larger number of registers to prevent large amount of interactions with memory. Any register can contain either data or an address. Registers act as the fast local

memory store for all data processing operation. Load-store architecture: The processor operates on data held in registers. Separate load and store instructions transfer data between the register bank and external memory. These design rules allow a RISC processor to be simpler, and thus the core can operate at higher clock frequencies.
CISC RISC

1.Complex instructions taking multiple cyclesSimple instructions taking one cycle2.Any instruction may refer to memoryOnly LOAD/STORE refer to memory3.Not pipelined or less pipelinedHighly pipelined4.Instructions interpreted by the micro-programInstructions executed by the hardware5.Variable format Fixed format instructions6.Many instructions and modesFew instructions and modes7.Complexity in the micro-programComplexity in the compiler8.Single register setMultiple register sets

Table 2.3.1: Difference between RISC and CISC architectures:

2.4 ARM Processor Core: Similar to most RISC machines ARM works on load-store architecture, so only load and store instructions perform memory operations and all other arithmetic and logical operations are only performed on processor registers. The figure shows the ARM core data flow model. In which the ARM core as functional units connected by data buses,. And the arrows represent the flow of data, the lines represent the buses, and boxes represent either an operation unit or a storage area.

The figure shows not only the flow of data but also the abstract components that make up an ARM core.

Figure 2.4.1: ARM core dataflow model

In the above figure the Data enters the processor core through the Data bus. The data may be an instruction to execute or a data item. This ARM core represents the Von Neumann implementation of the ARM data items and instructions share the same bus. In contrast, Harvard implementations of the ARM use two different buses.

The instruction decoder translates instructions before they are executed. Each instruction executed belongs to a particular instruction set. The ARM processors, like all RISC processors, use load-store architecture. This means it has two instruction types for transferring data in and out of the processor: load instructions copy data from memory to registers in the core, and conversely the store instructions copy data from registers to memory. There are no data processing instructions that directly manipulate data in memory. Thus, data processing is carried out solely in registers. Data items are placed in the register file a storage bank made up of 32-bit registers. Since the ARM core is a 32- bit processor, most instructions treat the registers as holding signed or unsigned 32-bit values. The sign extend hardware converts signed 8-bit and 16-bit numbers to 32-bit values as they are read from memory and placed in a register. The ALU (arithmetic logic unit) or MAC (multiply accumulate unit) takes the register values Rn and Rm from the A and B buses and computes a result. Data processing instructions write the result in Rd directly to the register file. Load and store instructions use the ALU to generate an address to be held in the address register and broadcast on the Address bus. One important feature of the ARM is that register Rm alternatively can be preprocessed in the barrel shifter before it enters the ALU. Together the barrel shifter and ALU can calculate a wide range of expressions and addresses. After passing through the functional units, the result in Rd is written back to the register file using the Result bus. For load and store instructions the incrementer updates the address register before the core reads or writes the next register value

from or to the next sequential memory location. The processor continues executing instructions until an exception or interrupt changes the normal execution flow.

2.4.1 ARM Bus Technology: Embedded systems use different bus technologies. The Peripheral Component Interconnect (PCI) bus connects devices such as video card and disk controllers to the X 86 processor buses. This is called External or off chip bus technology. Embedded devices use an on-chip bus that is internal to the chip and allows different peripheral devices to be inter-connected with an ARM core. There are two different types of devices connected to the bus 1. Bus Master 2. Bus Slave

Bus Master: A logical device capable of initiating a data transfer with another device across the same bus (ARM processor core is a bus Master). Bus Slave: A logical device capable only of responding to a transfer request from a bus master device (Peripherals are bus slaves) Generally a Bus has two architecture levels Physical lever: Which covers electrical characteristics a bus width (16, 32, 64 bus). Protocol level: which deals with protocol?

NOTE: - ARM is primarily a design company. It seldom implements the electrical characteristics of the bus, but it routinely specifies the bus protocol

2.4.2 AMBA (Advanced Microcontroller Bus Architecture) Bus protocol: AMBA Bus was introduced in 1996 and has been widely adopted as the On Chip bus architecture used for ARM processors. The first AMBA buses were 1. 2. ARM System Bus ( ASB ) ARM Peripheral Bus ( APB )

Later ARM introduced another bus design called the ARM High performance Bus (AHB). Using AMBA i. ii. Peripheral designers can reuse the same design on multiple projects A Peripheral can simply be bolted on the On Chip bus with out having to

redesign an interface for different processor architecture. This plug-and-play interface for hardware developers improves availability and time to market. AHB provides higher data throughput than ASB because it is based on centralized multiplexed bus scheme rather than the ASB bidirectional bus design. This change allows the AHB bus to run at widths of 64 bits and 128 bits ARM introduced two variations on the AHB bus 1. Multi-layer AHB

2.

AHB-Lite

In contrast to the original AHB , which allows a single bus master to be active on the bus at any time , the Multi-layer AHB bus allows multiple active bus masters. AHB-Lite is a subset of the AHB bus and it is limited to a single bus master. This bus was developed for designs that do not require the full features of the standard AHB bus. AHB and Multiple-layer AHB support the same protocol for master and slave but have different interconnects. The new interconnects in Multi-layer AHB are good for systems with multiple processors. They permit operations to occur in parallel and allow for higher throughput rates. 2.4.3 ARCHITECTURE Revisions: Every ARM processor implementation executes a specific instruction set architecture (ISA), although an ISA revision may have more than one processor implementation .The ISA has evolved to keep up with the demands of the embedded market. This evolution has been carefully managed by ARM, so that code written to execute on an earlier architecture revision will also execute on a later revision of the architecture. The nomenclature identifies individual processors and provides basic information about the feature set. 2.4.4 NOMENCLATURE: ARM uses the nomenclature shown below is to describe the processor implementations. The letters and numbers after the word ARM indicate the features a processor may have.

ARM { x }{ y }{ z }{ T }{ D }{ M }{ I }{ E }{J }{ F }{ -S } x family y memory management / protection unit z cache T Thumb 16 bit decoder D JTAG debug M fast multiplier I Embedded ICE macro cell E enhanced instruction (assumes TDMI) J Jazelle F vector floating-point unit S synthesizable version

All ARM cores after the ARM7TDMI include the TDMI features even

though they may not include those letters after the ARM label The processor family is a group of processor implementations that share the same hardware characteristics. For example, the ARM7TDMI, ARM740T, and ARM720T all share the same family characteristics and belong to the ARM7 family

JTAG is described by IEEE 1149.1 standard Test Access Port and boundary

scan architecture. It is a serial protocol used by ARM to send and receive debug

information between the processor core and test equipment

Embedded ICE macro cell is the debug hardware built into the processor that

allows breakpoints and watch points to be set

Synthesizable means that the processor core is supplied as source code that

can be compiled into a form easily used by EDA tools.

2.4.5 Introduction to ARM7TDMI core:

The ARM7TDMI core is a 32-bit embedded RISC processor delivered as a hard macro cell optimized to provide the best combination of performance, power and area characteristics.
2.4.6 ARM7TDMI Features:

32/16-bit RISC architecture (ARM v4T) 32-bit ARM instruction set for maximum performance and flexibility 16-bit Thumb instruction set for increased code density Unified bus interface, 32-bit data bus carries both instructions and data Three-stage pipeline 32-bit ALU Very small die size and low power consumption Fully static operation Coprocessor interface Extensive debug facilities (Embedded ICE debug unit accessible via JTAG interface

unit) 2.4.7 Benefits:

Generic layout can be ported to specific process technologies Unified memory bus simplifies SoC integration process ARM and Thumb instructions sets can be mixed with minimal overhead to support Code written for ARM7TDMI-S is binary-compatible with other members of the ARM7

application requirements for speed and code density

Family and forwards compatible with ARM9, ARM9E and ARM10 families, thus it's quite easy to port your design to higher level microcontroller or microprocessor

Static design and lower power consumption are essential for battery -powered devices Instruction set can be extended for specific requirements using coprocessors Embedded ICE-RT and optional ETM units enable extensive, real-time debug facilities

2.5 ARM Register file & modes of operation:

The ARM architecture has register file with 37 registers. In addition to these registers there will be several other registers inside the processor which will not be visible to the programmer but used by the processor internally to execute instructions. The current program status register (CPSR) has condition flags and several other control bits. When the ARM enters in privileged modes it has access to some special registers as explained below. However these are arranged into several banks, with the accessible bank being governed by the processor mode. Each mode can access a particular set of r0-r12 registers, a particular r13 (the stack pointer) and r14 (link register), r15 (the program counter), cpsr (the current program status register)and privileged modes can also access a particular spsr (saved program status register).In user mode 16 data registers and 2 status registers are visible. Depending upon context, register r13 and r14 can also be used as General Purpose Registers. In ARM state the

registers r0 to r13 are Orthogonal that means - any instruction which use r0 can as well be used with any other General Purpose Register (r1-r13) . The ARM processor has three registers assigned to a particular task or special function: r13, r14 and r15. They are frequently given different labels to differentiate them from the other registers.

Register r13 is traditionally used as the stack pointer (sp) and

stores the head of the stack in the current processor mode Register r14 is called the link register (lr) and is where the core

puts the return address whenever it calls a subroutine. Register r15 is the program counter ( pc ) and contains the

address of the next instruction to be fetched by the processor The register file contains all the registers available to a programmer. Which registers are visible to the programmer depend upon the current mode of the

processor.

Figure 2.2 Register set of LPC2148

2.5.1 ARM Modes of Operation:

ARM has total seven modes of operation. They are user , abort, fast interrupt, request, interrupt request, supervisor, system and undefined. Out of all these modes the user mode is non-privileged mode which does not have write permissions to CPSR. The other six modes are privileged modes.

Privileged: - Full read-write access to the CPSR. Under this we are having Abort, Fast interrupt request, Interrupt request, Supervisor, System and Undefined.

Abort (10111): When there is a failed attempt to access memory Fast interrupt Request (FIQ (10001)) & interrupt request (10010) : Correspond to interrupt levels available on ARM Supervisor mode (10011): State after reset and generally the mode in which OS kernel executes System mode (11111): Special version of user mode that allows full read-write access of CPSR. Undefined (11011): When processor encounters an undefined instruction Non-privileged:- Only read access to the control filed of CPSR but read-write access to the condition flags. User (10000): User mode is user for programs and applications. And this is the normal mode

The above figure shows all 37 registers of register file. Out of these 37 registers, 20 registers are hidden from a program in different modes. These are called banked registers.
2.5.2 Current program status registers:

The CPSR is a 32 bit register in addition to the 16 general purpose registers. The CPSR has flag and control bits in it. The following figure illustrates the bit positions of various control or flag bits of CPSR. The CPSR is divided into 4 fields, each of 8 bits size. They are Flag, status, extension and control fields. In the present versions of ARM the status and extensions fields bits are reserved for future use. If flag up date option is enabled1 then the flag bits will be changed as described below. Remember that flag bits are only affected when such option is chosen in the instruction; otherwise flag bits will preserve their old values. N Negative flag; this bit is set when the 31 bit (most significant bit) of result is one, otherwise it is reset Z Zero flag; this bit set if the result is zero, otherwise it is reset C carry flag; this bit is set when there is a carry out of addition and no barrow for subtraction, otherwise it is reset V overflow flag; this bit is set when there is overflow in signed arithmetic operations The I and F bits correspond to interrupt masking and the T bit tells the thumb state (whether the processor is in normal mode or thumb mode). The least significant five bits of CPSR indicate the mode in which processor is currently operating. Except in user mode in all other modes it is possible to write appropriate value in these bits for changing to any other mode. The mode also can be changed when exception or interrupt occurs. The following exceptions and interrupts results in mode change: reset, interrupt request, and fast interrupt

request, software interrupt, data abort, pre-fetch abort and execution of undefined instruction.
2.5.3 Banked registers:

Out of total 37 registers in register file at any time the processor accesses 17 registers, remaining 20 registers are called banked registers. If the processor is in user mode it accesses all R0 to R15 and CPSR register which are shown in first column in above diagram. Banked registers are available only when the processor is in a particular mode. Processor modes (other than system mode) have a set of associated banked registers that are subset of 16 register. Consider if the processor is in fast interrupt request mode then the register R8_fiq is used instead of R8 and similarly for few other registers as shown in above figure. So the original R8 register is unchanged when the processor comes back to the user mode.
2.5.4 SPSR:

The saved program status registers (SPSR) stores the previous modes CPSR when there is a mode change. When the processor returns by using special return instruction the CPSR is restored from the corresponding SPSR. Each privileged mode (except system mode) has associated with it a Save Program Status Register, or SPSR. Mode Changing: Mode changes by writing directly to CPSR or by hardware when the processor responds to exception or interrupt. To return to user mode a special return instruction is used that instructs the core to

restore the original CPSR and banked registers.

2.6 ARM Instruction Set:

Different ARM architectures revisions support different instructions. However new revisions usually add instructions and remain backwardly compatible. The following shows the type of instructions that ARM support. I. II. III. IV. V. Data Processing Instructions Branch Instructions Load-store Instructions Software Interrupt Instruction Program Status Register Instructions

CHAPTER 3

LPC2148

Microcontroller

3.1ARM7controller

Fig 3.1 Block Diagram of LPC2148 Microcontroller

The LPC2148 microcontrollers are based on a 32 bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, that combines the microcontroller with embedded high speed flash memory of 512 kB. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces the code by more than 30 % with minimal performance penalty. Due to their tiny size and low power consumption, LPC2148 microcontrollers are ideal for the applications where miniaturization is a key requirement, such as access control and point-of-sale. A blend of serial communications interfaces ranging from a USB 2.0 Full Speed device, multiple UARTS, SPI, SSP to I2Cs and on-chip SRAM of 8 kB up to 40 kB, make these devices very well suited for communication gateways and protocol converters, soft modems, voice recognition and low end imaging, providing both large buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems. 3.2 Features of LPC2148 Microcontroller : 16/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.

8 to 40 kB of on-chip static RAM and 32 to 512 kB of on-chip flash program memory. 128 bit wide interface/accelerator enables high speed 60 MHz operation.

In-System/In-Application Programming (ISP/IAP) via on-chip boot-loader software. Single flash sector or full chip erase in 400 ms and programming of 256 bytes in 1 ms.

EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the on-chip RealMonitor software and high speed tracing of instruction execution.

USB 2.0 Full Speed compliant Device Controller with 2 kB of endpoint RAM.

In addition, the LPC2146/8 provide 8 kB of on-chip RAM accessible to USB by DMA.

One or two (LPC2141/2 vs. LPC2144/6/8) 10-bit A/D converters provide a total of 6/14 analog inputs, with conversion times as low as 2.44 s per channel. Single 10-bit D/A converter provides variable analog output. Two 32-bit timers/external event counters (with four capture and four compare channels each), PWM unit (six outputs) and watchdog.

Low power real-time clock with independent power and dedicated 32 kHz clock input. Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400 kbit/s), SPI and SSP with buffering and variable data length capabilities.

Vectored interrupt controller with configurable priorities and vector addresses. Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64

package.

Up to nine edge or level sensitive external interrupt pins available. 60 MHz maximum CPU clock available from programmable on-chip PLL with settling time of 100 s.

On-chip integrated oscillator operates with an external crystal in range from 1 MHz to 30 MHz and with an external oscillator up to 50 MHz. Power saving modes include Idle and Power-down. Individual enable/disable of peripheral functions as well as peripheral clock scaling for additional power optimization. Processor wake-up from Power-down mode via external interrupt, USB, Brown-Out Detect (BOD) or Real-Time Clock (RTC). Single power supply chip with Power-On Reset (POR) and BOD circuits: CPU operating voltage range of 3.0 V to 3.6 V (3.3 V 10 %) with 5 V

tolerant I/O pads. 3.3 Description about the Block Diagram:3.3.1 On chip Flash Program Memory : -

LPC 2148 is having 512 kB Flash memory. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several
3.3.2

ways(ISP/IAP).

On chip Static RAM:-

On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed as 8-bit, 16-bit, and 32-bit. An 8 kB SRAM block intended to be utilized mainly by the USB
3.3.3 Interrupt Controller:-

The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings.

3.3.4 Analog to Digital Converter :-

LPC2148 contains two analog to digital converters(ADC0 & ADC1 ). Total number of available ADC inputs is 14. These two ADCs are 10 bit successive approximation analog to digital converters. Measurement range of 0 V to VREF. Global Start command for both converters.
3.3.5 Digital to Analog Converter :-

The DAC enables to generate a variable analog output. The maximum DAC output voltage is the VREF voltage. 10-bit DAC. Buffered output. Power-down mode available.
3.3.6 USB 2.0 Device Controller :-

The USB is a 4-wire serial bus that supports communication between a host and a number (127 max) of peripherals. Enables 12 Mbit/s data exchange with a USB host controller. A DMA controller (available only in LPC2146/48) can transfer data between an endpoint buffer and the USB RAM.
3.3.7 UART :-

LPC2148 contains two

UARTs( UART0 & UART1). In addition to

standard transmit and receive data lines, the LPC2148 UART1 also provides a full modem control handshake interface. 16 byte Receive and Transmit FIFOs. It contains Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values.

3.3.8 I2C-bus serial I/O controller :-

I2C is a bidirectional. It is a multi-master bus, it can be controlled by more than one bus master connected to it. It supports bit rates up to 400 kbit/s. Serial clock Bidirectional data transfer between masters and slaves.

synchronization allows devices with different bit rates to communicate via one

serial bus. Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer.

3.3.9 SPI serial I/O control :-

It is s a full duplex serial interface, designed to handle multiple masters and slaves connected to a given bus. Synchronous, Serial, Full Duplex Communication.
3.3.10 SSP serial I/O control :-

Supports full duplex transfers. Data frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. Synchronous serial communication. Master or slave operation. 8-frame FIFOs for both transmit and receive. Four bits to 16 bits per frame .

3.3.11 Timers :-

LPC 2148 has two 32-bit timer/counters with a programmable 32-bit prescaler. It also having external External event counter. Four 32-bit capture channels per timer/counter that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. It is also having Four 32-bit match registers that allow: Continuous operation with optional interrupt generation on match. Stop timer on match with optional interrupt generation. Reset timer on match with optional interrupt generation.

Four external outputs per timer/counter corresponding to match registers, with the following capabilities: Set LOW on match.

Set HIGH on match.

Toggle on match. Do nothing on match.

Watchdog Timer :-

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time. 3.3.13 Real Time Clock :-

The RTC is designed to provide a set of counters to measure time when normal or idle operating mode is selected. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode).
3.3.14 Crystal Oscillator :-

On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz. The oscillator output frequency is called fosc and the ARM

processor clock frequency is referred to as CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is running and connected.
3.3.15 PLL :-

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. The PLL settling time is 100 s

3.4 PIN Diagram of LPC2148

Fig 3.3 LPC2148 Pin Diagram

3.5 Special Function Register Description

3.5.1 PIN Connect Block:

The purpose of the Pin Connect Block is to configure the microcontroller pins to the desired functions. The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. The Pin connect Block contains 3 Registers to configure the functionality of port pins. They are described in below figure.

PINSEL0:

The PINSEL0 register controls the functions of the pins as per the settings listed in below block. The direction control bit in the IO0DIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically. The PINSEL0 register is used to configure P0.0 to P0.15 pins of Microcontroller. Similarly PINSEL1 is to configure P0.16 to P0.31. And PINSEL2 Register is used to configure P1.16 to P1.31 as P1.0 to P1.15 are not accessible.

Similarly Remaining Registers.

3.5.2 General Purpose Input/ Output Ports

Every physical GPIO port is accessible via either the group of registers providing an enhanced features and accelerated port access or the legacy group of registers Bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port Direction control of individual bits All I/O default to inputs after reset Backward compatibility with other earlier devices is maintained with legacy registers

 appearing at the original addresses on the VPB bus

Applications:

General purpose I/O Driving LEDs, or other indicators Controlling off-chip devices Sensing digital inputs LPC21418 has two 32-bit General Purpose I/O ports. Total of 30 input/output and a single output only pin out of 32 pins are available on PORT0. PORT1 has up to 16 pins available for GPIO functions. PORT0 and PORT1 are controlled via two groups of 4 registers shown below.
Rgeister Description

IODIR:

IOPIN

IOSET

IOCLR

3.5.3 Universal Asynchronous Receiver/Transmitter

Features:

Register locations conform to 550 industry standard. Receiver FIFO trigger points at 1, 4, 8, and 14 bytes. Built-in fractional baud rate generator with autobauding capabilities. Mechanism that enables software and hardware flow control implementation.

 16 byte Receive and Transmit FIFOs

PIN Description

UART0 contains registers organized as shown in Table 96. The Divisor Latch Access Bit (DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches.

UART0 Receiver Buffer Register (U0RBR - 0xE000 C000, when DLAB = 0, Read Only)

The U0RBR is the top byte of the UART0 Rx FIFO. The top byte of the Rx FIFO contains the oldest character received and can be read via the bus interface. The LSB (bit 0) represents the oldest received data bit. If the character received is less than 8 bits, the unused MSBs are padded with zeroes. The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the U0RBR. The U0RBR is always Read Only. Since PE, FE and BI bits correspond to the byte

sitting on the top of the RBR FIFO (i.e. the one that will be read in the next read from the RBR), the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the U0LSR register, and then to read a byte from the U0RBR.

UART0 Transmit Holding Register

The U0THR is the top byte of the UART0 TX FIFO. The top byte is the newest character in the TX FIFO and can be written via the bus interface. The LSB represents the first bit to transmit.The Divisor Latch Access Bit (DLAB) in U0LCR must be zero in order to access the U0THR. The U0THR is always Write Only.

UART0 Divisor Latch Registers

The UART0 Divisor Latch is part of the UART0 Fractional Baud Rate Generator and holds the value used to divide the clock supplied by the fractional presale in order to produce the baud rate clock, which must be 16x the desired baud rate . The U0DLL and U0DLM registers together form a 16 bit divisor where U0DLL contains the lower 8 bits of the divisor and U0DLM contains the higher 8 bits of the divisor. A 0x0000 value is treated like a 0x0001 value as division by zero is not allowed. The Divisor Latch Access Bit (DLAB) in U0LCR must be one

in order to access the UART0 Divisor Latches. Details on how to select the right value for U0DLL and U0DLM can be found later on in this chapter.

The formula to Calculate the Baud rate of the Communication is given below
PCLK(in Hz)

Desired Baud rate

= 16 x (U0DLL + U0DLM)

Below Table lists different Register values for different baud rate values

UART0 Line Control Register:

The U0LCR determines the format of the data character that is to be transmitted or received.

UART0 Line Status Register:

The U0LSR is a read-only register that provides status information on the UART0 TX and RX blocks.

CHAPTER -4

Graphical LCD

A graphic LCD is inexpensive, easy-to-control, powerful solution for the display of information to a user. It can provide both text and information from an application.JHD12864E graphic LCD with two built-in drivers (one for the left half of the display and one for the right). 128x64 LCD as having 1024 bytes of memory , every bit of which is visible. The display is split

logically in half. It contains two drivers; one controls the left half of the display, the other
control the right half. The former is selected by chip-select signal CS1, the latter by CS3. Each driver must be addressed independently. Each half consists of 8 horizontal pages which are 8 bits (1 byte) high. The page addresses, 0-7, specify one of the 8 pages. This is illustrated in Figure

4.1.

Figure 4.2: Page address of a graphic LCD

CS1 and CS2 are active-low in most LCDs. However, in some rare cases they are active-high. The designer should check the LCDs data sheet in cases of uncertainty. Chip-selected signals are active-low.

PIN ASSIGNMENT
The LCD consists of 20 pins, the functions of which are described in Table 4.3.

Table 4.2

The LCD can be reset by holding RST low for at least 100 ns. When it is reset, the display is off and the display start line register becomes 0. The content is not affected. While RST is low, no further command is executed. The LCDs backlight is controlled by pins 19(A) and 20(K) shown in

figure 4.2

DB0-DB7 are input/output pins. Their respective PSoC pins should be in High-Z mode before a read operation. Similarly, before a write operation,their respective PSoC pins should be in Strong mode. Table 5.3 shows the commands of JHD12864 graphic LCD. Y Address (0-63) The Y address counter designates the address of the internal DDRAM. An address is set by the instruction and automatically increased by 1 by read or write operations of display data. Y address 0 is the left-most byte, and Y address 63 is the right-most byte of a page. X Address (0-7) This is the page address and has no count function.

Display Start Line (0-63) The display start line register specifies the line in RAM that corresponds to the top line of the LCD panel when displaying contents

in display data RAM on the LCD panel. It is used for scrolling the screen.

Table 4.3

The power supply for the graphic LCD comes from VSS and VDD. Vee is the LCDs negative output voltage(-10V). It is used in combination with VDD to produce contrast-adjust voltage.

Chapter 5

SOFTWARE DEVOLOPMENT Using vision Keil IDE

Step 1: Give a double click on uvision 4 icon on the desk top ,it will generate a window as shown below.

Step 2: To create new project go to project select new micro vision project .

Step 3: select a drive where you would like to create your project.

Step 4: Create a new folder and name it with your project name.

Step 5: Open that project folder and give a name of your project executable file and save it.

Step 6: After saving it will show some window there you select microcontroller company i.e NXP from Phillips.

your

Step 7: Select your chip as LPC2148

Step 8:After selecting chip click on OK then it will display some window asking to add STARTUP file. Select YES .

Step 9: A target is created and startup filoe is added to your project target and is shown below.

Step 10:To write your project code select a new file from FILE menu bar.

Step 11: It will display some text editor ,to save that file select SAVE option from FILE menu bar.

Step 12: By giving a file name lwith extension .C for c files and save it.

Step 13: Write the code of your projct and save it.

Step 14: To add our c file to target give a right click on Source Group ,choose ADD files to Group option.

Step 15:It will dispay some window there select the file you have to add and click on ADD option.

Step 16: The file will be added to our target and it shows in the project window.

Step 17: Now give a right click on target in the project window and select Options for Target.

Step 18: It will shoe some window ,in that go to output option and choose Create Hex file option by selecting that box.

Step 19: In the same window go to Linker option and choose Use Memory Layout from Target Dialog by selecting the box,and click OK.

Step 20: Now to Compile your project go to Project select Build Target option or press F7.

Step 21: In the build OUT PUT window you can see the errors and warnings if there in your code.And here Your project Hex file will be created.

DUMPING THE HEX FILE TO MICROCONTROLLER USING FLASH MAGIC

Step 1-Communications Set COM Port Baud Rate Device Interface :COM1 : 19200 : LPC2148 :None(ISP)

Oscillator Freq(MHz):12 Step 2-Erase Select the box Erase all Flash + Code Rd Prot Step 3-Hex File Click on browse to load the serial.hex file from the folder serial_driver. Step 4-Options Select the box Verify after programming.

Power up the microcontroller board using USB cable, make serial cable connection between PC and microcontrollers UART0 db9 connector. To make the board enter programming mode Hold down Boot switch (isp) and Reset, then release Reset first and finally Boot. Step 5-Start Click the Start button

CHAPTER 6

Project Description

Explain about your project in one paper

CHAPTER 7

Result
Wriite one paragraph about ur result and attach the images I sent.