Design for Testability (DFT)

Design for Testability

To increase to controllability and/or observability Methodology
Reconfiguration Test point insertion Checksum Sub band Filtering IEEE standard 1149.4

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Reconfiguration

Isolation (Bypassing)
Normal Test functional block 1 Test functional block 2
Analog function
sel1

Analog function
sel2

Most used currently Switch (multiplexer) should be carefully designed

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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Reconfiguration

Loop Around
Loop around for back-to-back testing
voice
sel2

Modulator

RF

voice

Demodulator

Downconverter
sel1

RF

Example
CODEC, RF/IF Test

Switch (multiplexer) should be carefully designed Fault masking

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Reconfiguration

DfT for Switched Capacitor Filter [Soma, VTS94]

In test mode, bypass a filter stage by converting it to an all-pass gain stage

Open grounding switches and close signal path switches Operated in continuous fashion, not in sampled-data mode (bandwidth extended) C1
v2 = C2 || C4 v1
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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Reconfiguration

SW-OPAMP Type A (1/2) [Huertas, VTS96]

SW-OPAMP
With additional inputs: Test, VT

= 0: regular opamp = 1: unit buffer

VT is connected to the output of previous stage

In test mode

= 0 for stage under test = 1 for others

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Reconfiguration

SW-OPAMP Type A (2/2)

Frequency responses of original opamp and sw-opamp Gain

Phase

Carefully design for embedded switches is needed to maintain the opamp performance (offset, frequency response, SR, CMRR, )
MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Reconfiguration

SW-OPAMP Type B (1/2) [Renovell, EDTC98; J. W. Lin]

Test strategy
C=1: normal operation test C=0: reconfiguration test

Example
C1 C2 C3 =111 C1 C2 C3 =100 C1 C2 C3 =000

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Reconfiguration

SW-OPAMP Type B (2/2) [Crols, JSSC1994]

Switched-Opamp
Additional inputs: C C= 1: regular opamp C= 0: power-off opamp
C M10 M8 VDD M5 M7

V-

M1

M2

V+

Cc

Vo

M6 5uA

Loading effect due to large output drive stage

M3 VSS

M4

M9

Add switch on output to isolate the large loading

Switch in signal path should be carefully designed
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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Reconfiguration

Oscillation Test Strategy (1/2) [Kaminska, VTS96]

In test model
Partitioning CUT into functional building blocks Converting each building block to an oscillator
Shift poles on the imaginary axis Adding a feedback loop to the CUT Combine various building blocks to form an oscillator

Defects cause deviations in oscillation frequency

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

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Reconfiguration

Oscillation Test Strategy (2/2)

Example
Continuous-time state-variable filter

Excellent for hard and large deviation faults

Adopted by Fluence

Challenges
No universal rules to transfer DUT into oscillator No trivial relationship between the oscillation frequency and the specification under test
MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

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Test Point Insertion

Analog Scan -- Voltage-Based [C.L. Wey, TIM90]

DI

Voltage-based scan cell

SI

SO
+

Scan Path
PI
+ +

CUT
+

PO

SI
+

SO
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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Test Point Insertion

Analog Scan -- Current-Based [Soma, CICC95]

Current-based scan cell
I(in) Vdd

Shift In Gnd

Shift Out

Scan Path
PI V-I Converter Vdd CUT V-I Converter Vdd V-I Converter Vdd PO

SO Gnd Gnd Gnd

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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Test Point Insertion

IDDQ / IDDT Test

Insert current sensor between CUT and Vdd (Vss) Use current signature to make pass/fail decision Compare to:
DC threshold (IDDQ) [Stopjakova, 96] Expected spectrum (IDDT) [Siskos, 97]

Challenges
Resistance in Vdd Path Aliasing
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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Test Point Insertion

Output Response Compaction [Bertrand, EDTC97]

Summing or weighted-summing the internal node voltage or branch current During Testing
C=0, output is initialized to 0 C=1, performs the integration function The analog signature provided by the =RC of the integrator

Challenge -- Aliasing
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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Checksum

Analog Checksum (1/3) [Chatterjee, D&T96]

For Linear circuit (system)
X (t + t ) = AX (t ) + Bu (t ) y (t ) = CX (t ) + Du (t ) u(t) : input, y(t) : output, x(t ) : state variable
x1 (t + t ) a11 a12 x1 (t ) b1 u (t ) + x (t + t ) = a a22 x2 (t ) b2 2 21 x1 (t + t ) a11 x1 (t ) + a12 x2 (t ) + b1u (t ) x (t + t ) = a x (t ) + a x (t ) + b u (t ) 22 2 2 21 1 2

X(t) : state vector

X (t + t ) = AX (t ) + Bu (t )

x1 (t + t ) + x2 (t + t ) = a11 x1 (t ) + a12 x2 (t ) + a21 x1 (t ) + a22 x2 (t ) + b1u (t ) + b2u (t ) = (a11 + a21 )x1 (t ) + (a12 + a22 )x2 (t ) + (b1 + b2 )u (t )
a12 + a22 x1 (t ) u 0] x2 (t ) + [b1 + b2 ]u (t ) b1+b2 x3 (t )

Let

[x3 (t + t )] = [a11 + a21

x1

x2
-1 -1

y
a12+a22

x3 (t + t ) = x1 (t + t ) + x2 (t + t )

a11+a21

1/s

x3
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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Checksum

Analog Checksum (2/3)

Fourth order band pass leapfrog filter Checksum circuit

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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Checksum

Analog Checksum (3/3)

Fault free response Faulty response

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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Sub-Band Filtering

Sub-Band Filtering (1/3) [Abraham, ITC99]

Motivation
Reducing the aliasing probability of the integrator scheme by analyzing the signature for each frequency band

Signature Analysis Scheme

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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Sub-Band Filtering

Sub-Band Filtering (2/3)

Low-pass filtering and down-sampling

Filtering Example

20

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Sub-Band Filtering

Sub-Band Filtering (3/3)

Recursive Architecture of Filter Bank
Sub-Band Filtering Wavelet

Pros -- More immune from fault aliasing problems Cons -- Requires on-chip ADC
21

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

IEEE Standard 1149.1

Digital boundary cells Digital pins Digital circuit

Digital boundary scan path

TDI TMS

TAP controller

TDO TCK
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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Test Board with Mixed-Signal Parts

The introduction of analog components to 1149.1 compliant The introduction of analog components to 1149.1 compliant chip, the ability to isolate faulty interconnects on the analog chip, the ability to isolate faulty interconnects on the analog I/O pins does not exist!! I/O pins does not exist!!
MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

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1149.4 -- Mission Statement

To define, document, and promote the use of a standard mixed-signal test bus that can be used at the device, sub-assembly, and system levels to improve the controllability and observability of mixed-signal designs and to support mixed-signal built-in test structures in order to reduce test development time and costs, and improve test quality.
24

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Structure of a Basic 1149.4 Chip

Digital Boundary Module (DBM)

VH VL VG

Analog Boundary Module (ABM)

Core

Analog I/O Pins

Internal Analog Bus (AB1, AB2 ) Analog Test Stimulus Bus (AT1, AT2)
AT1 AT2 TDO TCK

Digital I/O Pins

Circuit

VH VL VG

Boundary Scan Path

TBIC (Test Bus Interface Circuit)

Analog Test Access Port (ATAP = AT1 + AT2) Digital Test Access Port (TAP ) as in IEEE1149.1
25

Digital Test Access Port (TAP) as in IEEE1149.1

TDI TMS

Test Control Circuitry

TAP Controller Instruction register and decoder

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Analog Boundary Module (ABM)

TDO Vdd

VTH
CD

F/F F/F F/F

Analog core

Mode control from TAP AB1 AB2

F/F TDI GND

Input value can be sensed, digitized (against VTH), and captured in the register Ability to disconnect the receiving core from the pin using CD and drive either a 1 or a 0 ABMs can be implemented with actual switches or can be integral in the analog circuit
26

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Test Bus Interface Circuit (TBIC)

VH and VL allow fixed 1 and 0 values (for EXTEST) using S1, S2, S3, S4 ATn disconnected from ABn via S5, S8 Noise suppression via S9, S10, Vclamp when ABn not inAT1 AT2 use
AB1 AB2

S1

VH

S2

Vclamp S9 S10

S3

VL

S4 S5 S8 S7 S6

+ -

VTH

- +

Provision for interconnect test

Bus connection and calibration

27

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

DfT Strategies Have Potential to

Reduce redundancy Reduce probabilities of undetectable faults at the layout level Improve test access (controllability and observability) Reduce demands on production test equipment Increase resolution of parameter measurement Provide support for on-line monitoring and diagnostics
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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

DfT Principle 1: Precision

Definition
Measurement sample deviation relative to measurement mean, e.g. standard deviation (MEAS) of a set of measurements

Sources of imprecision: various noise

Signal: Other signal: Test/DfT cct: Quantization: Misc: thermal or shot noise of source impedance capacitive coupling or via power rail power supply, coupling, buffers, algorithm in converter under test, or ADC of tester transmission line reflections at I/O pins

Basic technique to increase precision: integration

The more samples averaged, the better

Example
Histogram
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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

[S. Sunter, ITC tutorial #15, 1999]

DfT Principle 2: Accuracy

Definition
Measurement mean relative to true mean
e.g. average measurement error 100% * (MEAS - 0) / 0

Cause of inaccuracy: systematic errors

Wrong gain Offset voltage Capacitive coupling

To increase accuracy: substraction

e.g. measure with/without stimulus, inverted/non-inverted, doublecorrelated sampling

Example
Differential signals, IEEE1149.4 metrology
30

MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

[S. Sunter, ITC tutorial #15, 1999]

DfT Principle 3: Conversion to Digital (without an ADC)

Definition
Converting a continuous variable into a binary-coded digital value

Why not use an ADC

Area, design automation Technology and process-dependence, diagnosability How to test the ADC

Example
e.g. convert a delay into an oscillation whose frequency is counted e.g. compare Vin to voltage from RC, and measure delay

Known Delay

Vin Unknown Delay Frequency Counter Fref

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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

General DfT Guidelines

Incorporate DfT features at a early design stage Partition the circuit in simple and ease to treat macro blocks Use digital test access port to select test mode Separate analog and digital circuits Consider the limitation (speed, accuracy, memory, ) of ATE If possible, incorporate digital circuit rather than analog one when using DfT techniques
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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

Reference (1/2)
1.

2.

3.

4.

5.

6.

7.

8.

M. Soma & V. Kolarik A Design-for-Test Technique for Switched-Capacitors Filters,, IEEE European Design & Test Conference, pp.42-47, Paris, March 1994 D. Vazquez, J. L. Huertas, A. Rueda, Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design, VLSI Test Symposium, pp.42-47, 1996 M. Renovell, F. Azais, Y. Bertrand, Optimized implementations of the multi-configuration DFT technique for analog circuits, Design, Automation and Test in Europe, pp.815-821, 1998 J. Crols, M. Steyaert, Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages, IEEE Journal of Solid-State Circuits, vol.29 Issue 8, pp.936-942, Aug. 1994 K. Arabi, B. Kaminska, Oscillation-Test Strategy for Analog and Mixed-Signal Integrated Circuits, VLSI Test Symposium, pp.476-482, 1996 K. Arabi, B. Kaminska, Testing Analog and Mixed-Signal Integrated Circuits Using Oscillation-Test Method, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.16, Issue 7, pp.745-753, July 1997 C. L. Wey, Built-in self-test (BIST) structure for analog circuit fault diagnosis, IEEE Transactions on Instrumentation and Measurement, vol.39, Issue 3, pp.517-521, June 1990 M. Soma, Structure and concepts for current-based analog scan, IEEE Custom Integrated Circuits Conference, pp.517-520, 1995
MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12

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Reference (2/2)
9.

10.

11.

12.

13.

14.

M. Sidiropulos, V. Stopjakova, H. Manhaeve, Implementation of a BIC monitor in a new analog BIST structure, IEEE International Workshop on IDDQ Testing, pp.59-63, 1996 S. Siskos, A. A. Hatzopoulos, A simple built-in current sensor for current monitoring in mixed-signal circuits, IEEE Transactions on Instrumentation and Measurement, vol.46, Issue 6, pp.1301-1304, Dec. 1997 M. Renovell, F. Azais, Y. Bertrand, On-chip analog output response compaction, European Design and Test Conference, pp.568-572, 1997 A. Chatterjee, B. C. Kim, N. Nagi, DC built-in self-test for linear analog circuits, IEEE Design & Test of Computers, vol.13, Issue 2, pp.26-33, Summer 1996 J. Roh, J. A. Abraham, Subband filtering scheme for analog and mixed-signal circuit testing, International Test Conference, pp.221-229, 1999 http://grouper.ieee.org/groups/1149/4/index.html

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MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin 2009/5/12