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RAJAGIRI SCHOOL OF ENGINEERING AND TECHNOLOGY RAJAGIRI VALLEY, KAKKANAD. Third Semester Digital Electronics Question Bank 1.

Determine the decimal equivalent of the binary number 101011


1 1 0 1 0 1 x 1 x 2 x 4 x 8 x 16 x 32 Total = 1 = 2 = 0 = 8 = 0 = 32 = 43

Therefore the decimal equivalent of 101011 is 43. 2. Convert the number 25510 and 80110 to binary coded decimal (BCD) notation and perform BCD addition, leaving the answer in BCD notation. 25510 0010 0101 0101BCD 80110 1000 0000 0001BCD 1010 0101 0110BCD 1010 0101 0110BCD + 0110 0000 0000
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= 0001 0000 0101 0110BCD (Ans) 3. Write the number -.062510 in floating point format, with a 10-bit mantissa and a 6-bit exponent, both using 2's complement representation.
-.062510 = -.0001 2 = -.1 * 2-3 = 1 100000000 * 1 11101

4. Convert -23 into a 7-bit


signed magnitude number 1's complement number 2's complement number 1010111 1101000 1101001

Ans:

5. Convert (101.11)2 to an octal number to a hexadecimal number. 1

Ans: (5.6)8, (5.C)16 6.

The function in the above circuit is a) abcd b) ab+cd c) (a+b)(c+d) d) (a+b)(c+d) 7. For the function defined by the truth table given A B C F 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1

The canonical form of F' in SOP form. The canonical form of F' in POS form. SOP: A'B'C' + A'B'C + AB'C' + AB'C POS: (A+B'+C ) (A+B'+C' )(A'+B'+C ) (A'+B'+C')wrong!!!!!!!

Ans:

8. Convert the following functions to the other canonical form: 2

F(A,B,C) = (1,3,7) F(A,B,C,D) = (0,1,2,3,4,6,12) Ans: (0,2,4,5,6) ( (5,7,8,9,10,11,13,14,15)

9. Prove Ans: note:there is an alternate method(by distributive prop)

10. Give the relationship that represents the dual of the Boolean property A + 1 = 1? (Note: * = AND, + = OR and ' = NOT) a) A * 1 = 1 b) A * 0 = 0 c) A + 0 = 0 d) A * A = A e) A * 1 = 1 11. Give the best definition of a literal? a) A Boolean variable b) The complement of a Boolean variable c) 1 or 2 d) A Boolean variable interpreted literally e) The actual understanding of a Boolean variable 12. The examples AB = BA and A+B = B+A represent which of the following Boolean laws? a) Associative b) Commutative c) Intersection d) Union 13. What is the output of an exclusive NOR gate when (a) all inputs are LOW and (b) all inputs are HIGH? a) (a) HIGH (b) HIGH b) (a) LOW (b) HIGH c) (a) HIGH (b) LOW d) (a) LOW (b) LOW 14. Simplify the Boolean expression (A+B+C)(D+E)' + (A+B+C)(D+E) and choose 3

the best answer. a) A + B + C b) D + E c) A'B'C' d) D'E' e) None of the above 15. Which of the following relationships represents the dual of the Boolean property x + x'y = x + y? a) x'(x + y') = x'y' b) x(x'y) = xy c) x*x' + y = xy d) x'(xy') = x'y' e) x(x' + y) = xy 16. Given the function F(X,Y,Z) = XZ + Z(X'+ XY), the equivalent most simplified Boolean representation for F is: a) Z + YZ b) Z + XYZ c) XZ d) X + YZ e) None of the above 17. Which of the following Boolean functions is algebraically complete? a) F = xy b) F = x + y c) F = x' d) F = xy + yz e) F = x + y' 18. Simplification of the Boolean expression (A + B)'(C + D + E)' + (A + B)' yields which of the following results? a) A + B b) A'B' c) C + D + E d) C'D'E' e) A'B'C'D'E' 19. Given, that F = A'B'+ C'+ D'+ E', which of the following represent the only correct expression for F'? a) F'= A+B+C+D+E b) F'= ABCDE c) F'= (A+B)CDE d) F'= AB+C'+D'+E' 4

20. An equivalent representation for the Boolean expression A' + 1 is a) A b) A' c) 1 d) 0 21. Simplification of the Boolean expression AB + ABC + ABCD + ABCDE + ABCDEF yields which of the following results? a) ABCDEF b) AB c) AB + CD + EF d) A + B + C + D + E + F e) A + B(C+D(E+F)) 22. Which gate is the following circuit equivalent to?

a) b) c) d) e)

AND Gate NOT gate OR gate NOR gate NAND gate

23. Flip-flop is a typical Synchronous Astable Device. a) True b) False 24. A sequential circuit is a digital circuit whose logic states depend on a specified time sequence. a) True b) False 25. A synchronous sequential circuit changes its states at discrete instants of time. a) True b) False 26. A transition of a clock from 0 to 1 is called a) Falling Edge b) Raising edge c) Edge trigger 27. A JK flip-flop is presently in the RESET state and must go to the SET state on the next clock pulse. J must be 1 and K must be X (don't care). a) Trueb) False

28. For a D flip-flop, the next state is always equal to the D input. a) Trueb) False 29. A D filp-flop is connected as shown below. Assume it has initially been reset. After 8 clock pulses, the Q output is high.

a) True

b) False

30. The most important advantage of synchronous counters over asynchronous counters is that there is no cumulative time delay. a) True b)False 31. Serial in - parallel out shift register can be used as a serial in - serial out shift register, simply by getting the serial output from the right-most (LSB) flip-flop. a) True b) False 32.

Assume the circuit above has initially been reset. X is high and Y is low. After one clock pulse, Q becomes: a) High b) Low c) Can not be determined.

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The above circuit is a construction of: a) S R flip flop b) J K flip flop c) D flip flop d) None of the above 34.

In the timing diagram above, A and B are the flip-flop's inputs, Qs are the outputs, and C is the clock input. It could be a timing diagram of: a) a positive edge-triggered S-R flip-flop b) a positive edge-triggered J-K flip-flop. c) a negative edge-triggered S-R flip-flop. d) a negative edge-triggered J-K flip-flop. e)Both a & b 35. A three-bit up-down binary counter is in the down mode and in the 000 state. After 3 clock pulses, to what state does the counter go? a) 010 b) 011 c) 111 d) 110 e) 101 36. How many states does a modulus-12 counter have? a) 24 7

b) 12 c) 8 d) 6 37. The output of an 8-bit serial in - serial out shift register is connected back to its input. Assume the initial content of the shift register is 11000011. After 4 clock pulses, the content becomes: a) 11000011 b) 00001100 c) 00111100 d) 00001111 e) 11110000 38. How many clock pulses are needed to shift a byte of data into and out of an eight-bit serial in - serial out shift register? a) 4 b) 8 c) 12 d) 16 e) None of the Above 39. The initial content of a 4-bit bidirectional shift register is 0011. The serial input contains 1100. After applying two clock pulses when the control line is set to shift-left mode, and then two clock pulses when the control line is set to shift-right mode, the content of the register becomes: a) 0011 b) 1100 c) 1111 d) 0000 e) 1001 40. How many flip-flops are needed to build a divide-by-12 Johnson counter? a) 24 b) 12 c) 10 d) 8 e) 6

PART B 41. Solve the arithmetic (0110BCD+ 1108 +11016) / 1002 using binary and give the final answer in decimal. 0110BCD = 610 = 0 1102 01108 = 001 001 0002 001 001 1102 = 0000 0000 0100 1110 + 011016 = 0000 0001 0001 0000 0000 0001 0101 1110 /10002 = 101011.1102 = 32+8+2+1 + 0.50+ 0.25 = 43.7510 42. Perform the following addition: 3458 + 1738 Show all working in octal; do not convert to a different base. Express the answer in hexadecimal also. Ans: 3458 + 1738 = 3 4 5 1 7 3 5 4 08 = 101 100 000 = 1 0110 0000 =16016 43. Express the decimal number -0.187510 in the floating point format M(6) E(4), with both mantissa and exponent in 2's complement.
0.1875 = 0.0011 2 = 0.11000 * 2-2 -0.1875 = 101000 * 2-2 101000 1110 mantissa exponent

44. Perform the following addition : 1000 1001BCD + 0111 11012 Convert the answer into hexadecimal representation. 1000 1001BCD = 8910 = 10110012

= D616 45. Calculate the value of the following expression: [4] 8 * (10114 + F516) = 9

_________________ in binary notation.

where * denotes multiplication. Give your answer

46. Show how the decimal number -36.062510 can be represented in floating point format with a 12-bit mantissa and a 4-bit exponent, both using 2's complement representation.

47. Convert the number 25510 and 80110 to binary coded decimal (BCD) notation and perform BCD addition, leaving the answer in BCD notation. 25510 0010 0101 0101BCD 80110 1000 0000 0001BCD
_______________________

1010 0101 0110BCD 1010 0101 0110BCD + 0110 0000 0000


_______________________-___________________________

= 0001 0000 0101 0110BCD 48. Calculate the value of the expression (11012 + 24 8 + F1416 ) x 410 and give the result in binary. (11012 + 24 8 + F1416 ) x 410 =(1101+ 010 100 + 1111 0001 0100)2 * 1002 = 1111 0011 01012 * 1002 = 11 1100 1101 01002 49. Explain how to convert a multi-digit decimal number into binary-coded decimal and back again, and how to add two multi-digit BCD numbers. To convert from decimal to BCD, convert each decimal digit to a 4-bit binary value, and concatenate these binary sequences. To convert back again, reverse this process (split the binary sequence into 4-bit chunks, convert each to a decimal digit, and concatenate the digits). To add in BCD, add in 4-bit chunks from the least significant end; and partial sum over 9 results in a carry to the next chunk.

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50. Add together the different number systems, ( 348 + E0416 ) and give the answer in BCD.
(

348 + E0416) = 01 1100 1110 0000 0100 1110 0010 0000 1110 0010 00002 = E3816 = 14x256 +2x16 = 3584 + 32 = 361610 = 0011 0110 0001 0110BCD

51. 11112 + 234 + B9416) 6 10=? 1 = (1111 + 1011 + 1011 1001 0100)2 100002 = 1011 1010 11102 100002 = 1011 1010.11102 = 272.78 52. Simplify the following Boolean expression: (X + Y)(X + Y')(X' + Z). (X + Y)(X + Y')(X' + Z) (X + (Y*Y')) * (X' + Z) (X + (0)) * (X' + Z) (X) * (X' + Z) (X*X' + X*Z) (0 + X*Z) X*Z

Distributive Complement Element Identitity Element Distributive Complement Element Identitity Element

53. Derive a simplified POS (product of sums) expression from the following K map:

ANS: F= B+C

54. Simplify the expression 11

55. Using the laws of boolean algebra, transform the expression into a sum of products in the simplest form possible.

56. Simplify the following Boolean expression: (X + Y)(X + Y')(X' + Z). (X + Y)(X + Y')(X' + Z) (X + (Y*Y')) * (X' + Z) (X + (0)) * (X' + Z) (X) * (X' + Z) (X*X' + X*Z) (0 + X*Z) X*Z

Distributive Complement Element Identitity Element Distributive Complement Element Identitity Element

57. Express the following function as a sum of minterms and product of maxterms: (XY + Z)(XZ + Y). Sum of minterms: X'YZ +

XY'Z + XYZ' + XYZ Product of maxterms: XYZ * XYZ' * XY'Z * X'YZ 58. Simplify using Boolean Algebra F(A,B,C,D) = ABD + (A+C+D) + AB + ACD + ABD Ans:= ABD + ACD + AB + ACD + ABD = ABD + AB + AD(C+C) + ABD = ABD + AB + AD+ ABD 12

= B(A+AD) + D(A+AB) = B(A+D) + D(A+B) = AB + BD + AD + BD 59. Simplify the following expression using Boolean Algebra, and identify the laws used: F(A,B,C,D) = AB + (A+B+D) + ABD + AD Ans: F(A,B,C,D) = AB + (A+B+D) + ABC + AD = AB(1+C) + ABD + AD De Morgans law / = AB + A(BD+D) Dominance law = AB + A(B + D) Redundancy law = AB + AB + AD 60. Draw the logic diagram for the expression using XOR and NAND logic gates ONLY F(A,B,C,D) = AB + A B + CD =((AB +AB) + CD)) A B C = ((AB + AB)(CD) ) D

61. Construct a Truth Table for the segment of a program. IF sensor A AND sensor B THEN Alarm Sound ELSE IF sensor B AND sensor C THEN Alarm does not Sound ELSE IF sensor A OR NOT sensor C THEN Alarm Sound ELSE Alarm do not sound

C B A Alarm Sound /not sound

0 0 0 1

1 0 0 0

0 1 0 1

1 1 0 0

0 0 1 1

1 0 1 1

0 1 1 1

1 1 1 1 13

62. The following diagram shows an automobile alarm circuit that is used to detect certain undesirable conditions. The three switches are used to monitor the status of one of the doors, the ignition system, and the headlights.

Design a logic circuit that takes these three switches as inputs and activates the alarm when, and only when, either of the following conditions exists: the headlights are on and the ignition is off the door is open and the ignition is on Your answer should consist of: (i) a truth table (ii) a complete K-map (iii) a simplified SOP expression (iv) the logic diagram itself.

minterm D I L A 0 1 2 3 4 5 6 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0

A= DI+IL

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63. What is the difference between a variable, a literal and a term? ANS: A variable is a symbol that may take on the value 0 or 1. A literal is the use of a variable or its complement in an expression. A term is the expression formed by literals and operations at one level. For example, the following function: F1=xy+xy'z+x'yz Has 3 variables (x,y,z), 8 literals (x,y,x,y',z,x',y,z), and 4 terms (xy, xy'z, x'yz, and the OR term that combines the first level AND terms). 64. Express the function L in terms of A,B,C,D
L C B voltage supply D bulb

ANS: L = (A+B)( C) (D is redundant)

65. Given the truth table below, get the logic circuit.
INPUTS A 0 0 0 0 0 1 1 1
C B

OUTPUT C 0 1 0 1 0 1 0 1
A

B 0 0 1 1 0 0 1 1

X 0 0 0 1 0 1 1 0

A ABC

ABC

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ABC

66. Implement f= AB+CD usinf NAND gates only


A B C D G3 CD G2 AB G1 X = AB + CD

67. Implement the function using NOR gates only ((A+B)C+D)(E+F)


A B C D E F E+F A+B A+B+C A+B+C+D A+B+C+D+E+F

68. Use the Quine-McCluskey method to determine the prime implicants in the
expression m2, m3, m6, m8, m15

69. Express the following circuit symbolically.

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Redraw the circuit using a single gate, and express the new circuit symbolically too. The circuit implements the expression . It is equivalent to the circuit, which implements the expression Y = A + B + C

70. Find a minimal product-of-sums expression for the function


F (A, B, C, D) = (2, 4, 5, 6, 7, 10, 12, 13, 14, 15)

so the minimal product-of-sums expression is B(C + D). 71. Express the expression using NAND gates only

72. Implement the following expression F= A'BC (A+D)' 17

Ans:

73. Subtract 19 (00010011) from 28 (00011100) by using two's complement. Complementing 19 11101100 add 1 + 1 -------2's complement of 19 11101101 This result must be added to 28 to obtain our result. 28 00011100 + -19 11101101 +9 100001001(discard the carry) 74. Simplify the expression F (A, B, C, D) = (2, 4, 5, 6, 7, 10, 12, 13, 14, 15) using K- map.

so the minimal product-of-sums expression is B(C + D). 75. Explain, with the aid of a diagram, how we can use full adders to perform 2's complement arithmetic. How many full adders are required if the result is in the range 31 to 32?

The carry out of one adder is connected to the carry in of the next. The two numbers to be added are input bit-wise across the array of adders. The first carry in is set to 18

zero. Five full adders will be required if the result is to be in the range -31 to 32. 76. Show how a NAND gate can be implemented using only multiplexers. Draw a block diagram to illustrate your answer, labelling all of the inputs and outputs clearly.

77. Design a 4-input priority encoder for the inputs and outputs shown in the table below.

Draw the k-map for A1 & A0

Logic diagram: 19

78. Draw a diagram to show how a half-adder can be constructed using a decoder and an OR gate. Label all inputs and outputs.

79. Show how a 4x1 multiplexer can be used to implement the following logical function:

80. Draw a diagram to show that a 2 to 1 MUX can be made to behave as a single NOT 20

gate. Label the inputs and output appropriately.

81. Draw a diagram to show how a 2 to 1 MUX can be used to turn two 4 to 1 MUXs into a single 8 to 1 MUX. Label all the connections and inputs.

82. Draw a diagram to show how a 2 to 4 decoder and an OR gate can be used together to implement a half-adder.

83. Show how two half-adders can be connected to produce a full-adder.

84. Draw diagram showing how to implement a 4 to 2 encoder using two OR gates. 21

85. Draw a diagram showing how to make 1 to 8 demultiplexor act like a 3 to 8 decoder, without using any extra gates. Label the inputs to the decoder A0 to A2 , and the outputs B0 to B7.

86. Implement the function f(W,X,Y,Z) = (0,1,3,4,8,9,15)

using an 8 to 1 multiplexor and other logic gates as necessary. Use W as an input to the multiplexor and X,Y,Z as selectors.

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87. Show how to implement a full-adder using two 4-to-1 multiplexors.

88. Draw a diagram to show how a half-adder can be implemented using an AND-gate and XOR-gate (exclusive or).

89. Show how two full-adders can be connected to produce a 2-bit parallel adder.

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90. Consider the circuit below:

Show how X can be written as a function of inputs A and B, without simplification. Using laws of Boolean algebra, show how this function for X can be simplified as far as possible. Draw a circuit to implement the function with the minimum number of gates. X = . (A + B) + . (A + B)
= = = = = = .A 0+ .B .B .B .B . (A + B) + . (A + B) + . B + . (A + B) . B + . (A + B) + . (A + B) + .A+ .B + .A +0 + .A [distribution] [complementation] [dominance] [distribution] [complementation] [dominance]

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91. The truth table below shows how output Y should be determined by four inputs A, B, C, and D. An x in the Y column indicates a don't care condition: the value of Y is not important for the current combination of inputs.

92. Draw and label a circuit diagram to show how two 4-bit parallel adders can be connected to produce a BCD adder. You may use and or or gates if necessary. The BCD adder should have two BCD inputs inputs B3B2B1B0 and A3A2A1A0 and a single BCD output T3T2T1T0.

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93. Show how to implement exclusive-or and exclusive-nor (that is, equality) using just two 2 x 1 mulitplexors each. Exclusive OR

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Exclusive NOR

94. Show how to construct a 3 8 decoder, using two 2 4 decoders and other suitable gates

95. Convert F(A,B,C,D) = (0,1,3,5,9,11,13,15) into the minterm form and Implement the function with a multiplexer and other necessary logic gates. Show the implementation table using A as input and B,C,D as the selectors.

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96. Exactly how many 2-to-1 MUXes are necessary to realize an 8-to-1 MUX? Draw a Schematic of the 8-to-1 MUX realized in terms of 2-to-1 MUXes.

97. Simplify the expression F(A, B, C, D) = (4, 8, 9, 10, 11, 12, 14, 15)

F= AC+AB+BCD 28

98. Explain how a sequential logic circuit is different from a combinational logic circuit. Ans: The output values of a combinational logic circuit are computed directly from the current input values. Combinational circuit, the output at any instant of time are entirely dependent upon the inputs present at that time. Output values of a sequential logic circuit are based on the sequence of input values received. In other words sequential circuits exhibit memory of past input values. Sequential circuits don't necessarily "remember" the exact values of past inputs, instead they move through a series of states. Sequential circuits move from one state to another based on the current state and current input value. Sequential circuit consist of combinational circuit to which memory elements are connected to form a feedback path (OR: in a sequential circuit, the output at any instant depends also on the history of the circuit). Timing is important with sequential circuits because the circuit can move from one state to another based on its current state and current input. There are two types of sequential circuits with respect to the timing of changes: synchronous and asynchronous. With synchronous sequential circuits a clock is used to control the timing of changes between states. With asynchronous sequential circuits the state of the circuit changes as soon as new inputs arrive. Memory in sequential circuits is implemented with feedback paths. 99. Consider the following figure

`
Complete the waveform for output Q, as input A varies as shown over four clock cycles:

Ans:

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100. Consider the following sequential circuit:

Draw the output wave form for the following input

Out put wave form:

101. Show how an edge-triggered SR flip-flop can be implemented using NAND gates:

102. Show how an edge-triggered T flip-flop can be implemented using NAND gates.

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103. Show how a combination of edge-triggered T flip-flops can be used to construct a synchronous binary counter that counts up: 0000, 0001, ..., 1110, 1111, 0000, ...

104. Give the characteristic table for a clocked JK flip-flop, and draw a diagram showing how to convert an edge-triggered JK flip-flop into an edge-triggered T flip-flop.
Characteristics table for JK flip-flop Qt 0 0 0 0 1 1 1 1 J 0 0 1 1 0 0 1 1 K 0 1 0 1 0 1 0 1 Qt + 1 0 0 1 1 1 0 1 0

JK flip-flop to T flip-flop conversion

105. Draw a diagram showing how to construct an edge-triggered SR flip-flop from AND gates, NAND gates and inverters.

106. Draw a diagram showing how to turn an edge-triggered SR flip-flop into an edge-triggered D 31

flip-flop.

107. Distinguish between synchronous and asynchronous counters. In a synchronous counter, all the flip-flops are connected to a single clock. In an asynchronous counter, each flip-flop is triggered by the previous one. 108. Design a 3-bit synchronous up counter, using T flip-flops.

109. Design a 3-bit asynchronous up counter, using T flip-flops.

110. Show how to construct an edge-triggered D flip-flop from an edge-triggered SR flipflop.D flip-flop from SR flip-flop.

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111. Show how to construct an edge-triggered D flip-flop from ordinary logic gates (NOT, AND, OR, NAND, NOR).

112. Show how to connect three edge-triggered D flip-flops into a 3-bit ring counter, in which exactly one output is high at any one time.

113. Design a sequential circuit whose state tables are specified in Table, using D flipflops. Present State Q0 Q1 00 01 10 11 x=0 x=1 Next State 00 00 11 00 01 10 10 01 Output x=0 x=1 0 0 0 0 0 0 0 1

Excitation table for a D flip-flop.


Output Transitions QQ(next) 0 0 0 1 1 0 1 1 Flip-flop inputs D 0 1 0 1

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Next step is to derive the excitation table for the design circuit, which is shown in Table, The output of the circuit is labelled Z. Present State Q0 Q1 00 00 01 01 10 10 11 11 Next State Q0 Q1 00 01 00 10 11 10 00 01 Input x 0 1 0 1 0 1 0 1 Flip-flop Output Inputs Z D0 D1 0 0 0 1 1 1 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1

Simplified expression: D0 = Q0.Q1' + Q0'.Q1.x D1 = Q0'.Q1'.x + Q0.Q1.x + Q0.Q1'.x' Z = Q0.Q1.x

114. Draw a circuit showing how to configure, using additional logic gates, a serialin/ 34

serial-out shift register as: i) shift-right register ii) shift-left register i)

ii)

CLK 115. Use JK flipflops to design a 3-bit synchronous up/down counter that starts at 001 and cycles through Prime numbers only ( i.e. numbers divisible by only themselves or 1 ).Assume that M=0 counts down, M=1 counts up.

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