CPLD Development/Programmer Kit

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Table of Contents

Section 1 Introduction ........................................................................................... 1-1

1.1 1.3 CPLD Development/Programmer Kit ........................................................1-1 Kit Features...............................................................................................1-2 CPLD Development/Programmer Board ............................................1-2 Logic Doubling CPLDs .......................................................................1-2 CPLD ISP Download Cable ................................................................1-2 PLD Software CD-ROM......................................................................1-2 Atmel CD-ROM Data Books ...............................................................1-3

1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.4 1.5 1.7

Device Support .........................................................................................1-3 System Requirements...............................................................................1-3 Technical Support .....................................................................................1-4 ProChip Designer ...............................................................................1-5 Atmel-WinCUPL .................................................................................1-5 ATMISP ..............................................................................................1-5 POF2JED ...........................................................................................1-5

1.8.1 1.8.2 1.8.3 1.8.4

Section 2 Hardware Description ........................................................................... 2-1

2.1 Atmel CPLD Development/Programmer Board.........................................2-1 8-segment Display LEDs ....................................................................2-2 Push-button Switches.........................................................................2-6 Clock Select Jumper...........................................................................2-6 VCC Select Jumper ............................................................................2-7 JTAG Port Header ..............................................................................2-7 Power Connectors ..............................................................................2-8 Expansion Terminal Holes..................................................................2-9 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.2.1 2.3

Atmel CPLD ISP Cable .............................................................................2-9

Section 3 CPLD Design Flow Tutorial .................................................................. 3-1

3.1 3.2 3.3 Overview ...................................................................................................3-1 Create a Project Using the New Project Wizard .....................................3-1 Add a Design File......................................................................................3-6

Section 4 Schematic Diagrams............................................................................. 4-1

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Section 1 Introduction

1.1

CPLD Development/ Programmer Kit

The Atmel CPLD Development/Programmer Kit (P/N: ATF15xx-DK2) is a complete development system and an In-System Programming (ISP) programmer for the ATF15xx family of industry-standard pin-compatible Complex Programmable Logic Devices (CPLDs) with Logic Doubling features. This kit provides designers a very quick and easy way to develop, prototype and evaluate new designs with an ATF15xx CPLD. With the availability of the different Socket Adapter Boards to support all the package types offered in the ATF15xx family of ISP CPLDs, this CPLD Development/Programmer Board can be used as an ISP programmer to program the ATF15xx ISP CPLDs in all the available package types through the industry-standard JTAG interface (IEEE 1149.1a-1993).

Figure 1-1. Contents of the ATF15xx-DK2

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1.3
1.3.1

Kit Features
CPLD Development/ Programmer Board 10-lead JTAG-ISP Port Regulated Power Supply Circuitry for 9V DC Power Source 5V or 3.3V VCC Operation 84-lead PLCC Socket Adapter Board Socket Adapter Board Headers Expansion Terminal Holes for all Input and I/O pins of the ATF15xx Device 2 MHz Crystal Oscillator Eight 8-segment LED Displays Global Clear and Output Enable Push Button Switches ATF1508AS-15JC84, 5V 128-Macrocell ISP CPLD with Logic Doubling Architecture ATF1508ASVL-20JC84, 3.3V Low-power 128-Macrocell ISP CPLD with Logic Doubling Architecture 5V/3.3V ISP Download Cable for PC Parallel Printer (LPT) Port Free Atmel-WinCUPL Design Software 30-day Trial Version of Atmel ProChip Designer Software Full Licensed Version of Atmel ProChip Designer Software (permanent license required) Atmel CPLD ISP Software (ATMISP) POF2JED Conversion Utility Logic Doubling Support and Documentation

1.3.2

Logic Doubling CPLDs

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1.3.4

PLD Software CD-ROM

1.3.3

CPLD ISP Download Cable

n n n n n n n n n n n n n n n n n n n n n n

1.2

Kit Contents

CPLD Development/Programmer Board 84-lead PLCC Socket Adapter Board (P/N: ATF15xx-SAJ84)(1) Atmel CPLD ISP Download Cable Atmel PLD Software CD-ROM (includes ProChip Designer, Atmel-WinCUPL and other EPLD software) Atmel CD-ROM Data Books One ATF1508AS 5V 84-lead PLCC Sample Device One ATF1508ASVL 3.3V, low-power, 84-lead PLCC Sample Device Atmel CPLD Development/Programmer Kit User Guide
1. Only the 84-lead PLCC Socket Adapter Board is included in this kit. Other Socket Adapter Boards are sold separately. Please refer to Section 1.6 for ordering information of the Socket Adapter Boards.

Note:

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1.5

System Requirements

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1.3.5

Atmel CD-ROM Data Books

Data Sheets Application Notes Manuals and User Guides

The Atmel CPLD Development/Programmer Board supports the following devices in all speed grades and packages:
ATF1502AS/ASL ATF1502ASV ATF1502SE/SEL ATF1502AE/AEL ATF1504AS/ASL ATF1504ASV/ASVL ATF1504SE/SEL ATF1504AE/AEL ATF1508AS/ASL ATF1508ASV/ASVL ATF1508SE/SEL ATF1508AE/AEL ATF1516SE/SEL (Future) ATF1516AE/AEL (Future) ATF1532AE/AEL (Future)

The minimum hardware and software requirements to program an ATF15xx ISP CPLD on the CPLD Development/Programmer Board through the Atmel CPLD ISP Software (ATMISP) V4.0 or later are: Pentium or Pentium-compatible microprocessor based computer Windows 98, Windows NT 4.0, Windows ME, or Windows 2000 16-MByte RAM 10-MByte free hard disk space Windows-supported mouse Available parallel printer (LPT) port 9V DC power supply with 500 mA of supply current SVGA monitor (800 x 600 resolution)

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Ordering Information

Part Number ATF15xx-DK2 ATF15xx-SAA44 ATF15xx-SAJ44 ATF15xx-SAC49 ATF15xx-SAJ68 ATF15xx-SAJ84 ATF15xx-SAA100 ATF15xx-SAQ100 ATF15xx-SACT100 ATF15xx-SAA144 ATF15xx-SAQ160 ATF15xx-SAC169 ATF15xx-SAQ208 ATF15xx-SACT256

Description Atmel CPLD Development/Programmer Kit 44-lead TQFP Socket Adapter Board 44-lead PLCC Socket Adapter Board 49-lead BGA Socket Adapter Board 68-lead PLCC Socket Adapter Board 84-lead PLCC Socket Adapter Board 100-lead TQFP Socket Adapter Board 100-lead PQFP Socket Adapter Board 100-lead BGA Socket Adapter Board 144-lead TQFP Socket Adapter Board 160-lead PQFP Socket Adapter Board 169-lead BGA Socket Adapter Board 208-lead PQFP Socket Adapter Board 256-lead BGA Socket Adapter Board

1.7

Technical Support

For technical support on any Atmel PLD related issues, please contact the Atmel PLD Applications Group at: Hotline: Email: URL: 1-408-436-4333 pld@atmel.com www.atmel.com/atmel

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1.8
1.8.1

References
ProChip Designer

To help PLD designers use the different Atmel PLD software, documentation such as Help Files, Tutorials, Application Notes/Briefs, and User Guides are available.

ProChip Designer Help Files Tutorials Known Problems & Solutions

From the ProChip Designer main window, click on HELP and then select PROCHIP DESIGNER HELP. From the ProChip Designer main window, click on HELP and then select TUTORIALS. From the ProChip Designer main window, click on HELP and then select REVIEW KPS.

1.8.2

Atmel-WinCUPL
Help Files CUPL Programmers Reference Guide Tutorial Known Problems & Solutions From the Atmel-WinCUPL main window, click on HELP and then select CONTENTS. From the Atmel-WinCUPL main window, click on HELP and then select CUPL PROGRAMMERS REFERENCE. From the Atmel-WinCUPL main window, click on HELP, select ATMEL INFO and then select TUTORIAL1.PDF. From the Atmel-WinCUPL main window, click on HELP, select ATMEL INFO and then select CUPL_BUG.PDF.

1.8.3

ATMISP
Help Files Tutorial Known Problems & Solutions From the ATMISP main window, click on HELP and then select ISP HELP. From the ATMISP main window, click on HELP, and then select ATMISP TUTORIAL. Using Windows Explorer, go to the directory where ATMISP is installed and open the README.TXT file through any ASCII text editor.

1.8.4

POF2JED
ATF15xx Conversion Application Brief From the POF2JED main window, click on HELP and then select CONVERSION OPTIONS.

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Section 2 Hardware Description

2.1

Atmel CPLD Development/ Programmer Board

The Atmel CPLD Development/Programmer Board, along with the Socket Adapter Board as shown in Figure 2-1, contains many features that designers will find very useful when developing, prototyping, or evaluating their ATF15xx CPLD design. Features such as push-button switches, 8-segment display LEDs, 2 MHz crystal oscillator, 5V/3.3V VCC selector, JTAG-ISP port, and expansion terminal holes make this a very versatile starter/development kit and an ISP programmer for the ATF15xx family of JTAG-ISP CPLDs.

Figure 2-1. CPLD Development/Programmer Board with 84-lead PLCC Socket Adapter Board
8-segment Display LEDs 2 MHz Crystal Oscillator Power Supply Header Power Supply Jack Clock Select Jumper

Power Switch Power LED 84-pin PLCC Socket

Expansion Terminal Holes JTAG Port Header

VCC Select Jumper

GCLR Push-button Switch

GOE Push-button Switch

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2.1.1

8-segment Display LEDs

The Atmel CPLD Development/Programmer Board contains eight 8-segment LEDs to allow the designer to observe the outputs of the ATF15xx. These eight LEDs are labeled DSP1 to DSP8 on the board. These eight display LEDs are common anode LEDs with the common anode lines connected to VCC and the individual cathode lines connected to the I/O pins of the ATF15xx CPLD on the CPLD Development/Programmer Board. To turn on a particular segment of an LED, the corresponding ATF15xx I/O pin connected to this LED segment must be in a logical-0 state. Hence, the outputs of the ATF15xx need to be configured as active-low outputs in the design file.

Figure 2-2. 8-segment Display LED

A F G E D Dot C B

Each segment of the display LED is hard-wired to one specific I/O pin of the ATF15xx. For the higher pin count devices (100-lead and larger), all eight segments of the eight LEDs are connected to the I/O pins of the ATF15xx. However, for the lower pin count devices (84-lead and smaller), only a subset of the LED segments are connected to the ATF15xx's I/O pins. Table 2-1 to Table 2-8 below show the connections of the LEDs to the ATF15xx in all the different package types.

Table 2-1. Connections of LEDs to ATF15xx 44-lead PLCC

DSP/Sgt 1/A 1/B 1/C 1/D 1/E 1/F 1/G 1/DOT 2/A 2/B 2/C 2/D 2/E 2/F 2/G 2/DOT PLD Pin # NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC DSP/Sgt 3/A 3/B 3/C 3/D 3/E 3/F 3/G 3/DOT 4/A 4/B 4/C 4/D 4/E 4/F 4/G 4/DOT PLD Pin # 28 26 24 25 27 29 31 NC 36 33 34 40 37 39 41 NC DSP/Sgt 5/A 5/B 5/C 5/D 5/E 5/F 5/G 5/DOT 6/A 6/B 6/C 6/D 6/E 6/F 6/G 6/DOT PLD Pin # 6 4 5 8 11 9 12 NC 18 16 14 17 19 20 21 NC DSP/Sgt 7/A 7/B 7/C 7/D 7/E 7/F 7/G 7/DOT 8/A 8/B 8/C 8/D 8/E 8/F 8/G 8/DOT PLD Pin # NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

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Table 2-2. Connections of LEDs to ATF15xx 44-lead TQFP

DSP/Sgt 1/A 1/B 1/C 1/D 1/E 1/F 1/G 1/DOT 2/A 2/B 2/C 2/D 2/E 2/F 2/G 2/DOT PLD Pin # NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC DSP/Sgt 3/A 3/B 3/C 3/D 3/E 3/F 3/G 3/DOT 4/A 4/B 4/C 4/D 4/E 4/F 4/G 4/DOT PLD Pin # 21 19 18 20 22 23 25 NC 30 27 28 34 31 33 35 NC DSP/Sgt 5/A 5/B 5/C 5/D 5/E 5/F 5/G 5/DOT 6/A 6/B 6/C 6/D 6/E 6/F 6/G 6/DOT PLD Pin # 44 42 43 2 5 3 6 NC 12 10 8 11 13 14 15 NC DSP/Sgt 7/A 7/B 7/C 7/D 7/E 7/F 7/G 7/DOT 8/A 8/B 8/C 8/D 8/E 8/F 8/G 8/DOT PLD Pin # NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

Table 2-3. Connections of LEDs to ATF15xx 68-lead PLCC

DSP/Sgt 1/A 1/B 1/C 1/D 1/E 1/F 1/G 1/DOT 2/A 2/B 2/C 2/D 2/E 2/F 2/G 2/DOT PLD Pin # NC NC NC NC NC NC NC NC 37 33 36 39 41 40 42 NC DSP/Sgt 3/A 3/B 3/C 3/D 3/E 3/F 3/G 3/DOT 4/A 4/B 4/C 4/D 4/E 4/F 4/G 4/DOT PLD Pin # 47 45 44 46 49 51 52 NC 56 54 55 61 59 60 64 NC DSP/Sgt 5/A 5/B 5/C 5/D 5/E 5/F 5/G 5/DOT 6/A 6/B 6/C 6/D 6/E 6/F 6/G 6/DOT PLD Pin # 5 4 7 9 13 8 10 NC 17 14 15 18 22 20 23 NC DSP/Sgt 7/A 7/B 7/C 7/D 7/E 7/F 7/G 7/DOT 8/A 8/B 8/C 8/D 8/E 8/F 8/G 8/DOT PLD Pin # 25 24 27 29 32 28 30 NC NC NC NC NC NC NC NC NC

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Table 2-4. Connections of LEDs to ATF15xx 84-lead PLCC

DSP/Sgt 1/A 1/B 1/C 1/D 1/E 1/F 1/G 1/DOT 2/A 2/B 2/C 2/D 2/E 2/F 2/G 2/DOT PLD Pin # 49 46 48 50 52 51 54 NC 57 55 56 58 61 60 63 NC DSP/Sgt 3/A 3/B 3/C 3/D 3/E 3/F 3/G 3/DOT 4/A 4/B 4/C 4/D 4/E 4/F 4/G 4/DOT PLD Pin # 67 64 65 68 70 69 73 NC 76 74 75 77 80 79 81 NC DSP/Sgt 5/A 5/B 5/C 5/D 5/E 5/F 5/G 5/DOT 6/A 6/B 6/C 6/D 6/E 6/F 6/G 6/DOT PLD Pin # 6 4 5 8 10 9 11 45 16 12 15 17 20 18 21 44 DSP/Sgt 7/A 7/B 7/C 7/D 7/E 7/F 7/G 7/DOT 8/A 8/B 8/C 8/D 8/E 8/F 8/G 8/DOT PLD Pin # 25 22 24 27 29 28 30 41 34 31 33 35 37 36 39 40

Table 2-5. Connections of LEDs to ATF15xx 100-lead TQFP

DSP/Sgt 1/A 1/B 1/C 1/D 1/E 1/F 1/G 1/DOT 2/A 2/B 2/C 2/D 2/E 2/F 2/G 2/DOT PLD Pin # 47 52 48 46 44 45 42 49 54 41 40 56 58 57 60 55 DSP/Sgt 3/A 3/B 3/C 3/D 3/E 3/F 3/G 3/DOT 4/A 4/B 4/C 4/D 4/E 4/F 4/G 4/DOT PLD Pin # 67 64 63 65 68 69 71 61 80 76 78 84 81 83 85 75 DSP/Sgt 5/A 5/B 5/C 5/D 5/E 5/F 5/G 5/DOT 6/A 6/B 6/C 6/D 6/E 6/F 6/G 6/DOT PLD Pin # 96 93 94 97 99 98 100 92 12 9 8 10 13 14 16 6 DSP/Sgt 7/A 7/B 7/C 7/D 7/E 7/F 7/G 7/DOT 8/A 8/B 8/C 8/D 8/E 8/F 8/G 8/DOT PLD Pin # 20 17 19 21 25 23 29 22 32 30 31 33 36 35 37 28

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Table 2-6. Connections of LEDs to ATF15xx 100-lead PQFP

DSP/Sgt 1/A 1/B 1/C 1/D 1/E 1/F 1/G 1/DOT 2/A 2/B 2/C 2/D 2/E 2/F 2/G 2/DOT PLD Pin # 48 50 49 47 44 46 43 51 56 54 42 58 60 59 62 52 DSP/Sgt 3/A 3/B 3/C 3/D 3/E 3/F 3/G 3/DOT 4/A 4/B 4/C 4/D 4/E 4/F 4/G 4/DOT PLD Pin # 69 66 65 67 70 71 73 63 82 78 81 86 83 85 87 77 DSP/Sgt 5/A 5/B 5/C 5/D 5/E 5/F 5/G 5/DOT 6/A 6/B 6/C 6/D 6/E 6/F 6/G 6/DOT PLD Pin # 98 95 96 99 3 100 4 94 14 11 10 12 15 16 18 8 DSP/Sgt 7/A 7/B 7/C 7/D 7/E 7/F 7/G 7/DOT 8/A 8/B 8/C 8/D 8/E 8/F 8/G 8/DOT PLD Pin # 22 19 21 23 27 25 39 24 37 38 35 33 31 34 32 30

Table 2-7. Connections of LEDs to ATF15xx 144-lead TQFP

DSP/Sgt 1/A 1/B 1/C 1/D 1/E 1/F 1/G 1/DOT 2/A 2/B 2/C 2/D 2/E 2/F 2/G 2/DOT PLD Pin # 79 78 74 80 82 81 83 77 88 86 87 91 93 92 94 84 DSP/Sgt 3/A 3/B 3/C 3/D 3/E 3/F 3/G 3/DOT 4/A 4/B 4/C 4/D 4/E 4/F 4/G 4/DOT PLD Pin # 100 98 99 101 106 102 107 97 118 119 117 114 112 116 113 111 DSP/Sgt 5/A 5/B 5/C 5/D 5/E 5/F 5/G 5/DOT 6/A 6/B 6/C 6/D 6/E 6/F 6/G 6/DOT PLD Pin # 134 137 136 133 138 132 131 139 9 7 6 8 10 11 15 5 DSP/Sgt 7/A 7/B 7/C 7/D 7/E 7/F 7/G 7/DOT 8/A 8/B 8/C 8/D 8/E 8/F 8/G 8/DOT PLD Pin # 25 22 23 26 28 27 29 21 41 31 32 38 37 40 39 30

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Table 2-8. Connections of LEDs to ATF15xx 160-lead PQFP

DSP/Sgt 1/A 1/B 1/C 1/D 1/E 1/F 1/G 1/DOT 2/A 2/B 2/C 2/D 2/E 2/F 2/G 2/DOT PLD Pin # 91 89 90 80 73 78 72 88 69 71 68 92 94 93 96 70 DSP/Sgt 3/A 3/B 3/C 3/D 3/E 3/F 3/G 3/DOT 4/A 4/B 4/C 4/D 4/E 4/F 4/G 4/DOT PLD Pin # 102 100 98 101 103 105 106 97 110 108 109 123 111 121 122 107 DSP/Sgt 5/A 5/B 5/C 5/D 5/E 5/F 5/G 5/DOT 6/A 6/B 6/C 6/D 6/E 6/F 6/G 6/DOT PLD Pin # 11 159 160 10 12 13 14 158 20 18 16 19 21 23 24 15 DSP/Sgt 7/A 7/B 7/C 7/D 7/E 7/F 7/G 7/DOT 8/A 8/B 8/C 8/D 8/E 8/F 8/G 8/DOT PLD Pin # 29 27 28 52 50 53 51 25 43 49 30 31 32 41 33 48

2.1.2

Push-button Switches

Two push-button switches are provided to allow the user to control the logic states of the OE1 and GCLR inputs of the ATF15xx. These two switches are labeled GOE and GCLR on the board. The GCLR push-button switch is a momentary Single-Pole Single-Throw (SPST) normally open switch while the GOE push-button switch is a snap-acting momentary SPST normally open switch. As shown in the CPLD Development/Programmer Board schematic in Figure 4-1, these two switches are normally open and the GCLR and GOE signals are pulled-up to VCC when they are not depressed. When the switches are depressed, the GCLR and GOE signals are connected to GND. The output of the GCLR switch is connected to the GCLR dedicated input pin of the ATF15xx, and it is intended to be used as an active-low reset signal to reset the registers in the ATF15xx. The output of the GOE switch is connected to the OE1 dedicated input pin of the ATF15xx. It is intended to be used as an active-high or active-low output enable signal to control the enabling/disabling of the tri-state output buffers in the ATF15xx. However, these two switches can also be used to generate general logic input signals to the GCLR and OE1 input pins of the ATF15xx.

2.1.3

Clock Select Jumper The Clock Select Jumper, labeled JPCLK, on the CPLD Development/Programmer Board is a two-position jumper that allows the user to select which GCLK dedicated input pin (either GCLK1 or GCLK2) of the ATF15xx should be connected to the output of the 2 MHz crystal oscillator. In addition, the jumper can be removed to allow an external clock source to be connected to GCLK1 and/or GCLK2 of the ATF15xx. Table 2-9 shows the pin numbers for the GCLR, OE1, GCLK1 and GCLK2 dedicated input pins of the ATF15xx in all the available package types.

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Table 2-9. Pin Numbers of GCLR, OE1, GCLK1 and GCLK2

Signal GCLR OE1 GCLK1 GCLK2 44-lead TQFP 39 38 37 40 44-lead PLCC 1 44 43 2 68-lead PLCC 1 68 67 2 84-lead PLCC 1 84 83 2 100-lead PQFP 91 90 89 92 100-lead TQFP 89 88 87 90 144-lead TQFP 127 126 125 128 160-lead PQFP 141 140 139 142

2.1.4

VCC Select Jumper

The VCC Select Jumper, labeled VCC Select, on the CPLD Development/Programmer Board is a two-position jumper that allows the users to select the V CC voltage level (either 3.3V or 5.0V) used by various components on the CPLD Development/Programmer Board. This voltage generated by the on-board voltage regulation circuitry is applied to the VCC input pins (both VccINT and VccIO) of the ATF15xx, the common anode lines of the eight 8-segment LEDs, the VCC input of the 2 MHz crystal oscillator, the two push-button switches, and the VCC pin (Pin 4) of the 10-pin JTAG port header labeled JTAG. Therefore, when a 3.3V device (ATF15xxASV/ASVL/AE/AEL) is used on this board, the VCC Select Jumper must be in the 3.3V position. On the other hand, when a 5V device (ATF15xxAS/ASL/SE/SEL) is used on this board, the VCC Select Jumper must be in the 5.0V position. This is also true when the ATF15xx is being programmed through ISP on this board.

2.1.5

JTAG Port Header

The JTAG Port Header, labeled JTAG, on the CPLD Development/Programmer Board is used to connect the ATF15xx's JTAG port pins (TCK, TDI, TMS and TDO) through the ISP download cable to the parallel printer (LPT) port of a PC for ISP programming of the ATF15xx. Table 2-10 shows the pin numbers for the four JTAG port pins of the ATF15xx in all the available package types.

Table 2-10. Pin Numbers of JTAG Port Signals

Signal TDI TDO TMS TCK 44-lead TQFP 1 32 7 26 44-lead PLCC 7 38 13 32 68-lead PLCC 12 57 19 50 84-lead PLCC 14 71 23 62 100-lead PQFP 6 75 17 64 100-lead TQFP 4 73 15 62 144-lead TQFP 4 104 20 89 160-lead PQFP 9 112 22 99

The ISP algorithm is controlled by the ATMISP software, which runs on the PC. The four JTAG signals are generated by the LPT port and they are buffered by the ISP download cable before going into the ATF15xx on the CPLD Development/Programmer Board. The pinout for the 10-pin JTAG Port Header on the CPLD Development/Programmer Board is shown in Figure 2-3 and the dimensions of this 10-pin male JTAG header are shown in Figure 2-4.

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Figure 2-3. Pinout Diagram of 10-pin JTAG Port Header (Top-view)

TCK TDO TMS NC TDI 1 3 5 7 9 2 4 6 8 10 GND VCC NC NC GND

Figure 2-4. 10-pin Male Header Dimensions

Top View 0.100 0.100 Side View 0.025Sq.

0.235 All dimensions are in inches

The pinout of this 10-pin JTAG Port Header is compatible with the Altera ByteBlaster and ByteBlasterMV cables. In addition, the ATMISP software allows users to choose either the Atmel CPLD ISP Cable or the ByteBlaster/ByteBlasterMV cable to implement ISP. 2.1.6 Power Connectors The Atmel CPLD Development/Programmer Board contains two different types of power connectors, and either one can be used to connect to a 9V DC power source to power the board. The first power connector, labeled JPower, is a barrel power jack with a 2.1 mm diameter post and it mates to a 2.1 mm (inner diameter) x 5.5 mm (outer diameter) female plug. The second power connector, labeled JP Power, is a 4-pin male 0.1" header with 0.025" square posts. The availability of these two types of power connectors allows the users to choose the type of power supply equipment to use for the CPLD Development/Programmer Board.

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2.2

Socket Adapter Board

Atmel CPLD Development/Programmer Socket Adapter Boards are circuit boards that interface with the Atmel CPLD Development/Programmer Board. They are used in conjunction with the CPLD Development/Programmer Board to evaluate/program Atmel ISP CPLDs in different package types. Currently, there are nine Socket Adapter Boards available covering all the package types offered in the ATF15xx family of CPLDs. They include 44-lead PLCC, 44-lead TQFP, 68-lead PLCC, 84-lead PLCC, 100-lead TQFP, 100-lead PQFP, 144-lead TQFP and 160-lead PQFP. New Socket Adapter Boards will become available when new packages are offered. Each socket adapter board contains a socket for the Atmel ATF15xx device on the top side and male headers on the bottom side. The headers on the bottom side mate with the female headers, labeled JPLEFT and JPRIGHT, on the CPLD Development/Programmer Board. The eight 8-segment LEDs, push-button switches, JTAG port signals, crystal oscillator, VCC, and GND on the CPLD Development/Programmer Board are connected to the ATF15xx device on the Socket Adapter Board through these two rows of connectors.

2.2.1

Expansion Terminal Holes

Rows of expansion terminal holes suitable for 0.1" headers with 0.025" square posts are available on each of the Socket Adapter Boards to allow users to interface the ATF15xx to an external circuit board. All input and I/O pins except the four JTAG port pins of the ATF15xx are routed to these expansion terminal holes, and the corresponding pin numbers are marked next to the terminal holes. Please refer to the Socket Adapter Board schematics in Section 4 for the pinouts of the expansion terminal holes. On the bottom side of the Socket Adapter Boards, traces connecting the pairs of expansion terminal holes can be cut to isolate the LEDs, push-button switches and crystal oscillator from the ATF15xx on the Socket Adapter Board. This allows the users to gain complete control and access to all input and I/O pins of the ATF15xx.

2.3

Atmel CPLD ISP Cable

The Atmel CPLD ISP Cable connects the parallel printer (LPT) port of the users PC to the 10-pin JTAG header on the Atmel CPLD Development/Programmer Board or a custom circuit board. This is shown in Figure 2-5. This ISP cable acts as a buffer to buffer the JTAG signals between the PC's LPT port and the ATF15xx on the circuit board. The circuit schematic of the Atmel CPLD ISP Cable is shown in Figure 4-10 and Figure 4-11. The Power-On LED on the back of the 25-pin male connector housing indicates that the cable is connected properly. Make sure this LED is turned on before using the Atmel CPLD ISP Software (ATMISP). This ISP cable consists of a 25-pin (DB25) male connector, which is connected to the LPT port of a PC. The 10-pin female plug connects to the 10-pin male JTAG header on the ISP circuit board. The red color stripe on the ribbon cable indicates the orientation of Pin 1 of the female plug. The 10-pin male JTAG header on the CPLD Development/Programmer Board is polarized to prevent users from inserting the female plug in the wrong orientation. If the user is attempting to program low voltage (3.3V) devices, the user needs to use Rev. 4 or later of the Atmel CPLD ISP Cable. This and later revisions will support both the 3.3V and 5V ATF15xx ISP CPLDs. Earlier revisions of the cable only supported 5V devices. When programming 3.3V devices, the V CC supplied to the ISP cable should also be 3.3V. Similarly, the V CC supplied to the ISP cable should be 5.0V when programming 5V devices.

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Figure 2-5. Atmel ISP Cable Connection to ISP Hardware Board/Circuit Board

Figure 2-6 shows the pinout for the 10-pin Female header on the Atmel-ISP Cable. The pinout on the 10-pin male header on the PC board (if used for ISP) must match this pinout.

Figure 2-6. Atmel ISP Download Cable 10-pin Female Header Pinout

Note:

The users circuit board must supply VCC and GND to the Atmel CPLD ISP Cable through the 10-pin male header (See Figure 2-3).

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Section 3 CPLD Design Flow Tutorial

3.1

Overview

This tutorial will guide the user through a complete design cycle for the Atmel ATF15xx CPLD with Logic Doubling architecture. It will go through each phase of the design cycle step-by-step from design entry, logic synthesis, device fitting, in-system programming, and finally verifying the design on the Atmel CPLD Development/Programming Board.

Note:

To complete this tutorial, ProChip Designer V4.0 or later and Atmel-ISP Software (ATMISP) V4.0 or later are required.

3.2

Create a Project Using the New Project Wizard

Before starting the design process, a Project File must be created within ProChip Designer. ProChip Designer's New Project Wizard provides a very easy way to create a new Project File. 1. Click on the START .... PROGRAMS .... PROCHIP Icon to launch ProChip Designer. Or double-click on the PROCHIP icon on the desktop.
(1) Click to launch ProChip Designer

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2.

Click on PROJECT .... NEW or double-click on the NEW PROJECT shortcut button to launch the New Project Wizard.
(2) Click to create New Project

3.

Click on the NEXT button to start the project file creation process.

(3) Click Next to Start

4. 5. 6.

Click on the BROWSE button to open the browser window. Use C:\PROCHIP\DESIGNS\CUPL as the directory of the project. Enter DEV_KIT.APJ as the project filename. The extension of a project file must be .APJ. The name and directory of the design project is specified in this window. All design, simulation and other project files must be placed in this project directory.

Note:

(4) Click on Browse

(5) Select the Project Directory (6) Enter the Project Filename

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7.

Choose [ATF1508AS-10JC84] as the target device type for the project. Also review the Filters that allow for selection of a specific Speed Grade or Package Type.

(7) Select the Device Type

8.

Select CUPL ALTIUM as the software tool for this design flow.

(8) Select the Design Flow

With ProChip Designer V4.0 and later, the five possible design flows and their corresponding design entry types supported are listed in the table below:

Design Flow CUPL Altium

Design Entry Type CUPL design entry through Altium Protel 99SE Verilog design entry through Exemplar Leonardo Spectrum VHDL design entry through the Altium PeakFPGA
(1)

Verilog Exemplar(1) VHDL Altium VHDL Exemplar

VHDL design entry through Exemplar Leonardo Spectrum Schematic design entry through Altium Protel 99SE

Schematic Altium Note:

1. Design flow require Mentor Graphics Leonardo Spectrum software with Atmel CPLD support.

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9.

Select DONE WITH PARTS so that there will be only one device in this project.

On the other hand, users can select ADD MORE PARTS to include more parts to the current Project Directory.

(9) Select Done with Parts

10. Click the FINISH button to finish the New Project Wizard and the project creation process. This closes the New Project Wizard and opens the ProChip Designer window. The Sources in the project are shown in the Left window.

(10) Click Finish to End New Project Wizard

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11. Click on the Device Icon [ATF1508AS-10JC84] to view the Design Flow window.

Project Sources Window

Information Dialog Box

Message Window

(11) Click on the Device Icon

Project File Window

Design Flow Window

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3.3

Add a Design File

Once the Project File is created, the next step is to add the design source file(s) into the users project. For this tutorial, a single CUPL design file will be added into the project. Click on the ADD/EDIT button from Source Manager to open the Source Manager Window. The user can view the Source Manager Help File by clicking on the Help button within the Source Manager Window to view the description for the different processes. 2. In the Source Manager Window, click on the ADD button to add a CUPL design file to the project. 1. 3. In the File Manager Window, select LOGIC_D8.PLD from the C:\PROCHIP\DESIGNS\CUPL directory as the source design file for this project.

(1) Click Add/Edit to Open Source Manager Window

(3) Select CUPL Source File

(2) Click ADD to add Design File

This "LOGIC_D8.PLD" is a CUPL design that uses the eight 8-segment LED displays and the 2 MHz oscillator on the Atmel CPLD Development/Programmer Board to generate a scrolling message that displays the words "logic doubling" on the LEDs. The GOE push-button switch is used to control the direction that the message scrolls in (left or right). The GCLR push-button switch is used to reset the counter registers. When the GCLR push-button switch is depressed, the message will stop scrolling. This CUPL design can be compiled using either the ProChip Designer or the Atmel-WinCUPL software. The first section of the LOGIC_D8.PLD as shown below pre-defines which segments of the LED should be asserted in order to display the desired letter or number. For example, to display the upper case letter "C", segments A, D, E, and F need to be set to low (active low) and the remaining segments need to be set to high.

$define $define $define

Font0 'b'1000000 Font1 'b'1111001 : FontA 'b'0001000

/* = ( /* = (

_f_e_d_c_b_a ); _c_b ); _c_b_a );

0 */ 1 */ A */

/* = (_g_f_e

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The next section of this CPLD design as shown below illustrates how to declare and assign pin numbers in the CUPL language to the input and output signals. The input and output pin assignments are assigned according to the connections between the CPLD and the eight 8-segment LED's as shown in the connection tables (Table 2-1 to Table 28) in Section 2.
/* Inputs pin 1 = pin 83 = pin 84 = */ GCLR; /* Global Clear input */ MCLK; /* Global Clock input */ GOE; /* GOE1 button used as direction control */

/* Outputs */ /* DSP1 */ pin 49 = LED1A; pin 46 = LED1B; pin 48 = LED1C; pin 50 = LED1D; pin 52 = LED1E; pin 51 = LED1F; pin 54 = LED1G;

/* /* /* /* /* /* /*

LED1 LED1 LED1 LED1 LED1 LED1 LED1

segment segment segment segment segment segment segment

A B C D E F G

*/ */ */ */ */ */ */

Next, the buried signals for the counter and state machine are declared as PINNODE's as shown below. The feedback and/or the foldback paths available in each macrocell implement these buried signals. For the listing of the pinnode numbers, please refer to the "ATF15xx Device Help" section of the ProChip Designer Help File.
pinnode [618,634,650,687]= [CA20..CA17]; pinnode = [CA16..CA0]; pinnode = [SM7..SM0];

After assigning the input, output and buried signals, the related signals (i.e. the LED segments and buried counter) are grouped together as shown below to make the design source code more readable and manageable. In CUPL, the "Field" declaration can be used to group a specific set of signals.
Field DSP1 Field DSP2 : Field CNT_A Field SM = [LED1G,LED1F,LED1E,LED1D,LED1C,LED1B,LED1A]; = [LED2G,LED2F,LED2E,LED2D,LED2C,LED2B,LED2A]; = [CA20..CA0]; = [SM7..SM0];

Next, a 21-bit buried up-counter implemented using D-type Flip-flops is shown below and it is used to divide the 2.0 MHz clock into a 0.954 Hz (2 MHz 221 = 0.954 Hz) signal that can be used to display the text messages. The last bit of this counter is used as the clock for the state machine that controls the display sequence of the messages on the LEDs.
CA0.d = !CA0; CA1.d = CA0 $ CA1; : CA7.d = (CA6 & CA5 & CA4 & CA3 & CA2 & CA1 & CA0) $ CA7; : CNT_A.ck = MCLK; CNT_A.ar = !GCLR;

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The next section of this PLD design is a state machine with 15 states to control the display sequence of the text messages on the LEDs. The GOE push-button switch on the CPLD Development/Programmer Board controls the flow of this state machine. When this switch is in the "up" position, the state machine will go from RESET to State-0 to State-1 to State-2 and so on until it reaches State-14 and then it will go back to State-0. On the other hand, if the GOE switch is in the "down" position, the state machine will go in the opposite direction (i.e. State-14 to State13 .. etc).
SM.ck = COUNTER_1; sequence SM { present RESET present if if : present if if } next S0; S0 SM_DIR next S1; !SM_DIR next S14; S14 SM_DIR next S0; !SM_DIR next S13;

Finally, the last section of the PLD design will assign the appropriate letters or numbers to the eight 8-segment LEDs to be displayed during the different states of the state machine. The user can easily change the letters/numbers to be displayed by changing this section of the code to the appropriate pre-defined letters/numbers.
LED1 = # # # # # # # # # # # # # # # FontBK FontBK FontLl FontLo FontLg FontLi FontLc FontBK FontLd FontLo FontLu FontLb FontLl FontLi FontLn FontLg & & & & & & & & & & & & & & & & SM:[RESET] SM:[S0] SM:[S1] SM:[S2] SM:[S3] SM:[S4] SM:[S5] SM:[S6] SM:[S7] SM:[S8] SM:[S9] SM:[S10] SM:[S11] SM:[S12] SM:[S13] SM:[S14];

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3.4

Compile the CUPL Design

In this part of the tutorial, the CUPL design will be compiled through the Logic Synthesis process into a set of optimized/minimized logic equations. 1. Click on the CUPL Design Ex. button in the Design Flow Window to open the Logic Synthesis Window.

(1) Open Logic Synthesis

2. 3. 4.

Make sure all of the options in the Optimization section are unchecked. Make sure the Minimization setting is set to Quick. Click on the Compile button to start the CUPL compile process.

(2) Make sure these Options are Not Checked

(3) Set to Quick

(4) Start the Compile Process

The user can click on the Set Defaults button and it will automatically specify the Synthesis tool in the Tool Text box. If the user clicks on the CUPL Tab, it shows the various Synthesis options. Please refer to the HELP file for further description.

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3.5

Fit the Synthesized Design File

In Section 3.4, the Logic Synthesis portion of the CPLD Design Flow was completed. On successful compilation, the CUPL compiler tool produces a PLA output file (with extension .pla). A PLA file contains the netlist of the optimized and minimized logic equations. It is now necessary to map this netlist into a specific Atmel PLD architecture using the Atmel Fitter. 1. The user can now proceed to the Device Fitter portion of the Design Flow by clicking on the Atmel Fitter button.

(1) Open the Atmel Fitter Window

The user can either use the Default options or specify Fitter properties. ProChip Designer will automatically select the PLA file associated to the current design project and the tool type. In this example, since the target device is an ATF1508AS, the fit1508.exe device fitter will be selected. The fitter creates the important JEDEC and FIT REPORT output files. They contain the data for programming the Device (using In-System Programming or on a third party device programmer) and the pin assignments required for board layout respectively. Please review the Global Device Parameters and Pin/Node Options as well. The Help Files also show the Device Pin_Node lists for each of the ATMEL CPLDs. 2. 3. 4. Make sure the JTAG box is checked. This enables the JTAG port for ISP programming. Make sure the PIN FIT CONTROL setting is set to Keep. This will ensure that the pin assignments in the PLD file will be kept during the Place-and-Route process. When all the fitter options are set, click on the Run Fitter button to fit the design.

(2) Check the JTAG box (3) Set the Pin Fit Control setting to KEEP

(4) Start the Fitting Process

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The Fitter Report (.FIT) File generated for this design is shown below.

Logic Array Block Cascades A: LC1 - LC16 B: LC17 - LC32 C: LC33 - LC48 D: LC49 - LC64 E: LC65 - LC80 F: LC81 - LC96 G: LC97 - LC112 H: LC113- LC128 Total Total Total Total Total Total Total Total Total Total :

Logic Cells 16/16(100%) 16/16(100%) 16/16(100%) 16/16(100%) 16/16(100%) 16/16(100%) 16/16(100%) 16/16(100%) 3/4 60/64 128/128 31/128 25/128 153/128 0 7 56 372

I/O Pins 8/16(50%) 8/16(50%) 8/16(50%) 6/16(37%) 6/16(37%) 8/16(50%) 8/16(50%) 8/16(50%) (75%) (93%) (100%) (24%) (19%) (119%)

Foldbacks 5/16(31%) 3/16(18%) 2/16(12%) 2/16(12%) 6/16(37%) 2/16(12%) 3/16(18%) 2/16(12%)

TotalPT 46/80(57%) 51/80(63%) 48/80(60%) 40/80(50%) 55/80(68%) 47/80(58%) 43/80(53%) 42/80(52%)

FanIN (19) (38) (38) (38) (32) (38) (25) (34) 0 0 0 0 0 0 0 0

dedicated input used: I/O pins used Logic cells used Flip-Flop used Foldback logic used Nodes+FB/MCells cascade used input pins output pins Pts

The ATF15xx Family devices Logic Doubling features provide extra I/O connectivity and logic reusability. Some of the Logic Doubling features available in the ATF15xx family of CPLDs are: Bury either Register or Combinatorial signal while using the other for output Dual independent feedback allows multiple latch functions per macrocell 5 product terms per macrocell, expandable to 40 per macrocell with cascade logic, plus 15 more with foldback logic D/T/Latch configurable flip-flops plus transparent latches Global and/or per macrocell Output Enable Single level Switch Matrix Up to 40 inputs per Logic Block

In the LOGIC_D8.PLD example given in this tutorial, Logic Blocks B, C D, and F have 37 or more signal inputs (Fan-In's) as shown in the Universal-Interconnect-Multiplexer assignments section of the .FIT file. The availability of wide Fan-In's to the Logic Blocks is one of the many Logic Doubling features. This feature improves the possibility of routing all the necessary signals from the Global Bus to the Logic Blocks. In addition, macrocells 37 and 59 of the ATF1508 are able to implement both combinatorial outputs (LED1G and LED8D) and buried registered signals (CA0 and RST) within the same macrocells. This is shown in the Resource Usage section of the .FIT file. For more examples of design techniques that utilize the Logic Doubling features of the ATF15xx Family, refer to Atmel's Logic Doubling White Paper and Reference Designs available on the Atmel website. These examples show how to apply Logic Doubling techniques to new product designs, to obtain the benefits of more features in a smaller and possibly less expensive chip, or spare logic resources for future revisions and reduce the risk of PCB re-spin.

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3.6

Program and Verify Design

In this step of the tutorial, the user will program an ATF1508AS 84-pin PLCC device on the Atmel CPLD Development/Programmer Board through ISP and then verify the design by observing the text messages displayed on the eight 8-segment LED displays of the CPLD Development/Programmer Board. The user will need to follow the steps below to setup the ATMISP software in order to program the ATF1508AS 84-pin PLCC on the CPLD Development/Programmer Board. 1. To create a new chain file, the ATMISP Software first needs to be launched either through the PROGRAM CHIP button in the ProChip Designer window, the ATMISP desktop icon or the Start ... Programs .. Atmel ISP menu.

(1) Launch ATMISP

If ATMISP is launched through ProChip Designer, steps 2 to 6 below can be skipped since ProChip Designer will automatically setup the appropriate chain file for the ISP operation. 2. To create a new chain file, select the New command under the File menu or click on the New Shortcut Button.

(2) Create New Chain File

3.

The first piece of information that the software asks for when creating a new chain is the number of devices in the JTAG chain. Therefore, enter 1 and then click OK since a 1-device JTAG chain will be programmed.

(3) Enter the number of devices

4.

Next the user will need to specify the properties of each JTAG device in the Device Properties window. First, select the target device type of the first device in the JTAG chain. For this tutorial, please select ATF1508AS as the target device type. In the JTAG Instruction field, the user can specify the appropriate JTAG instruction to be executed on this device in the chain. Please select Program/Verify to program and verify the ATF1508AS.

5.

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6.

The next step is to specify the JEDEC file to be programmed into the target device in the JEDEC File field. Click on the Browse button, change the directory to [..\PROCHIP\DESIGNS\CUPL"] and then select LOGIC_D8.JED as the target JEDEC file. Click OK to close the JTAG Device Properties window when all properties are specified.

(5) Specify JTAG Instruction (4) Specify Target Device Type

(6) Select JEDEC File

The next few steps require the user to setup the Atmel CPLD Development/Programmer Board to program the ATF1508AS through ISP. 7. Connect the 25-DB side of the Atmel-ISP Cable to the PC's parallel port and the 10-pin header side of the Atmel-ISP Cable to the Atmel CPLD Development Board as shown Figure 2-5. Connect a 9V AC/DC power adapter to the power connector (JPower) of the Atmel CPLD Development/Programmer Board. Set the 5V/3.3V jumper to 5V. This will set the system board VCC to 5V.

8. 9.

10. Set the JPCLK jumper to GCLK1 so that the output of the crystal oscillator will be connected to Pin 83 of the ATF1508AS. 11. Connect the 84-pin PLCC Socket Adapter Board onto the main Development/Programmer Board.
Note: If a device in a different package type is to be programmed, then the appropriate Socket Adapter Board must be used.

12. Switch the Power Switch to the ON position. 13. Select the appropriate LPT port in the Port Setting field. LPT 1 is the default port. 14. Select the ISP download cable type in the Cable Types field. The default cable type is the Atmel ISP Cable but it can be changed to the Altera ByteBlaster cable if the ByteBlaster cable is being used. Now both the users software and hardware are setup for ISP programming, and the user can execute the PROGRAM/VERIFY instruction to program the ATF1508AS on the Atmel CPLD Development/Programmer Board.

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15. Click on the Run button in the ATMISP main window to execute the JTAG instruction to program the ATF1508AS on the CPLD Development/Programmer Board.

(13) Select LPT Port Number

(14) Select Cable Type

(15) Click on the RUN Button

After successfully programming the ATF1508AS with the LOGIC_D8.JED file, the eight 8-segment LED's will display the words "Logic Doubling". If these two text messages are correctly displayed on the CPLD Development/Programmer Board, then the user has successfully completed this tutorial.

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Section 4 Schematic Diagrams

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DOT1

DOT2

DOT3

DOT4

DOT5

DOT6

DOT7

Figure 4-1. Schematic Diagram of the Atmel CPLD Development/Programmer Board

VCC GCLK1 GCLK1 D4G D4F D4A D4B D3G D3F D3A D3B D3B TK C D2G D2F D2A D2B D1G D1F D1F D1A D1A D1B GND 1 3 5 7 9 11 11 13 15 17 19 21 23 25 25 27 27 29 31 33 35 37 39 RDOT1 RDOT2 RDOT3 RDOT4 RDOT5
VCC

2 4 6 8 10 10 12 12 14 16 18 20 22 24 26 26 28 28 30 32 34 36 38 40 DSP1 DSP2 DSP3 DSP4 DSP5 DSP6 DOT DOT DOT DOT DOT DOT Vc1 Vc2 Vc1 Vc2 Vc1 Vc2 Vc1 Vc2 Vc1 Vc2 Vc1 Vc2 a f g c d a b c d e f g a b c d e f g a b c d e f g a b c d e f g d d d e c e c e c g g g e b f f f b b b f e d a b c d e f g a a a a g b c a f e d a b c d e f g g b c

GND GCLK2 GCLK2 D4D D4E D4C DOT4 TDO D3E D3D D3C D3C DOT3 D2E D2D D2C DOT2 D1E D1D D1D D1C D1C DOT1 VCC

RDOT6

RDOT7

DOT8

JPRIGHT

RDOT8

DSP7

DSP8

a f e d g b c

a f e d a b c d e f g g b c

RDSP11

RDSP13

RDSP15

RDSP17

RDSP21

RDSP23

RDSP25

RDSP27

RDSP31

RDSP33

RDSP35

RDSP37

RDSP41

RDSP43

RDSP45

RDSP47

RDSP51

RDSP53

RDSP55

RDSP57

RDSP61

RDSP63

RDSP65

RDSP67

RDSP71

RDSP73

RDSP75

RDSP77

RDSP81

RDSP83

RDSP85

JPLEFT VCC GOE D5B D5A D5F D5G D5G DOT6 D6B D6A D6F D6G D7B D7A D7F D7F D7G D8B D8A D8F D8G GND 1 3 5 7 9 11 13 15 17 17 19 19 21 23 25 27 29 31 33 33 35 35 37 39 RDSP12 RDSP14 RDSP16 RDSP22 RDSP24 RDSP26 RDSP32 RDSP34 RDSP36 D1A D1B D1C D1D D1E D1F D1G D2A D2B D2C D2D D2E D2F D2G HEADER 20X2 HEADER 20X2 VR1 LM317 3 Vin Vin ADJ +Vout +Vout 2 VCC 2 4 6 8 10 12 14 16 18 18 20 20 22 24 26 28 30 32 34 34 36 36 38 40 GND GCLR DOT5 D5C D5D D5E D5E TDI D6C D6D D6E TMS DOT7 D7C D7D D7D D7E DOT8 D8C D8D D8E VCC

RDSP42

RDSP44

RDSP46

RDSP52

RDSP54

RDSP56

RDSP62

RDSP64

RDSP66

RDSP72

RDSP74

RDSP76

RDSP82

RDSP84

D3A D3B D3C D3D D3E D3F D3G

D4A D4B D4C D4D D4E D4F D4G

D5A D5B D5C D5D D5E D5F D5G

D6A D6B D6C D6D D6E D6F D6G

D7A D7B D7C D7D D7E D7F D7G

D8A D8B D8C D8D D8E D8F D8G

RDSP86

RDSP87

a b c d e f g

HEADER 20X2

VCC

JPCLK

GCLK2

1 2 3

GCLK1

R7 4.7K

R8 4.7K

R 9 10K

R10 4.7K JTAG

TCK TDO TMS

R5 1K 1 3 5 7 9 2 4 6 8 10
GCLR GCLR

R6 1K
GOE GOE

R11 1K

R12 1K

JP JP JP Power JP Power 1 1 2 3 4

R1 200

C3 0.1

TDI

R4 1K 6 4 2 6 4 2 GCLR GOE1

OSC OSC

2 5 3 1 5 3 1

2MHZ D1 POWER SWITCH R2 330 LED1 VCC VCC

9 JPower V

1N4001 C1 100uF C 2 0.1uF 0.1uF R3 270

5.0V

C5 0.1uF 3 2 1

C6 0.1uF

C7 0.1uF

3.3V

Vcc Select

Schematic Diagrams

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DOT DOT Vc1 Vc2 Vc1 Vc2

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Schematic Diagrams

JPLEFT VCC GOE D5B D5A D5F D5G D6B D6A D6F D6G 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND GCLR D5C D5D D5E TDI D6C D6D D6E TMS

6 5 4 3 2 1 44 43 42 41 40

P2 P1 P44 P43

P6 P5 P4

P41 P40

D5A D5C D5B VCC GCLK2 GCLR GOE GCLK1 GND D4G D4D

U1 TDI D5D D5F GND D5E D5G TMS D6C VCC D6B D6D I/O I/O I/O VCC I/OE2/GCLK2 GCLR OE1 GCLK1 GND GCLK3 I/O P8 P9 P11 P12 P14 P16 P17 7 8 9 10 11 12 13 14 15 16 17 TDI I/O I/O GND I/O I/O TMS I/O VCC I/O I/O I/O TDO I/O I/O VCC I/O I/O TCK I/O GND I/O 39 38 37 36 35 34 33 32 31 30 29 PLCC44 18 19 20 21 22 23 24 25 26 27 28 P39 P37 P36 P34 P33 P31 P29 D4F TDO D4E D4A VCC D4C D4B TCK D3G GND D3F

Figure 4-2. Schematic Diagram of 44-pin PLCC Socket Adapter Board

GND

VCC

ATMEL PLCC44

HEADER 20X2 JPRIGHT VCC GCLK1 D4G D4F D4A D4B D3G D3F D3A D3B TCK 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND GCLK2 D4D D4E D4C TDO D3E D3D D3C

I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O

VCC

c1 0.1uF

c2 0.1uF

c3 0.1uF

c4 0.1uF

GND

VCC

HEADER 20X2

CPLD Development/Programmer Kit User Guide

P18 P19 P20 P21

D6A D6E D6F D6G GND VCC D3C D3D D3B D3E D3A

P24 P25 P26 P27 P28

3300APLD08/02

4-3

JPLEFT VCC GOE D5B D5A D5F D5G D6B D6A D6F D6G 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 JPRIGHT VCC GCLK1 D4G D4F D4A D4B D3G D3F D3A D3B TCK 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND GCLK2 D4D D4E D4C TDO D3E D3D D3C 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND GCLR D5C D5D D5E TDI D6C D6D D6E TMS TDI D5D D5F GND D5E D5G TMS D6C VCC D6B D6D 1 2 3 4 5 6 7 8 9 10 11

U1 I/O I/O I/O VCC I/OE2/GCLK2 GCLR OE1 GCLK1 GND GCLK3 I/O P2 P3 P5 P6 P8 P10 P11 TDI I/O I/O GND I/O I/O TMS I/O VCC I/O I/O I/O TDO I/O I/O VCC I/O I/O TCK I/O GND I/O 33 32 31 30 29 28 27 26 25 24 23 TQFP44 12 13 14 15 16 17 18 19 20 21 22 P33 P31 P30 P28 P27 P25 P23 D4F TDO D4E D4A VCC D4C D4B TCK D3G GND D3F

Figure 4-3. Schematic Diagram of 44-pin TQFP Socket Adapter Board

GND

VCC

ATMEL TQFP44

HEADER 20X2

P12 P13 P14 P15

VCC

c1 0.1uF

c2 0.1uF

c3 0.1uF

c4 0.1uF

Schematic Diagrams

GND

VCC

HEADER 20X2
3300APLD08/02

D6A D6E D6F D6G GND VCC D3C D3B D3D D3A D3E

P18 P19 P20 P21 P22

I/O I/O I/O I/O GND VCC I/O I/O I/O I/O I/O

4-4

CPLD Development/Programmer Kit User Guide

P44 P43 P42

44 43 42 41 40 39 38 37 36 35 34

P40 P39 P38 P37

P35 P34

D5A D5C D5B VCC GCLK2 GCLR GOE GCLK1 GND D4G D4D

Schematic Diagrams

D5D D5F D5C GND D5A D5B VCC GCLK2 GCLR GOE GCLK1 GND

D4G VCC

JPLEFT VCC GOE D5B D5A D5F D5G D6B D6A D6F D6G D7B D7A D7F D7G 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND GCLR

P2 P1 P68 P67

P65 P64

D7C D7D D7E

Figure 4-4. Schematic Diagram of 68-pin PLCC Socket Adapter Board

GND

VCC

HEADER 20X2 JPRIGHT VCC GCLK1 D4G D4F D4A D4B D3G D3F D3A D3B TCK D2G D2F D2A D2B 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND GCLK2 D4D D4E D4C TDO D3E D3D D3C D2E D2D D2C c1 0.1uF c2 0.1uF

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

I/O I/O I/O I/O VCC I/O I/O GND VCC I/O I/O GND I/O I/O I/O I/O VCC

D5G VCC TDI D5E D6B D6C GND D6A D6D TMS D6F VCC D6E D6G D7B D7A GND

I/O I/O I/O GND I/O I/O VCC GCLK2 GCLR OE1 GCLK1 GND GCLK3 I/O VCC TCK I/O

D5C D5D D5E TDI D6C D6D D6E TMS

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

P62 P61

P9 P8 P7

P5 P4

D4D

U1 P10 P13 P14 P15 P17 P18 P20 P22 P23 P24 P25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 I/O VCC TDI I/O I/O I/O GND I/O I/O TMS I/O VCC I/O I/O I/O I/O GND I/O I/O GND TDO I/O I/O I/O VCC I/O I/O TCK I/O GND I/O I/O I/O I/O 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 P60 P59 P56 P55 P54 P52 P51 P49 P47 P46 P45 P44 D4F D4E GND TDO D4A D4C D4B VCC D3G D3F TK C D3E GND D3A D3D D3B D3C

ATMEL PLCC68

P27 P28 P29 P30

P32 P33

P36 P37

c3 0.1uF

c4 0.1uF

GND

VCC

HEADER 20X2

D7C D7F D7D D7G VCC D7E D2B GND VCC D2C D2A GND D2D D2F D2E D2G VCC

P39 P40 P41 P42

VCC

CPLD Development/Programmer Kit User Guide

3300APLD08/02

4-5

JPRIGHT MARK SMALLATMEL PIN83 PIN81 PIN79 PIN76 PIN74 PIN73 PIN69 PIN67 PIN64 PIN63 PIN60 PIN57 PIN55 PIN54 PIN51 PIN49 PIN46 JR1 JR3 JR5 JR7 JR9 JR11 JR12 JR14 JR15 JR18 JR20 JR23 JR25 JR27 JR29 JR31 JR33 VCC GCLK1 D4G D4F D4A D4B D3G D3F D3A D3B TCK D2G D2F D2A D2B D1G D1F D1A D1B GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 HEADER 20X2 JPLEFT PIN84 PIN4 PIN6 PIN9 PIN11 PIN44 PIN12 PIN16 PIN18 PIN21 PIN22 PIN25 PIN28 PIN30 PIN31 PIN34 PIN36 PIN39 JL1 JL3 JL5 JL7 JL9 JL11 JL12 JL14 JL16 JL18 JL19 JL21 JL23 JL25 JL27 JL29 JL31 JL33 VCC GOE D5B D5A D5F D5G DOT6 D6B D6A D6F D6G D7B D7A D7F D7G D8B D8A D8F D8G GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND GCLR DOT5 D5C D5D D5E TDI D6C D6D D6E TMS DOT7 D7C D7D D7E DOT8 D8C D8D D8E VCC JL2 JL4 JL6 JL8 JL10 JL13 JL15 JL17 JL20 JL22 JL24 JL26 JL28 JL30 JL32 JL34 PIN1 PIN45 PIN5 PIN8 PIN10 PIN15 PIN17 PIN20 PIN41 PIN24 PIN27 PIN29 PIN40 PIN33 PIN35 PIN37 GND GCLK2 D4D D4E D4C TDO D3E D3D D3C D2E D2D D2C D1E D1D D1C VCC PIN11 PIN10 PIN9 PIN8 GND PIN6 PIN5 PIN4 VCC PIN2 PIN1 PIN84 PIN83 GND PIN81 PIN80 PIN79 VCC PIN77 PIN76 PIN75 JR2 JR4 JR6 JR8 JR10 JR13 JR16 JR17 JR19 JR21 JR22 JR24 JR26 JR28 JR30 JR32 JR34 PIN2 PIN77 PIN80 PIN75 PIN70 PIN68 PIN65 PIN61 PIN58 PIN56 PIN52 PIN50 PIN48

U1 PIN12 VCC TDI PIN15 PIN16 PIN17 PIN18 GND PIN20 PIN21 PIN22 TMS PIN24 PIN25 VCC PIN27 PIN28 PIN29 PIN30 PIN31 GND 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I/O I/O I/O I/O GND I/O I/O I/O VCC_INT INPUT/OE2/GCLK2 INPUT/GCLRn INPUT/OE1 INPUT/GCLK1 GND I/O I/O I/O VCC_IO I/O I/O I/O 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 PIN74 PIN73 GND TDO PIN70 PIN69 PIN68 PIN67 VCC PIN65 PIN64 PIN63 TCK PIN61 PIN60 GND PIN58 PIN57 PIN56 PIN55 PIN54 VCC

Figure 4-5. Schematic Diagram of 84-pin PLCC Socket Adapter Board

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

I/O I/O I/O I/O I/O VCC_IO I/O I/O I/O GND VCC_INT I/O I/O I/O GND I/O I/O I/O I/O I/O VCC_IO

I/O VCC_IO I/O / TDI I/O I/O I/O I/O GND I/O I/O I/O I/O / TMS I/O I/O VCC_IO I/O I/O I/O I/O I/O GND

ATMEL ATF1508AS-15JC84

I/O I/O GND I/O / TDO I/O I/O I/O I/O VCC_IO I/O I/O I/O I/O / TCK I/O I/O GND I/O I/O I/O I/O I/O

PIN33 PIN34 PIN35 PIN36 PIN37 VCC PIN39 PIN40 PIN41 GND VCC PIN44 PIN45 PIN46 GND PIN48 PIN49 PIN50 PIN51 PIN52 VCC

c1 0.1uF

c2 0.1uF

c3 0.1uF

c4 0.1uF

HEADER 20X2

Schematic Diagrams

CPLD Development/Programmer Kit User Guide

3300APLD08/02

11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

4-6

Schematic Diagrams

D5F D5D D5A GND D5C D5B DOT5 VCC GCLK2 GCLR GOE GCLK1 GND D4G D4D D4F VCC D4E D4A D4C

JPLEFT VCC GOE D5B D5A D5F D5G DOT6 D6B D6A D6F D6G D7B D7A D7F D7G D8B D8A D8F D8G GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND GCLR DOT5 D5C D5D D5E TDI D6C D6D D6E TMS DOT7 D7C D7D D7E DOT8 D8C D8D D8E VCC

P100 P99 P98

P96 P95 P94

P92 P91 P90 P89

P87 P86 P85

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

P83 P82 P81

U1 P1 P2 P3 P4 P7 P8 P9 P10 P11 P12 P14 P15 P16 P18 P19 P21 P22 P23 P24 P25 P26 P27 P29 P30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 I/O I/O I/O GND I/O I/O I/O VCCINT GCLK2 GCLR OE1 GCLK1 GND I/O/GCLK3 I/O I/O VCCIO I/O I/O I/O I/On I/On I/O I/O VCCIO TDI I/On I/O I/On I/O I/O I/O GND I/O I/O I/O TMS I/O I/O VCCIO I/O I/O I/O I/On I/O I/On I/O GND I/On I/On I/On I/On I/O I/O GND TDO I/On I/O I/On I/O I/O I/O VCCIO I/O I/O I/O TCK I/O I/O GND I/O I/O I/O I/On I/O I/On I/O VCCIO I/On I/On 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P80 P79 P78 P77 P74 P73 P72 P71 P70 P69 P67 P66 P65 P63 P62 P60 P59 P58 P57 P56 P55 P54 P52 P51

D5E D5G VCC TDI DOT6

D4B DOT4 GND TDO D3G D3F D3E D3A VCC D3D D3B D3C TCK DOT3 D2G GND D2E D2F D2D D2A D2B VCC DOT2 DOT1

Figure 4-6. Schematic Diagram of 100-pin PQFP Socket Adapter Board

D7E GND DOT8

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

VCC

HEADER 20X2

c1 0.1uF

c2 0.1uF

c3 0.1uF

c4 0.1uF

CPLD Development/Programmer Kit User Guide

D6C D6B D6D GND D6A D6E D6F TMS D6G D7B VCC D7C D7A D7D DOT7 D7F

HEADER 20X2 JPRIGHT VCC GCLK1 D4G D4F D4A D4B D3G D3F D3A D3B TCK D2G D2F D2A D2B D1G D1F D1A D1B GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND GCLK2 D4D D4E D4C DOT4 TDO D3E D3D D3C DOT3 D2E D2D D2C DOT2 D1E D1D D1C DOT1 VCC

ATMEL PQFP100

P31 P32 P33 P34 P35

P37 P38 P39

P42 P43 P44

D8E D8G D8D D8F D8C VCC D8A D8B D7G GND VCC D2C D1G D1E GND D1F D1D D1A D1C D1B

P46 P47 P48 P49 P50

I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O I/O GND I/O I/O I/O I/O I/O

3300APLD08/02

4-7

P94 P93 P92

P90 P89 P88 P87

P85 P84 P83

Figure 4-7. Schematic Diagram of 100-pin TQFP Socket Adapter Board

VCC GOE D5B D5A D5F D5G DOT6 D6B D6A D6F D6G D7B D7A D7F D7G D8B D8A D8F D8G GND

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

GND GCLR DOT5 D5C D5D D5E TDI D6C D6D D6E TMS DOT7 D7C D7D D7E DOT8 D8C D8D D8E VCC

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

P81 P80 P79 P78 P77 P76

JPLEFT

U1 P1 P2 P5 P6 P7 P8 P9 P10 P12 P13 P14 P16 P17 P19 P20 P21 P22 P23 P24 P25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 I/O I/O I/O I/O I/O GND I/O I/O I/O VCCINT GCLK2 GCLR OE1 GCLK1 GND I/O GCLK3 I/O I/O VCCIO I/O I/O I/On I/O I/On I/O I/On I/On VCCIO TDI I/On I/O I/On I/O I/O I/O GND I/O I/O I/O TMS I/O I/O VCCIO I/O I/O I/O I/On I/O I/On I/O I/O GND TDO I/On I/O I/On I/O I/O I/O VCCIO I/O I/O I/O TCK I/O I/O GND I/O I/O I/O I/On I/O I/On I/O VCCIO 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 TQFP100 VCC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P75 P72 P71 P70 P69 P68 P67 P65 P64 P63 P61 P60 P58 P57 P56 P55 P54 P53 P52 DOT4 GND TDO D3G D3F D3E D3A VCC D3D D3B D3C TCK DOT3 D2G GND D2E D2F D2D DOT2 D2A D1B VCC

VCC TDI DOT6 D6C D6B D6D GND D6A D6E D6F TMS D6G D7B VCC D7C D7A D7D DOT7 D7F D7E

ATMEL TQFP100

HEADER 20X2 JPRIGHT VCC GCLK1 D4G D4F D4A D4B D3G D3F D3A D3B TCK D2G D2F D2A D2B D1G D1F D1A D1B GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 GND GCLK2 D4D D4E D4C DOT4 TDO D3E D3D D3C DOT3 D2E D2D D2C DOT2 D1E D1D D1C DOT1 VCC

P27 P28 P29 P30 P31 P32 P33

P35 P36 P37

P40 P41 P42

c1 0.1uF

c2 0.1uF

c3 0.1uF

c4 0.1uF DOT8 D7G D8B D8C D8A D8D VCC D8F D8E D8G GND VCC D2C D2B D1G GND D1E D1F D1D D1A D1C DOT1 GND

Schematic Diagrams

HEADER 20X2

P44 P45 P46 P47 P48 P49 P50

GND I/On I/On I/O I/O I/O I/O I/O VCCIO I/O I/O I/O GND VCCINT I/O I/O I/O GND I/O I/O I/O I/O I/O I/On I/On

CPLD Development/Programmer Kit User Guide

3300APLD08/02

D5G D5E D5F D5D D5A GND D5C D5B DOT5 VCC GCLK2 GCLR GOE GCLK1 GND D4G D4D D4F VCC D4E D4A

D4C

P100 P99 P98 P97 P96

D4B

4-8

Schematic Diagrams

JPLEFT VCC GOE D5B D5A D5F D5G DOT6 D6B D6A D6F D6G D7B D7A D7F D7G D8B D8A D8F D8G GND P107 P106 D3G D3E GND TDO P102 P101 P100 P99 P98 P97 P96 P94 P93 P92 P91 P88 P87 P86 P84 P83 P82 P81 P80 P79 P78 P77 P74 D3F D3D D3A D3C D3B DOT3 VCC D2G D2E D2F D2D TCK D2A D2C D2B GND DOT2 D1G D1E D1F D1D D1A D1B DOT1 VCC ATMEL TQFP144 D1C VCC TQFP144 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

U1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 I/O I/O I/O I/O I/O I/O I/On I/O I/O I/On I/On I/On I/On VCCIO VCCINT GND I/O I/O I/O I/O GND VCCINT GND I/O I/O I/O I/O GND I/O I/On I/O I/O I/O I/O I/O I/O I/On I/On GND TDI I/O I/O I/O I/O I/O I/O I/O I/On GND I/O I/O I/O GND I/O I/On TMS I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O I/O GND I/On I/On I/On I/On I/O I/O GND TDO I/On I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/On TK C I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O I/O VCCIO I/On I/O VCCIO VCCIO I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCINT GND GCLK2 GCLR GOE GCLK GND VCINT I/On I/On I/On I/O I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73

Figure 4-8. Schematic Diagram of 144-pin TQFP Socket Adapter Board

GND TDI DOT6 D6C D6B D6D D6A D6E D6F P5 P6 P7 P8 P9 P10 P11 P14 P15 P16 P18 P21 P22 P23 P25 P26 P27 P28 P29 P30 P31 P32 GND D6G GND TMS DOT7 D7B D7C VCC D7A D7D D7F D7E D7G DOT8 D8B D8C GND

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

GND GCLR DOT5 D5C D5D D5E TDI D6C D6D D6E TMS DOT7 D7C D7D D7E DOT8 D8C D8D D8E VCC

DOT5 D5E D5B D5C GND D5A D5D D5F D5G VCC GND GCLK2 GCLR GOE GCLK1 GND VCC

P143 P142 P141 P140 P139 P138 P137 P136

P134 P133 P132 P131

P128 P127 P126 P125

P119

P118 P117 P116

144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109

P114 P113 P112 P111 P110 P109

D4B D4A D4C D4F VCC D4D D4G D4E DOT4

VCC

HEADER 20X2

JPRIGHT VCC GCLK1 D4G D4F D4A D4B D3G D3F D3A D3B TCK D2G D2F D2A D2B D1G D1F D1A D1B GND

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

GND GCLK2 D4D D4E D4C DOT4 TDO D3E D3D D3C DOT3 D2E D2D D2C DOT2 D1E D1D D1C DOT1 VCC

VCC

c1 0.1uF P44 P45 P53 P54 P55 P56 P60 P61 P62 P63 P65 P67 P68 P69 P70 P71 P72

c2 0.1uF

c3 0.1uF

c4 0.1uF

CPLD Development/Programmer Kit User Guide

P37 P38 P39 P40 P41 P42 GND VCC GND VCC VCC GND GND D8E D8D D8G D8F D8A

HEADER 20X2

3300APLD08/02

4-9

U1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O GND I/O NC NC NC NC I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O GND VCCINT I/O I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O NC NC NC NC I/O VCCIO I/O NC NC NC NC NC NC NC VCCIO TDI I/O I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O TMS I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC NC NC ATMEL PQFP160 NC NC NC NC NC NC NC GND TDO I/O I/O I/O I/O I/O I/O I/O VCCIO I/O I/O I/O I/O TCK I/O I/O I/O GND I/O I/O I/O I/O I/O I/O I/O NC NC NC NC NC NC NC I/O I/O I/O NC NC NC NC I/O I/O I/O I/O I/O GND I/O I/O I/O I/O VCCINT GCLK2 GCLR OE1 GCLK1 GND I/O/GCLK3 I/O I/O I/O VCCIO I/O I/O I/O I/O I/O NC NC NC NC I/O I/O I/O 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

VCC GOE D5B D5A D5F D5G DOT6 D6B D6A D6F D6G D7B D7A D7F D7G D8B D8A D8F D8G GND GND TDO D4E D4A D4C D4B DOT4 D3G D3F VCC D3E D3A D3D D3B TCK D3C DOT3 D2G GND D2E D2F D2D D1A D1C D1B DOT1 P111 P110 P109 P108 P107 P106 P105 P103 P102 P101 P100 P98 P97 P96 P94 P93 P92 P91 P90 P89 P88

JPLEFT 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

GND GCLR DOT5 D5C D5D D5E TDI D6C D6D D6E TMS DOT7 D7C D7D D7E DOT8 D8C D8D D8E VCC

Figure 4-9. Schematic Diagram of 160-pin PQFP Socket Adapter Board

VCC TDI D5D D5A D5E D5F D5G DOT6 D6C GND D6B D6D D6A D6E TMS D6F D6G DOT7 VCC D7B D7C D7A D8C D8D D8E D8G P10 P11 P12 P13 P14 P15 P16 P18 P19 P20 P21 P23 P24 P25 P27 P28 P29 P30 P31 P32 P33

HEADER 20X2 JPRIGHT VCC GCLK1 D4G D4F D4A D4B D3G D3F D3A D3B TCK D2G D2F D2A D2B D1G D1F D1A D1B GND 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

GND GCLK2 D4D D4E D4C DOT4 TDO D3E D3D D3C DOT3 D2E D2D D2C DOT2 D1E D1D D1C DOT1 VCC

HEADER 20X2

VCC

c1 0.1uF

c2 0.1uF

c3 0.1uF

c4 0.1uF

P41

P43

P48 P49 P50 P51 P52 P53 P54

P56 P57 P58 P59

P62 P63 P64 P65

P67 P68 P69 P70 P71 P72 P73

P78

DOT8 D8B D7E D7G D7D D7F

D2C D2A DOT2 D2B D1G D1E

D8F GND D8A

GND VCC

GND

Schematic Diagrams

D1F VCC D1D

VCC

P80

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

CPLD Development/Programmer Kit User Guide

VCC GCLK2 GCLR GOE GCLK1 GND

D5C D5B DOT5

GND

P160 P159 P158

P153 P152 P151 P150 P149

P147 P146 P145 P144

P142 P141 P140 P139

P137 P136 P135 P134

160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121

P132 P131 P130 P129 P128

P123 P122 P121

D4D D4G D4F

VCC

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Schematic Diagrams

Buffer/Line Driver

VCC D1 R16 100 TCK 1N4148 R26 4.7k R25 4.7k R24 4.7k R23 4.7k R22 4.7k R21 4.7k U1 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 1G 2G 74VHC244
20-SOIC

R17 100 AF R18 100 TDI 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 VCC GND 18 16 14 12 9 7 5 3 20 10 R19 100 INI R20 100 TMS VCC nACK BUSY

STROBE AUTO D0 INIT SEL_IN TDO D7

2 4 6 8 11 13 15 17 1 19

C1 0.1uF

Figure 4-10. Schematic Diagram of Atmel CPLD ISP Cable

GND GND

JP1 TCK TDO TMS TDI 1 3 5 7 9 2 4 6 8 10 R1 330ohm GND L1 LED

INI AF

HEADER 5X2

10 Pin Header to ISP Board

GND

CPLD Development/Programmer Kit User Guide

VCC

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Parallel Port Section

Voltage Detection

VCC R 2 R 3 P1 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 DB25 R 4 100 STROBE 100 AUTO 100 D0 ERROR R5 100 INIT SEL_IN R6 100 D3 R 7 R 8 R 9 100 D7 100
+ + 1.5V - 1.6V Vref

R12

10K

1.36V at VCC = 3.3 2.06V at VCC = 5.0

R13

4.7K

Figure 4-11. Schematic Diagram of Atmel CPLD ISP Cable, Continued

D2

1N4148

VCC 1N4148 R14 3.3K

D4

1N4148 4
8-SOP

VCC 8 U2B

nACK 100 BUSY VCC R10 R11 4.7K 4.7K GND

8 U2A R15 30K 1

4 LM393
8-SOP

LM393

ERROR
3V = 0 5V = 1

GND

GND

Schematic Diagrams

CPLD Development/Programmer Kit User Guide

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3300APLD08/02 /1M