WSS 2004 (Industrial Electronics) Finals Theory Paper

Question 1 Assume that the diodes are ideal and have a forward voltage drop of 0.7V, determine the current through diode D1 for the circuits below. +15V

2.2K

1.5K

1.0K

D1

0V

-15V

1k 1k 10V 5mA ZD1 3.3V D1

Question 1 Solution

Question 2 Design a 2-bit 2s complement number converter using the 2-4 decoder and 4-2 encoder whose function tables are given as follows. Functional Table of 2-4 Decoder Input A x 0 0 1 1 B x 0 1 0 1 Output Y0 Y1 Y2 Y3 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 1 1 1 1 0 Functional Table of 4-2 Encoder Input A0 A1 A2 0 1 1 1 0 1 1 1 0 1 1 1 A3 1 1 1 0 Output Y0 Y1 0 0 0 1 1 0 1 1

1 0 0 0 0

Question 2 Solution

Question 3 Design a 2nd Order Butterworth voltage controlled voltage source (VCVS) low-pass active filter that has a pass-band voltage gain of one and a cut-off frequency of 1 kHz. Sketch the gain amplitude versus frequency response of this filter. Let C = 0.47 F. Hence, determine the roll-off rate of the filter.

R1

R2

C1 R4 R3
Butterworth VCVS low pass filter Table 1 Circuit Element Values Gain 1 2 4 6 R1 1.422 1.126 0.824 0.617 R2 5.399 2.250 1.537 2.051 R3 Open 6.752 3.148 3.203 R4 0 6.752 9.444 16.012 C1 0.33C C 2C 2C Note: Resistances in k for scaling ratio (100 / fc C'), K=1. Question 3 Solution

8 0.521 2.429 3.372 23.602 2C

10 0.462 2.742 3.560 32.038 2C

Question 4 Put the following expression in sum-of-product (SOP) form. Verify with a truth table that the SOP expression you end with, is the same as the given expression.

[bd (a + c)] + a + a d

Question 4 Solution

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Question 5 The figure below shows a non-inverting clamper circuit. a) By means of Superposition Theorem, prove that the output voltage is:
Vo = Vref + 1 +
RF Vin R1

b)

Sketch the output waveform (for 1 cycle) if Vin is a 4 Vp-p sinewave of 1 kHz with zero dc offset voltage, and Vref is set to 1 Vdc. C1 R1=10k RF=10k

+VCC Ci +
+VCC

opamp RL

Vo

Vin

R3

VEE

R2

Vref 1V VEE

R4 10 k

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Question 5 Solution

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Question 6 6 a) Based on the memory chip and the 3-to-8 Decoder ICs given below, design a memory module with a capacity of 2 K x 8. Draw the complete circuit diagram and label all bus lines clearly. 3-To-8 Decoder S2 S1 S0 EN0 EN1 Y0 : : : Memory Chip A0 : : : A8 R/W CS I/O0 : : : I /O7

Y7

6 b)

Explain what will happen when the Chip-Select pin of one of the many memory chips is accidentally shorted to ground.

Question 6 Solution

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Question 7 Assuming ideal op amps, determine the output voltage Vo for each circuit in below. a)

Figure 1A

b)

Figure 1B

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Question 7 Solution

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Question 8 Figure 2 shows the intersection of two roads. Vehicle-detection sensors are placed along lanes A, B, C and D. The sensor outputs are LOW (0) when no vehicle is present, and HIGH (1) when a vehicle is present. The intersection traffic light is controlled as follow: i) ii) iii) iv) v) The E-W traffic light will be green whenever both lanes C and D are occupied. The E-W light will be green whenever either C or D is occupied but lanes A and B are not both occupied. The N-S light will be green whenever both lanes A and B are occupied but C and D are not both occupied. The N-S light will also be green when either lane A or B is occupied while C and D are both vacant. The E-W light will be green when no vehicles are present.

Using the sensor outputs A, B, C and D as inputs, design a logic circuit to control the traffic light. There should be 2 outputs, N-S and E-W, which become 1 when the corresponding light is to be green.

Figure 2

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Question 8 Solution

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Question 9 A 10 bits digital ramp ADC is operating at the clock rate of 1MHz, and the full scale output is equal to 10.23 V. a. Determine the step size and the resolution of this ADC converter. b. Determine the digital equivalent value of an analogue input of 3.728 V. c. Determine the conversion time required for converting the analogue 3.728 V to it digital equivalent value. d. Determine the average conversion time of this ADC.

Question 9 Solution

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Question 10 A 4 input CMOS domino AND logic gate with inputs A, B, C and D is designed as shown.

5V
Pre-charge Evaluate Evaluate

Vdd (+5V) Vout

Output CL

A B C D

Vx

Time (t)

Cp

The Inputs are normally held low during the period of Pre-charge. During the evaluate cycle, input A is at logic High and input B, C and D are at logic Low. The Output node drives an inverter with a switching threshold (VTn) of 2.8V. CP is the capacitance at the source-drain node of the series pull-down network and CL is the capacitance at the intermediate Output node of the logic gate. Calculate the maximum ratio of CP / CL required to ensure that charge sharing will not corrupt the final output value.

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Question 10 Solution

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