DESIGNING OF INFINITE IMPULSE RESPONSE DIGITAL FILTER BASED ON FPGA

Mariza Wijayanti, Sunny Arief Sudiro Electrical Engineering, Gunadarma university mariza@student.gunadarma.ac.id, sunny@staff.gunadarma.ac.id

AbstractThe Innite Impulse Response (IIR) lter is a property of signal processing systems. IIR systems have an impulse response function that is non-zero over an innite length of time. FieldProgrammable gate Array (FPGA) has become an extremely costeffective means of off-loading computationally intensive digital signal processing algorithms to improve overall system performance. The IIR lter implementation in FPGA, utilizing the dedicated hardware resources can effectively achieve application-specic integrated circuit (ASIC). In this thesis, The design start by specifying the lter specications, then perform mathematical calculations a lowpass, band-pass and high-pass IIR lter, simulated the design calculation results by using MATLAB and the nally is implemented in FPGA. Direct-form approach in realizing a digital lter is considered. The IIR lter is implemented in Spartan-IIIxc3s500c- 4fg320 FPGA and simulated with the help of Xilinx ISE 9.2i was used for synthesizing and simulation the code. Codes for direct form xed point IIR lter have been realized. Modules used such as multiplier, adder, and delay. Data simulation results compared with output Matlab program. Based on the test results of the comparison lter circuit, an error occurs due to the use Divider components that make the process of division by the result of rounding. KeywordsFilter, IIR, FPGA, Xilinx-Ise 9.2i, Matlab

I. I NTRODUCTION

N signal processing, the function of a lter is to remove unwanted parts of the signal, such as random noise, or to extract useful parts of the signal, such as the components lying within a certain frequency range [3].

Fig. 1: A block diagram of a basic lter[3] There are two types of lter which are analog and digital. IIR Filter is the kind of digital lter, which can be used to perform all kinds of ltering i.e. high-pass, low-pass, bandpass and band-reject [14]. A digital lter uses a digital processor to perform numerical calculations on sampled values of the signal. The processor may be a general-purpose computer such as a PC, or a specialized DSP (Digital Signal Processor) chip. Advantages: A digital lter is programmable, Digital lters are easily designed, tested and implemented on computer or workstation,

Digital lters are extremely stable with respect both to time and temperature, Digital lters can handle low frequency signals accurately, Digital lters are very much versatile. There are two basic types of digital lters, Finite Impulse Response (FIR) and Innite Impulse Response (IIR) lters. Design of digital IIR lters is heavily dependent on that of their analog counterparts because there are plenty of resources, works and straight forward design methods concerning analog feedback lter design while there are hardly any for digital IIR lters. As a result, usually, when a digital IIR lter is going to be implemented, an analog lter (e.g. Chebyshev lter, Butterworth lter, Elliptic lter) is rst designed and then is converted to a digital lter by applying discretization techniques such as Bilinear transform or Impulse invariance. FPGA arrived in 1984 as an alternative to programable logic devices(PLDs) and ASICs. FPGA offers the signicant benits of being readily programable. FPGA can be programmed again and again, giving designers multiple opportunities to tweak ther circiuts. FPGA consists of an array of logic blocks that are congured using software. Programable input/output blocks surround these logic blocks. Both are connected by programable interconnects. Today , however, FPGA offers millions of gates of logic capacity, operate at 300 MHz, and offer integrated functions like processors and memory. FPGA offers all of the features needed to implement most complex designs. Clock management is facilitated by on-chip PLL(phase-locked loop) or DLL(delay-locked loop) circuitry. Dedicated memory blocks can be congured as basic single-port RAMs, ROMs, FIFOs, or CAMs. Now a days FPGAs are system building resources such as high-speed serial input/output, arithmetic modules, embedded processors, and large amount of memory. Electronic circuit are built through several stages such as design,simulate, assembly, and testing. The design done with recognizes the need and usefulness of the circuit. Simulation at the time of the design needed to minimize the error rate when the circuit carried out in assembly, so it can reduce the cost of failure of the electronics circuit that designed and built. Now the problem is How to design a digital IIR lter Chebyshev using the bilinear transform and How the Filter was designed and simulated using Xilinx ISE 9.2i.

II. THEORETICAL FRAMEWORK IIR has Impulse response, h(n), with an innite number of samples.

IIR lter input-output equation :

(1) The advantages of IIR lter : Produce an equivalent magnitude response using a much lower lter order. Easier to design Less Delay The disadvantages of IIR lter : Difcult to get ideal linear phase characteristic. Difcult to get a stable system for lter A. Chebyshev Chebyshev lters are analog or digital lters having a steeper roll-off and more passband ripple (type I) or stopband ripple (type II) than Butterworth lters. Chebyshev lters have the property that they minimize the error between the idealized lter characteristic and the actual over the range of the lter, but with ripples in the passband. This type of lter is named in honor of Pafnuty Chebyshev because their mathematical characteristics are derived from Chebyshev polynomials. Because of the passband ripple inherent in Chebyshev lters, lters which have a smoother response in the passband but a more irregular response in the stopband are preferred for some applications[25]. To nd order in Chebyshev, used the following equation:

Fig. 3: Chebyshev Type 2 Lowpass Filter[25]

B. Forms of Direct Realization

Direct Realization can be cited in mathematical equation below:

a0 x(n ) + a1 x(n 1) + a2 x(n 2 ) + ... + ak x(n k )

y (n ) + b1 y (n 1) + b2 y (n 2 ) + ... + bk y (n k ) =

(1 + b1 z 1 + b2 z 2 + ... + bk z k ) Y (z ) = (a0 + a1 z 1 + a2 z 2 + ... + ak z k ) X (z )

(4)

H (z ) =
(2)

a + a1 z 1 + a2 z 2 + ... + ak z k Y (z ) = 0 X (z ) 1 + b1 z 1 + b2 z 2 + ... + bk z k

(3)

H (z ) =

1+

i=0 k

ai
k j =1

zi zi

bj

1) Direct Form I: A straightforward approach for IIR lter realization is Direct Form I, where the difference equation is evaluated directly. This form is practical for small lters, but may be inefcient and impractical (numerically unstable) for complex designs [17]. In general, this form requires 2N delay elements (for both input and output signals) for a lter of order N. Fig. 2: Chebyshev Type 1 Lowpass Filter[25] Direct Form I realization can be cited in mathematical equation:

y (n ) = a0 x(n ) + a1 x(n 1) + a 2 x(n 2 ) + ... + a k x(n k ) [b1 y (n 1) + b2 y (n 2 ) + ... + bk y (n k ) ]

k k

equation:

Y (z ) = H (z ) . X (z ) H (z ) =
(5)

y (n ) = ai x(n i ) a j y (n j )
i =0 j =1

N (z ) D(z ) N (z ) X (z ) . X (z ) = . N (z ) D(z ) D(z ) X (z ) D(z )

From this equation, we can built a diagram as shown as equation (5)

Y (z ) =

W (z ) =

Y (z ) = N (z ) . W (z ) W (z ) =
Fig. 4: Realization of Direct Form I[17]

X (z ) X (z ) = 1 D( z ) 1 + b1 z + ... + bk z k

(6)

(1 + b z
1

+ ... + bk z k W ( z ) = X ( z )

w(n ) + b1 w(n 1) + ... + bk w(n k ) = x(n ) w(n ) = x(n ) b1 w(n 1) ... bk w(n k ) w(n ) = x(n )
Fig. 5: Schematic Diagram IIR lter [13]

b w(n j )
k j =1 i

Y ( z ) = N ( z ) . W (z )

2) Direct Form II: The alternate Direct Form II only needs N delay units, where N is the order of the lter, potentially half as much as Direct Form I. This structure is obtained by reversing the order of the numerator and denominator sections of Direct Form I, since they are in fact two linear systems, and the commutativity property applies. Then, one will notice that there are two columns of delays (z 1 ) that tap off the center net, and these can be combined since they are redundant, yielding the implementation as shown below. The disadvantage is that Direct Form II increases the possibility of arithmetic overow for lters of high Q or resonance [14]. It has been shown that as Q increases, the round-off noise of both direct form topologies increases without bounds.This is because, conceptually, the signal is rst passed through an all-pole lter (which normally boosts gain at the resonant frequencies) before the result of that is saturated, then passed through an all-zero lter (which often attenuates much of what the all-pole half amplies). Direct Form II realization can be cited in mathematical

Y ( z ) = ao + a1 z 1 + ... + ak z k . W ( z ) y (n ) = ao w(n ) + a1 w(n 1) + ... + ak w(n k ) y (n ) =

a w(n i )
k i =0 i

From this equation, we can built a diagram as shown as equation (6)

here, partially factored forms of these polynomials have been calculated and tabulated. The polynomials are given in the basic form required for constructing the low-pass transfer function. The general form for the low-pass transfer functions in the table is

(7) Fig. 6: Realization of Direct Form II[14] The denominator coefcients of equation (7) are tabulated in the table I for the Butterworth function and Chebyshev functions for four possible values of passband ripple (0.5 dB, 1 dB, 2 dB, and 3 dB). The orders of the lters used are form k = 1 through k = 5. If unity gain at dc is desired, the numerator constant is selected as A0 = B0.

III. D ESIGN D IGITAL F ILTER This chapter is going to discussed the planning, design lowpass, highpass and bandpass chebysev digital lter with perform mathematical calculations. To applied in Xilinx Ise 9.2i, with VHDL stands for VHSIC hardware description language is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as eld programmable gate arrays and integrated circuits. Block diagram of overall system can be described as follows :

Fig. 7: Block Diagram Design of Digital Filter The pole location of various Butterworth and Chebyshev lters and the coefcients of the corresponding polynimials have been derived and tabulated by weinberg (see reference Table 3.1). An abbreviated set of the polynomial coefcients for the Butterworth and Chebyshev functions are presented

TABLE I: Coefcients of low-pass lter denominator polynomials [13]

(Note: Coefcients are dened in accordance with equation (7) [13])

A. Low-Pass Digital Filter Design Design a low-pass digital lter derived from a second-order Chebyshev analog lter with a 3 dB cutoff frequency 100 Hz. The sampling rate of the system is 1K Hz and 0,5 dB ripple lter. Solution The normalized analog transfer function of the second-order Chebyshev lter with 0,5 dB ripple is obtained from Table 3.1, using dummy variable p, the function is

Coefcient of : A0 = 0,098 A1 = 0,197 A2 = 0,098 B1 = -1,035 B2 = 0,429 98 Desimal = 0062 Hex 197 Desimal = 00C5 Hex 98 Desimal = 0062 Hex -1035 Desimal = FBF5 Hex 429 Desimal = 01AD Hex

B. Band-Pass Digital Filter Design A certain digital signal processing system has a sampling rate of 4K Hz. A digital band-pass lter is desired for the system, and the specications are as follows:

(8) The frequency r = 1 rad/s in the prototype must correspond to fr = 100 Hz in the digital lter, so that the design should be based on exact correspondence at these frequencies. The folding frequency is f0 = 1000/2 = 500 Hz, and vr = 100/500 = 0,2. The constant C is

Range of passband is from 600 Hz to 800 Hz with attenuation permitted to be no greater than 3 dB at the two band-edge frequencies. Attenuation must be at least 18 dB at 400 Hz and 1K Hz. Chebyshev type response is desired with 3 dB ripple.

Solution (9) The required transformation is The folding frequency is f0 = fs /2 = 2000 Hz. The two frequencies 600 Hz and 800 Hz will be selected as the band-edge frequencies f1 and f3 respectively. For convenience, these quantities and all subsequent frequencies will be converted to normalized form.

(10) Substitution of (10) into (8) (13)

(11)

(14)

(12)

(15)

(16)

(17) The center frequency v2 is Fig. 8: Realization for System of Equation 12

Fig. 9: Realization for System of Equation 26

The normalized analog transfer function of the second-order Chebyshev lter with 3 dB ripple is obtained from Table I, using dummy variable p, the function is : (18) The transformation constants D and E with assumption that r = 1 rad/s (23) The required transformation is

(19) Letting a and b represent the two analog frequencies,

(20) Substitution of (24) into (23)

(24)

(21) and

(25)

(22)

(26)

Coefcient of : A0 = 0,016 A2 = -0,032 A4 = 0,016 B1 = -1,727 B2 = 2,513 B3 = -1,559 B4 = 0,818

16 Desimal = 0010 Hex 32 Desimal = FFE0 Hex 16 Desimal = 0010 Hex -1727 Desimal = F941 Hex 2513 Desimal = 09D1 Hex -1559 Desimal = F9E9 Hex 818 Desimal = 0332 Hex

(32)

C. High-Pass Digital Filter Design Design a high-pass digital lter derived from a second-order Chebyshev analog lter with a 3 dB cutoff frequency of 400 Hz. The sampling rate of the system is 1K Hz, with 1 dB ripple lter. Solution The normalized analog transfer function of the second-order Chebyshev lter with 1 dB ripple is obtained from Table 3.1, using dummy variable p, the function is

(33)

(27) The analog frequency r = 1 rad/s in the prototype must correspond to fr = 1K Hz in the digital lter, so that the design should be based on exact correspondence at these frequencies. The folding frequency is Fig. 10: Realization for System of Equation 33 Coefcient of : A0 = 0,078 A1 = -0,156 A2 = 0,078 B1 = 1,2 B2 = 0,516

(28) and

78 Desimal = 004E Hex 156 Desimal = FF64 Hex 78 Desimal = 004E Hex 1200 Desimal = 04B0 Hex 516 Desimal = 0204 Hex

D. Process of Implementing IIR lter The analog input signal must be sampled rst and digitized using an ADC (analog-to-digital converter). The resulting binary numbers, representing successive sampled values of the input signal, are transferred to the processor, which carries out numerical calculations on them. These calculations typically involve multiplying the input values by constants and adding the products together. If necessary, the results of these calculations, which now represent sampled values of the ltered signal, are output through a DAC (digital-to-analog converter) to convert the signal back to analog form. The modules used for implementing IIR lter are as follows: Multiplication Module entity mult is PORT ( a: IN STD_LOGIC_VECTOR (15 DOWNTO 0); b: IN STD_LOGIC_VECTOR (15 DOWNTO 0); result: OUT STD_LOGIC _VECTOR (31 DOWNTO 0) ); end mult; ARCHITECTURE rtl OF mult IS

(29) The constant C is determined as

(30) The required transformation is

(31) Substitution of (31) into (27)

SIGNAL a_int, b_int: SIGNED (15 downto 0); SIGNALpdt_int: SIGNED(31downto 0); BEGIN a_int <= SIGNED (a); b_int <= SIGNED (b); pdt_int <= a_int * b_int; result <= STD_LOGIC_VECTOR (pdt_int); END rtl; Addition Module entity add is Port ( a : in STD_LOGIC_VECTOR (31 DOWNTO 0); b : in STD_LOGIC_VECTOR (31 DOWNTO 0); c : out STD_LOGIC_VECTOR (31 DOWNTO 0)); end add; ARCHITECTURE rtl OF add IS SIGNAL a_int, b_int: SIGNED (31 downto 0); SIGNAL pdt_int: SIGNED (31 downto 0); BEGIN a_int <= SIGNED (a); b_int <= SIGNED (b); pdt_int <= a_int + b_int; c <= STD_LOGIC_VECTOR(pdt_int); END rtl;

end divider; architecture Behavioral of divider is -- signal a ,b : bit_vector(31 downto 0); begin -- a <= to_bitvector(ain); -- b <= a sra 10; dvdout <= to_stdlogicvector (to_bitvector(ain) sra 10); end Behavioral; IV. SIMULATION RESULT AND ANALYSIS A. Digital Filter Design with Simulink 1) Low-Pass Filter: The specication of the lter as shown as gure, such as: 1) 2) 3) 4) 5) Response Type: Low-Pass Design Method: IIR Chebyshev Filter Order: 2 Frequency specication: Fs(1000Hz), Fpass(100 Hz) Magnitude Specication: 0.5 dB

The test results in a Matlab program to input 2 is obtained:

Delay Module entity dff is PORT( D : IN STD_LOGIC _VECTOR(15 downto 0); Clk, Res:IN STD_LOGIC; Q : OUT STD_LOGIC_VECTOR (15 downto 0)); end dff; architecture Behavioral of dff is begin PROCESS(Clk, Res) BEGIN IF Res = 1 THEn Q <= X"0000"; Else IF (Clkevent) AND(Clk=1) THEN Q <= D; END IF; END IF; END PROCESS; end Behavioral;

Fig. 11: Simulink Simulation of Low-Pass IIR Chebyshev Filter Following tests table in Matlab program to input 2, 4, 6, ..., 20:

Divider Module entity divider is Port ( ain : in STD_LOGIC _VECTOR (31 downto 0); dvdout : out STD_LOGIC _VECTOR (31 downto 0));

TABLE II: Result Simulation Low-Pass Filter with Simulink

2) Band-Pass Filter: The specication of the lter as shown as gure , such as:

Response Type: Band-Pass Design Method: IIR Chebyshev Filter Order: 4 Frequency specication: Fs(4000Hz), Fpass1(600 Hz), Fpass2(800 Hz) Magnitude Specication: 3 dB Fig. 13: Simulink Simulation of High-Pass IIR Chebyshev Filter

The test results in a Matlab program to input 2 is obtained:

Following tests table in Matlab program to input 2, 4, 6, ..., 20:

Fig. 12: Simulink Simulation of Band-Pass IIR Chebyshev Filter

Following tests table in Matlab program to input 2, 4, 6, ..., 20:

TABLE IV: Result Simulation High-Pass Filter with Simulink

B. Simulate Implementation Filter Based on FPGA 1) Low-Pass Filter: The designed coefcients are given in equation (3.12). Now this VHDL code is used to generate the circuit using Xilinx synthesis tool and simulated using Xilinx simulator with certain inputs (2, 4, 6, ... , 20 Des) and the corresponding input and output waveform are shown in Figure 14

TABLE III: Result Simulation Band-Pass Filter with Simulink

3) High-Pass Filter: The specication of the lter as shown as gure, such as:

Response Type: High-Pass Design Method: IIR Chebyshev Filter Order: 2 Frequency specication: Fs(1000Hz), Fpass(400 Hz) Magnitude Specication: 1 dB

The test results in a Matlab program to input 2 is obtained:

Fig. 14: Behavioral/Post-Route Simulation Result of The Low-Pass Filter (LPF)

This section displayed about simulation of placed and routed design on the chip, also known as timing simulation. Simulation is performed and the results are displayed in the simulator. If no stimulus is available, the design is simply compiled and loaded in the simulator.

3) High-Pass Filter: The designed coefcients are given in equation (3.52). Now this VHDL code is used to generate the circuit using Xilinx synthesis tool and simulated using Xilinx simulator with certain inputs (2, 4, 6, ... , 20 Des) and the corresponding input and output waveform are shown in Figure 18

Fig. 18: Behavioral/Post-Route Simulation Result of The High-Pass Filter (HPF)

Fig. 15: Design Summary of Low-Pass Filter

2) Band-Pass Filter: The designed coefcients are given in equation (3.41). Now this VHDL code is used to generate the circuit using Xilinx synthesis tool and simulated using Xilinx simulator with certain inputs (2, 4, 6, ... , 20 Des) and the corresponding input and output waveform are shown in Figure 16

Fig. 19: Design Summary of High-Pass Filter Fig. 16: Behavioral/Post-Route Simulation Result of The Band-Pass Filter (BPF)

C. Placed and Route Design

Placed and routed design is used to determine the locations of CLB (Congure Logic Blocks) and to determine whether the CLBs each other connected or not, it can be said that this section will process the circuits that has been formed. On the placed, this section shows how the circuits is formed on the IC FPGA, then on the route of this section displays the CLBs used by the circuits, but in this section the author gives only small Minutes used, to more clearly heres a picture of the design placed and routed each circuit.

Fig. 17: Design Summary of Band-Pass Filter

Fig. 20: Placed Design Input Data Settings of Band-Pass Filter Fig. 22: Placed Design Input Data Settings of Low/High-Pass Filter

Fig. 21: Route Design Input Data Settings of Band-Pass Filter

Fig. 23: Route Design Input Data Settings of Low/High-Pass Filter

D. Analysis In testing an error occurs or difference in results between Matlab program with Xilinx. Errors that occur due to the limitations of the data type at Xilinx, with rounding on fractions, shown in the table below :

tools. This following table utilization of resources for Spartan3E on the design and implementation of digital lters the data settings:

TABLE VIII: Resource Utilization The Data for Setting Circuit Digital Filter for The Spartan-3E

TABLE V: Comparison Simulation Low-Pass Filter Simulink with Xilinx TABLE IX: Advanced HDL Synthesis Report The multiplier used for low-pass and high-pass lters have equal number of coefcients and that for high-pass lter has a larger amount. Similarly, all other components eg adders and registers the same for a low-pass lter and high-pass lter, bandpass lter while having a large amount. The minimum period for low-pass, high-pass lter are 1.042ns (Maximum Frequency: 875.362MHz) and for the bandpass lter is 1.384ns (Maximum Frequency: 722.648MHz). The number of 4 input LUTs for low-pass, high-pass and bandpass lters 147, 209 and 147 respectively. Total gates used in design implementation are 1463, 2408, 1463, for the low-pass, bandpass and high-pass lter respectively. V. C ONCLUSIONS The designing of Lowpass, Bandpass, and Highpass IIR Digital Filter has been accomplished. A number of ndings has been identied during the designing and simulation phases as follows, 1) Since pole-zero point in each design within the circle with radius 1, Lowpass, Bandpass, and Highpass Chebyshev lter design are stable. 2) From the design calculation, Lowpass and Highpass Chebyshev design need order 2 Lowpass and Highpass lter frequency while Bandpass Chebyshev design need order 4 Bandpass lter frequency. 3) The IIR lter are can be implemented based on FPGAs. 4) In testing the lter circuit is still there is a difference between the results of Matlab simulation program with Xilinx program. This is inuenced by the use of components Divider that perform the division of process with the results of rounding. One of the problems in process

TABLE VI: Comparison Simulation Band-Pass Filter Simulink with Xilinx

TABLE VII: Comparison Simulation High-Pass Filter Simulink with Xilinx The design of the circuit Low-Pass, Band-Pass, and HighPass have been solved by using VHDL and implementation in a Xilinx Spartan-3E (package: FG320, speed: -5), in the process of making this design using Xilinx ISE 9.2i design

simulation with Xilinx program is the use of integer data, where data of fractions must be rounding advance . 5) The number of 4 input LUTs and the total gate used in the implementation of bandpass design more than the lowpass and highpass, while lowpass and highpass having the same number. VI. F UTURE W ORKS The future scope of this work includes the following: Develop the use of fractions in the simulating program Xilinx. The A/D and D/A converter can be interfaced within the FPGA. The optimization of the design can be done in terms of area occupied on chip. R EFERENCES
[1] Jayaram Bhaskar. VHDL primer. 3rd Edition. Pearson Education Asia Publications, 2000. [2] Elanix. Fpga architect - xilinxxc4000/spartan. 2011. [3] Freeuk. http://www.dsptutor.freeuk.com/dlt1, access on november. 2011. [4] Kevan Hashemi. Filter. 2011. http://www.brandeis.edu/Lab/Filter/ Filter.html, access on November. [5] Emmanuel C. Ifeachor and Barrie W. Jervis. Digital Signal Processing: A Practical Approach. 2nd Edition. England: Pearson Education Limited, 2002. [6] Emmanuel C. Ifeachor and B.William Jervis. Digital signal processing. 2002. [7] Desy Kristyawati. Analisa dan Simulasi Perancangan Bandpass Filter untuk Fetal Doppler Menggunakan PSPICE. Gunadarma University: Undergraduate Thesis, 2009. [8] Application Note. An introduction to digital lters. 1999. [9] Agam Adityas Nugroho. Design and simulation of bandpass iir butterworth and chebyshev digital lter for fetal doppler. Masters thesis, Gunadarma University, January 2010. [10] Perry. Digital Signal Processing: A Practical Approach. 3rd Edition. Tata Mc. Graw Hill, 2001. [11] Wahyu Kusuma Raharja and Sunny Arief Sudiro. Simulasi rancangan lter butterworth menggunakan xilinx-ise 8.1i dan modelsim 6.1b. 2008. [12] Prabhat Ranjan. Implementation of r lters. Masters thesis, Thapar University, July 2008. [13] Rorabaugh and Britton. Digital Filter Designers. Tab Books/McGrawHill, 1993. [14] Carmelina Ruggiero. Swgnali Biomedici 1. Laboratorio MedInfo, 1982. [15] Timothy J. Schlichter. www.uop.edu.jo/download/pdfcourses, access on november. 2011. [16] Hartono Siswono. Pengolahan Sinyal Digital. Depok, 2008. [17] Joseph Smith. Digital lter direct form i. 2001. [18] Joseph Smith. Digital lter direct form ii. 2001. [19] Silmina Ulfah. Designing backscattering control logic based on fpga using vhdl. Masters thesis, Gunadarma University, January 2011. [20] Michael E. Valdez. Digital lter. 2001. [21] M.E Van Valkenberg. Analog Filter Design. New York: CBS College Publishing, 1982. [22] John F Wakerly. Digital Design and Practice. 3rd Edition. Pearson Education Asia, 2000. [23] Chen Wen-chi. Logic Design. CRC Press, 2000. [24] Wikipedia. Butterworth lter. 2011. http://en.wikipedia.org/wiki/Butterworth_lter, access on November. Chebyshev lter. 2011. [25] Wikipedia. http://en.wikipedia.org/wiki/Chebyshev_lter, access on November. [26] Wikipedia. Signal processing. 2011. http://en.wikipedia.org/wiki/Filter_ (signal_processing),access on November. [27] Steve Winder. Analog and Digital Filter Design. British Library Cataloguing-in-Publication Data, 2002. [28] Hans J. Wospakrik. Sinyal dan Sistem Linear. Jakarta, Indonesia: Penerbit Erlangga, 1996. [29] Xilinx. Behavioral simulation. 2011. http://www.xilinx.com/itp/xilinx10/help, access on November.

Spartan-3e fpga family: Data [30] Xilinx. http://www.xilinx.com, access on November.

sheet.

2011.