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Type NoLQ0DZC2291 SPEC No. Date NO. PAGE 22 SUMMARY Connection of terminal STHR/STHL and LCD. NOTE 1st Issue 2nd Issue LCY-09033A 2009. 06.05 LCY09033B 2009.12.8
Note: In this ASIC Specification, binary notation, decimal notation and hexadecimal notation are described according to the rules below. Binary notation: Double quotation marks are used, e.g., 111000 or 1001. Otherwise, b is appended, e.g., 111000b. Hexadecimal notation: 0x is used, e.g., 0x3F or 0x2D. Otherwise, H is appended, e.g., 20H or 1000H. Decimal notation: Unless binary notation and hexadecimal notation are used, decimal notation is used.
LCY-09033B-1 CONTENTS 1. Overview and Features of Product ...................................................................................................................................... 3 1.1. 1.2. 1.3. 2. 2.1. 2.2. Product Overview.................................................................................................................................................... 3 Main Features ......................................................................................................................................................... 3 Block diagram ......................................................................................................................................................... 3 Pin Layout............................................................................................................................................................... 5 Pin Settings............................................................................................................................................................. 7
3. Absolute Maximum Ratings ..................................................................................................................................................... 8 4. Electrical Specification ............................................................................................................................................................. 8 4.1. Recommended Operating Range...................................................................................................................................... 8 4.2. DC Electrical Specification ................................................................................................................................................ 9 4.3. AC Electrical Specification................................................................................................................................................. 9 5. Register Map ......................................................................................................................................................................... 10 6. Conditions for Input Signal ................................................................................................................................................ 11 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 7. 7.1. 7.2. 7.3. 8. 8.1. 8.2. 9. 11. Conditions for Image Signal Input ......................................................................................................................... 11 Horizontal timing 1 HENAB = Active input............................................................................................................. 13 Horizontal timing 2 HENAB = Fixed to Lo ............................................................................................................. 13 Vertical timing 1 HENAB = Active input................................................................................................................. 14 Vertical timing 2 HENAB = Fixed to Lo.................................................................................................................. 14 Horizontal/Vertical Data Capture Position ............................................................................................................. 14 Protocol................................................................................................................................................................. 15 Serial Interface AC Characteristics ....................................................................................................................... 16 Instruction to Write/Read to/from ASIC ................................................................................................................. 17 Outline of Loading................................................................................................................................................. 18 Description of Register Regarding Loading .......................................................................................................... 18
Power ON Sequence......................................................................................................................................................... 19 FreeRun Display................................................................................................................................................................ 21 Overview of FreeRun Display ............................................................................................................................... 21 Conditions for Transition to FreeRun .................................................................................................................... 21 Conditions for Recovery from FreeRun................................................................................................................. 21
12. Horizontal/Vertical Reverse Display................................................................................................................................... 22 13. RGB Independent Gamma Correction............................................................................................................................... 23 13.1. 13.2. 13.3. 14.1. 14.2. 14.3. 14.4. 14.5. 15.1. Overview of RGB Independent Gamma Correction .............................................................................................. 23 Description of Register Regarding RGB Independent Gamma Correction ........................................................... 23 Flow of Use of Independent Gamma Function...................................................................................................... 23 EEPROM .............................................................................................................................................................. 24 Recommended EEPROM ..................................................................................................................................... 24 Description of Register Regarding EEPROM........................................................................................................ 24 How to Write/Read to/from EEPROM ................................................................................................................... 24 ROM_Map of EEPROM ........................................................................................................................................ 25 Overview of DAC Control...................................................................................................................................... 26
14. EEPROM........................................................................................................................................................................... 24
Page 1
LCY-09033B-2 15.2. 15.3. 15.4. 16.1. 16.2. 17.1. 17.1.1. 17.1.2. 17.1.3. 17.2. 17.2.1. 17.2.2. 17.2.3. Recommended Component for DAC .................................................................................................................... 26 Description of Register Regarding DAC Control ................................................................................................... 26 Actual Usage......................................................................................................................................................... 27 Overview of ADC Control ...................................................................................................................................... 28 Recommended Component for ADC..................................................................................................................... 28 Example of Horizontal Timing ............................................................................................................................... 29 Horizontal Timing for Horizontal Resolution 800 Dots (WVGA) ........................................................................29 Horizontal Timing for Horizontal Resolution 480 Dots (WEGA1/WEGA2).........................................................30 Horizontal Timing for Horizontal Resolution 400 Dots (WQVGA)......................................................................31 Example of Vertical Timing.................................................................................................................................... 32 Vertical Timing for Vertical Resolution 480 Lines (WVGA)................................................................................32 Vertical Timing for Vertical Resolution 240 Lines (WQVGA/WEGA2) ...............................................................34 Vertical Timing for Vertical Resolution 272 Lines (WEGA1)..............................................................................36
18. Cautions on storage............................................................................................................................................................. 37 18.1. Storage environment ..................................................................................................................................................... 37 18.2. Storage methods ........................................................................................................................................................... 37 18.3. Long-term storage ......................................................................................................................................................... 37 19. Recommended soldering condition of infrared reflow .......................................................................................................... 39 20. Outline drawings .................................................................................................................................................................. 40 21. Marking ................................................................................................................................................................................ 41 22. Tray container ...................................................................................................................................................................... 42 23.Packing outline drawing ........................................................................................................................................................ 43 24. Carton .................................................................................................................................................................................. 44
Page 2
LCY-09033B-3
1.
1.1.
1.2.
a) b) c) d) e) f) g) h) i)
Main Features
Timing controller (for WVGA, WQVGA, WEGA1 and WEGA2) contained ROMOFF setting (It can be specified whether external EEPROM should be disabled or enabled.) HSY/VSY input monitoring function. (Free Run is shown when HSY/VSY has not yet been input and when an error has been occurred in input.) Free Run Display (Blue background screen 1H = 1200 clk or more/1V = 700 Lines or more Horizontal/vertical reverse display available. Independent gamma setting (supported only for ROMOFF = 0) External D/A Converter 8ch control output supported (only for ROMOFF = 0) External A/D Converter 2ch control output supported (only for ROMOFF = 0) Internal register control with I2C (only for ROMOFF = 0)
1.3.
Block diagram
DCLK RGB
Input I/F
Waveform shaping/judgment
Gamma correction
Video signal
CMOS I/F
CMOS LCD
control signal
LUT
Synchronization signal
T-CON
uCom
I2C
Slave
Register
LUT/Reg Loader
I2C
Master
DAC Ctrl
ADC Ctrl
DAC
ADC
EEPROM
Page 3
LCY-09033B-4 Overview of block diagram is described below. (1) Input I/F Receives 18-bit parallel data input externally and passes it to the image processing block stated below. Waveform shaping (Hsy/Vsy phase difference absorption), pulse noise elimination (pulse of 2 clk or less) from control signal and synchronization signal input judgment are performed here. (2) Blue background display A block to generate the blue background display when Input I/F of (1) has judged that there is no synchronization signal input. (3) Gamma correction The gamma correction function allows to process input video data per RGB data and adjust the gamma curve per R, G and B. (This is available only for ROMOFF = 0.) (4) T-CON A block of timing controller to drive a panel of four kinds of resolutions, i.e., WVGA, WQVGA, WEGA1 and /WEGA2. (5) LUT/Reg_Loader A block to read a data from the external EEPROM, which is connected to have an initial value of an ASICs internal register and internal LUT, and to update the data for the register and LUT. (6) DAC Ctrl External D/C converter can be connected and controlled to set up the liquid crystal display gradation and specify the COM signal. In this block, a control signal to DAC is generated to control DAC. (7) ADC Ctrl External A/D converter can be connected and controlled. This block receives a signal from ADC and stores a data in the internal register of ASIC. Thermistor and photo sensor can be connected and monitored, by way of example.
Page 4
LCY-09033B-5
2.
2.1.
Pin Description
Pin Layout
Table 2-1 describes all the pins. Table 2-1: Pin Description PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O Attribute I I I I I I I I I I I I Id Iu Iu Id Id O I Id Iu Id Iu I Isu Id Id Id Id Id Iou Iu O O O O O IOu O O IOu Pin Name VDD IG0 IG1 IG2 IG3 IG4 IG5 IB0 IB1 IB2 IB3 IB4 IB5 ROMOFF VRVC HRVC SMC GMDSEL SOUT TMC AMC VSY HENAB HSY VDD GND DCLK GND FRESET VDD S_SEL G_SEL DSEL1 DSEL2 TEST1 GND SERDIO SERCK ADCCK ADCCS ADCDI ADCDO DACDI DACLD DACCK GND ROMCK ROMWC ROMDIO GND Drive Power Description of Function Operation when it is not be used
Green data input pin (LSB) Green data input pin Green data input pin Green data input pin Green data input pin Green data input pin (MSB) Blue data input pin (LSB) Blue data input pin Blue data input pin Blue data input pin Blue data input pin Blue data input pin (MSB) Setting whether external EEPROM should be disabled or enabled Vertical scan reversal Horizontal scan reversal ASIC test pin Gate start pulse output setting ASIC test pin ASIC test pin ASIC test pin Vertical synchronization signal input pin Horizontal data enable input pin Horizontal synchronization signal input pin
Clock input pin ASIC reset pin Source driver setting pin Gate driver setting pin Resolution setting pin 1 Resolution setting pin 2 ASIC test pin 3mA 3mA 3mA 3mA 3mA 3mA 3mA 3mA 3mA 3mA Serial data I/O pin Serial clock input pin ADC clock output pin ADC chip select output pin ADC control data output pin ADC data input pin DAC data output pin DAC load output pin DAC clock output pin EEPROM clock output pin EEPROM write protect output pin EEPROM data I/O pin
GND OPEN OPEN/VDD OPEN OPEN OPEN OPEN/VDD OPEN OPEN OPEN OPEN OPEN OPEN
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LCY-09033B-6
I/O Attribute O O O O O O O O O O O O O O O O O O IO IO O O O O O IO O IO O O I Id O O O I I I I I I
Pin Name VDD OR0 OR1 OR2 OR3 OR4 OR5 GND OG0 OG1 OG2 OG3 OG4 OG5 VDD OB0 OB1 OB2 OB3 OB4 OB5 GND STHR STHL VDD GND CLK GND STB REV FS REVC LBR GSPOI MODE2 R/L GSPIO SPS GOE MODE1 GCK CLS TEB TEST2 ALLON DCON G_SLP VDD IR0 IR1 IR2 IR3 IR4 IR5 GND IO: I/O pin
Drive Power 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA 6mA
Description of Function
Red data output pin (LSB) Red data output pin Red data output pin Red data output pin Red data output pin Red data output pin (MSB) Green data output pin (LSB) Green data output pin Green data output pin Green data output pin Green data output pin Green data output pin (MSB) Blue data output pin (LSB) Blue data output pin Blue data output pin Blue data output pin Blue data output pin Blue data output pin (MSB) * Start pulse I/O signal 1 * Start pulse I/O signal
1
12mA 6mA 6mA 6mA 3mA 3mA 3mA 3mA 3mA 3mA
Source driver sampling clock Source driver latch pulse output Source driver polarity reversal control output * Offset cancel / COM polarity reversal signal output Source driver horizontal reversal control output * Gate start pulse / Gate mode setting pin Gate driver vertical reversal control output * Gate start pulse * Gate driver control output * Gate driver shift clock ASIC test pin ASIC test pin Full gate output ON setting output Power supply circuit control output Gate slope control pin Red data input pin (LSB) Red data input pin Red data input pin Red data input pin Red data input pin Red data input pin (MSB)
O: Output pin
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LCY-09033B-7
2.2.
Pin Settings
Table 2-2 describes the pin settings. Table 2-2: Pin Settings Pin name S_SEL (*) G_SEL (*) VRVC HRVC Source setting pin For how to set this pin, ask the person in charge of Sharp Corporation. Gate setting pin For how to set this pin, ask the person in charge of Sharp Corporation. Gate driver scan direction setting Refer to Chapter 11 Horizontal/Vertical Reverse Display. Source driver scan direction setting Refer to Chapter 11 Horizontal/Vertical Reverse Display. Gate start pulse output setting GMDSEL Lo: Normal mode Hi: Interlacing two-pulse mode Input resolution switch setting pin Resolution WVGA WQVGA D_SEL2 (*) WEGA1 WEGA2 EEPROM setting pin Lo: EEPEOM is enabled. ROMOFF (*) Hi: EEPEOM is disabled. If ROMOFF is set to 1, this ASIC is used as a timing controller. Therefore, register control, DAC control, etc. cannot be performed. FRESET Reset pin (Lo-Active) * Time constant shall be 10 ms or less. Refer Figure 2-1. D_SEL1 0 1 0 1 D_SEL2 0 0 1 1 Function
D_SEL1 (*)
Do not change any setting of pins marked with *, after the ASIC power supply turns ON.
3.3 V
90%
FRESET
0V
10%
T 10 ms
Page 7
LCY-09033B-8
4. Electrical Specification
4.1. Recommended Operating Range
Table 4-1: Recommended Operating Range Parameter Supply voltage*
1
Condition
Typ. 3.15
Unit V V V V V V ns ns ms ms
Positive trigger voltage Negative trigger voltage Hysteresis voltage Input rise time Input fall time Input rise time Input fall time
Schmitt Buffer
0.8 0.3 0 0
Schmitt Buffer
0 0
Condition1 Parameter Supply voltage Input voltage, high Input voltage, low Symbol VDD VIH VIL Min. 3.0 0.7VDD 0 Typ. Max. 3.6 VDD 0.3VDD Unit V V V
Condition2 Parameter Supply voltage Input voltage, high Input voltage, low Symbol VDD VIH VIL Min. 2.7 0.75VDD 0 Typ. Max. 3.0 VDD 0.25VDD Unit V V V
Page 8
LCY-09033B-9
Page 9
LCY-09033B-10
5. Register Map
Table 5-1 shows the register map list of LQ0DZC2291. Table 5-1: Register Map List address bit7 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh gamma_enb 0Fh 10h bit6 bit5 bit4 bit3 bit2 da_0ch[7:0] da_1ch[7:0] da_2ch[7:0] da_3ch[7:0] da_4ch[7:0] da_5ch[7:0] da_6ch[7:0] da_7ch[7:0] henab[7:0] venab[7:0] rsel stb_hl[6:0] gck_hl[7:0] slp_ctrl[6:0] test test bit1 bit0 Initial value 0000_0000b 0000_0000b 0000_0000b 0000_0000b 0000_0000b 1111_1111b 0111_1000b 0000_0000b 1100_0010b 0010_0011b 0000_0000b 0100_0101b 1010_1010b 0100_0011b 0000_0000b 0000_0000b 0000_0000b
vrvc
hrvc
ready
jinput
: Register for auto-loading als register value 0: Inaccessible. als register value 1: Write/Read can be done from a host. : Register not for auto-loading als register value 0: Inaccessible als register value 1: Write/Read can be done from a host. : Register not for auto-loading Regardless of the als register value, Write/Read can be done. : Read-Only register Regardless of the als register value, Read only can be done.
Page 10
LCY-09033B-11
6.
6.1.
WVGA [D_SEL1=0, D_SEL2=0] ITEM Frequency DCLK Hi_Time Low Width Setup time Data[I* 0-5] Hold time
Min. Typ. 26.62 33.26 5 5 5 5 31.45 31.75 Cycle 1024 1056 Hsy 5 Pulse Width 520 525 Cycle Vsy 2 Pulse Width 50 60 frame rate 800 Horizontal display period A-8 A Hsy_DCLK phase defference -10 0 Hsy_Vsy phase defference 5 Vertical fromt porch 35 Vertical back porch tVBP 10 28 480 Vertical display porch tVA 5 Setup time tES 5 Enable signal[HENAB] Hold time tEH Pulse Width 800 tEP Horizontal front porch 2 tHFP 194 tHBP Horizontal display starting position tHBP 20 *1: This spec is appied for HENAB Lo mode and W/O EEPROM mode *2: This spec is applied for HENAB active mode or W/EEPROM mode
Symbol tCLK tWCH tWCL tDS tDH tH(t) tH(clk) tHPW tV tVPW fV tHA tHC tVH tVFP
Remark Frequency:1/(tV/tH(clk))
*1 *2
WQVGA [D_SEL1=1, D_SEL2=0] ITEM Frequency DCLK Hi_Time Low Width Setup time Data[I* 0-5] Hold time
Min. Typ. 6.96 7.99 5 5 5 5 61.3 63.6 Cycle 491 508 Hsy 5 Pulse Width 258 262 Cycle Vsy 2 Pulse Width 50 60 frame rate 400 Horizontal display period A-8 A Hsy_DCLK phase defference -10 0 Hsy_Vsy phase defference 5 Vertical fromt porch 20 Vertical back porch tVBP 9 240 Vertical display porch tVA 5 Setup time tES 5 Enable signal[HENAB] Hold time tEH Pulse Width 400 tEP Horizontal front porch 2 tHFP 87 tHBP Horizontal display starting position tHBP 20 *1: This spec is appied for HENAB Lo mode and W/O EEPROM mode *2: This spec is applied for HENAB active mode or W/EEPROM mode
Symbol tCLK tWCH tWCL tDS tDH tH(t) tH(clk) tHPW tV tVPW fV tHA tHC tVH tVFP
Remark Frequency:1/(tV/tH(clk))
*1 *2
Page 11
WEGA1 [D_SEL1=0, D_SEL2=1] ITEM Frequency DCLK Hi_Time Low Width Setup time Data[I* 0-5] Hold time Hsy Vsy Cycle Pulse Width Cycle Pulse Width
frame rate Horizontal display period Hsy_DCLK phase defference Hsy_Vsy phase defference Vertical fromt porch Vertical back porch Vertical display porch Setup time Enable signal[HENAB] Hold time Pulse Width Horizontal front porch
Symbol tCLK tWCH tWCL tDS tDH tH(t) tH(clk) tHPW tV tVPW fV tHA tHC tVH tVFP tVBP
Typ. 9.70
Max. 10.99
64.1 622
312
50 480 A 0
A-8 -10 2
A+8 10
31 272
41
tVA 5 tES 5 tEH 480 tEP 2 tHFP 116 tHBP Horizontal display starting position tHBP 20 *1: This spec is appied for HENAB Lo mode and W/O EEPROM mode *2: This spec is applied for HENAB active mode or W/EEPROM mode
164
Remark Frequency:1/(tV/tH(clk))
*1 *2
WEGA2 [D_SEL1=1, D_SEL2=1] ITEM Frequency DCLK Hi_Time Low Width Setup time Data[I* 0-5] Hold time
Min. Typ. 8.35 9.59 5 5 5 5 61.3 63.6 Cycle 589 610 Hsy 5 Pulse Width 258 262 Cycle Vsy 2 Pulse Width 50 60 frame rate 480 Horizontal display period A-8 A Hsy_DCLK phase defference -10 0 Hsy_Vsy phase defference 2 Vertical fromt porch 20 Vertical back porch tVBP 9 240 Vertical display porch tVA 5 Setup time tES 5 Enable signal[HENAB] Hold time tEH Pulse Width 480 tEP Horizontal front porch 2 tHFP 104 tHBP Horizontal display starting position tHBP 20 *1: This spec is appied for HENAB Lo mode and W/O EEPROM mode *2: This spec is applied for HENAB active mode or W/EEPROM mode
Symbol tCLK tWCH tWCL tDS tDH tH(t) tH(clk) tHPW tV tVPW fV tHA tHC tVH tVFP
Remark Frequency:1/(tV/tH(clk))
*1 *2
Page 12
LCY-09033B-13
6.2.
HSY
0.7HVDD
tHC
DCLK
tES tHBP tEH tDH tDS tHA tWCH tHFP
HENAB
InData
Figure 6-1: WVGA/WQVGA/WEGA1/WEGA2 Input Data Format (HENAB active/horizontal timing) InData above shows the image signal bus of IR0-5, IG0-5 and IB0-5 collectively. This applies to any InData after this.
6.3.
HSY
0.7HVDD
tHC
DCLK
tWCH tHBP tHFP
HENAB
tDH tDS tHA
InData
Page 13
LCY-09033B-14
6.4.
VSY
0.7HVDD
tVH
HSY HENAB
tVA
InData
6.5.
tWVL
VSY
0.7HVDD tVH
0.3HVDD tVH
HSY
tVBP tVFP tVA
HENAB InData
6.6.
Active input
A: Decided according to a henab register set value. B: Decided according to a venab register set value.
Page 14
LCY-09033B-15
7.
7.1.
SERCK SERDIO
START Condition SDA Input SDA Change STOP Condition
SERCK SERDIO
START Condition
1 MSB
9 ACK
SERCK SERDIO
1 MSB
Page 15
LCY-09033B-16
7.2.
Figure 7-2 and Table 5-1 show the specifications for AC characteristics of I2C serial I/F.
tHIGH tLOW
SERCK
tTAhd
SERDIO_in
tTAsu START Condition SDA Input tDIhd SDA Change tDIsu tTOsu tBUF
SERCK
SERDIO_in
tTOsu STOP Condition tW Write Cycle tTAsu START Condition
SERCK
tpd tDOhd Data Valid
SERDIO_out
0.8Vcc
SERCK
tR1 0.8Vcc
0.2Vcc tF1
SERDIO
tR2
0.2Vcc TF2
Figure 7-2: AC Specifications for Serial I/F Table 7-1: AC Specifications for Serial I/F Item Clock frequency Data clock Hi time Data clock Lo time Clock rise time Clock fall time Data rise time Data fall time Input data setup time Input data hold time Output data hold time Output data delay time Start condition setup time Start condition hold time Stop condition setup time Bus release time before transfer start Writing time Symbol fSCK tHIGH tLOW tR1 tF1 tR2 tF2 tDIsu tDIhd tDOhd tpd tTAsu tTAhd tTOsu tBUF tW Min. 600 1200 40 40 40 40 100 0 200 200 600 600 600 1300 Max. 400 Unit kHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
900
10
Page 16
LCY-09033B-17
7.3.
Figure 7-3 shows how to Write/Read to/from ASIC with I2C of LQ0DZC2291.
(When writing)
ACK ACK BYTE ADDR R/W DATA IN STOP ACK
BYTEWRITE
START
DEV SEL
ACK
ACK DA TA IN2
ACK DATA IN N
ACK
PAGEWRITE
START
(When reading)
ACK ACK BYTE ADDR R/W START DEV SEL R/W ACK NO ACK DATA OUT STOP
DEV SEL
ACK
ACK
NO ACK
* DEV_SEL of this ASIC is 1000111. Figure 7-3: How to Write/Read with I2C
Page 17
STOP
LCY-09033B-18
8.
8.1.
8.2.
Table 8-2 shows the registers regarding loading. Table 8-2: Registers Regarding Loading
address 31h als=0 als=1 32h ready ready
Hi: Initial EEPROM loading completed. Lo: Initial EEPROM loading in process. Hi: When HSY/VSY has not yet been input Lo: At a normal input operation Hi: When Henable has been input Lo: when Henable has not yet been input
bit7
bit6
bit5
bit4 -
bit3
bit2
bit1
bit0 als
Auto-loading enabled: Any access from I2C to a register area to be loaded is prohibited. Auto-loading disabled: Register access functions completely.
jinput
jenable
jinput jenable
Page 18
LCY-09033B-19
9.
Power ON Sequence
Figure 9-1 below shows the power ON sequence.
DCLK
Data in
FRESET 1650ck
DCON (internal counter reset cancel timing)
11
Internal VSY
10
Ready
REV
REVC
GOE
MODEx
RGBOut
Figure 9-1: Power ON Sequence Procedure: (1) (2) When ASIC has turned on, change the reset pin (FRESET) of this ASIC from Lo to Hi and cancel the reset. When the reset has been cancelled, ASIC loads the initial values of internal register and LUT from EEPROM (for a maximum period of approximately 2 V). * In this period, access with I2C from an external CPU to a register to be loaded is prohibited. When making access, check that the ready register is 1 (i.e., initial loading has been completed). (3) (4) (5) (6) Power ON sequence starts with VsyActive immediately after DCON has become Hi. REV reversal starts according to the Vsy(6) timing. (Polarity reversal starts.) Data output starts according to the Vsy(7) timing. The liquid crystal display enters a normal operation state at Vsy(8).
Page 19
LCY-09033B-20
henab[7:0] venab[5:0]
0010_0011b 0010_0011b
Horizontal display start position specified when the HENABLE signal is fixed to Lo. Vertical display start position specified. * Available only when ROMOFF = 0 is set.
rsel
vrvc
hrvc
0000_0000b
Scan direction change setting rsel, vrvc ,hrvc * Refer to Chapter 12: Horizontal/Vertical Reverse Display.
0Bh
stb_hl[6:0]
0100_0101b
stb_l Adjustment of STB in Hi period. Pulse width of STB is adjusted and charge share time is adjusted. * Refer to the set values listed in Table 10-2. 0Ch
Adjustment of CLS in Hi period. gck_hl * Refer to the set values listed in Table 10-2.
gck_hl[7:0]
1010_1010b
0Dh slp_ctrl
slp_ctrl[6:0]
0100_0011b
: Auto-loading register For the initial setting of stb_hl / gck_hl / slp_ctrl when ROMOFF = 0 has been specified, refer to Table 10-2. Table 10-2: Setting for stb_hl / gckhl / slp_ctrl stb_hl gck_hl WVGA 69 70 WQVGA 16 40 WEGA1 20 49 WEGA2 20 49
slp_ctrl 67 16 19 19
Perform the gate driver pulse output setting through the GMDSEL pin. Refer to Table 10-3. Table 10-3: Gate Start Pulse Output Setting GMDSEL Pin 0 1 Gate start pulse output setting Normal mode Interlacing two-pulse mode
Page 20
LCY-09033B-21
11.
11.1.
FreeRun Display
Overview of FreeRun Display
This ASIC shows the blue background stored internally when a synchronization signal (Hsy/Vsy) input externally has been disappeared.
11.2.
This ASIC counts Hsy/Vsy input externally. If the conditions below are met, this ASIC shows the blue background judging that there is no external input or an input error has occurred. A value of clk of 1H 1200 clk A value of clk of 1H tHA The number of lines of 1V 700 lines The number of lines of 1V tVA
11.3.
The ASIC counts Hsy/Vsy input externally in the FreeRun state. When the conditions below have been met and the same count value is obtained twice continuously, the ASIC shows the external input signal display judging that there is an external input. (tHA < a value of clk of 1H < 1200 clk) & the same count value obtained twice continuously (tVA < the number of lines of 1V < 700 line) & the same count value obtained twice continuously
Page 21
LCY-09033B-22
vrvc
hrvc
For 0 setting, the vertical/horizontal reverse display is set by the input pins VRVC and HRVC. For 1 setting, the vertical/horizontal reverse display is set by the register values vrvc and hrvc. If the rsel register value is 1, the vertical reverse display is set. If the rsel register value is 1, the horizontal reverse display is set.
vrvc hrvc
The HRVC pin/hrvc register setting and the I/O of LBR/STHR/STHL are shown below. Table 12-3: I/O Related to Horizontal Reverse Display HRVC pin/ hrvc register 0 1 LBR 0 1 STHR Input Output STHL Output Input
Please confirm the I/O relation described in specifications of LCD, and connect it with LQ0DZC2291. The VRVC pin/vrvc register setting and the I/O of RL/GSPOI_MODE2/GSPIO_SPS are shown below. Table 12-4: I/O Related to Vertical Reverse Display G_SEL=0 VRVC/ vrvc register 0 1 R/L 0 1 GSPOI_ MODE2 Output (GSPOI) Input (GSPOI) GSPIO_ SPS Input (GSPIO) Output (GSPIO) R/L 1 0 G_SEL=1 GSPOI_ MODE2 Output (MODE2) Output (MODE2) GSPIO_ SPS Output (SPS) Output (SPS)
Page 22
LCY-09033B-23
13. 13.1.
13.2.
Table 13-1 shows the register regarding RGB independent gamma correction. Table 13-1: Register Regarding RGB Independent Gamma Correction
address 0Eh gamma_en bit7 gamma_en bit6 bit5 bit4 bit3 Setting to turn ON/OFF RGB independent gamma gamma_en=0: Independent gamma correction is disabled. (The gamma correction is omitted.) gamma_en=1: Independent gamma correction is enabled.
bit2
bit1
bit0
13.3.
As described above, the independent gamma parameters are loaded from EEPROM. Those independent gamma parameters are stored in the 192 addresses from 0x40 to 0xFF in EEPROM. Therefore, to use the independent gamma function, (1) write the set values corresponding to input gradations in advance and (2) store the data of 0x80 in the address 0x0E (gamma_enb) where is an auto-loading area in EEPROM.
Page 23
LCY-09033B-24
14. EEPROM
14.1. EEPROM
When using this ASIC, 256word8bitEEPROM can be connected externally. Connect it to Pin (47: ROMCK, 48: ROMWC, 49: ROMDIO) of ASIC. This allows to load the ASIC register set values and independent gamma parameters from EEPROM. EEPROM is controlled by ASIC. So, any access from an external CPU to EEPROM must be performed through ASICs internal register.
14.2.
Recommended EEPROM
Rohm BR24L02-W can be recommended as EEPROM that connection verification was executed. * Slave address 1010_000
14.3.
Table 14-1 shows the register regarding EEPROM. Table 14-1: Description of Register Regarding EEPROM
address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
20h rom_adrs
rom_adrs[7:0]
An address to access EEPROM is specified.
0000_0000b
21h rom_data
rom_data[7:0]
0000_0000b
To write a data into EEPROM, specify an target address (in which the data is written) in the rom_adrs register and the target data (to be written) in this register and write the data into EEPROM through the rom_write register. To read a data from EEPROM, specify an target address (which stores the data to be read) in the rom_adrs and read the data from EEPROM through rom_read register. Then, the data stored in the specified address is stored in this register. When reading this register, confirm rom_head = 0 in advance.
rom_read
rom_write
xxxx_xx00b
The contents of EEPROM address specified in the rom_adrs register are read and then stored in the rom_data register. During reading from EEPROM, this register remains 1. When reading has been completed and the values have been stored in the rom_data register, this register becomes 0. A value of the rom_data register is written into an address in EEPROM, which is specified in the rom_adrs register. During writing into EEPROM, this register remains 1. When writing has been completed, this register becomes 0.
You can not set both of rom_read = 1 and rom_write = 1 simultaneously. Your operation is ignored.
14.4.
(How to write) (1) Read the address 0x22 to check that it is 0x00. (If the Read data in this address is 0x01or0x02, any instruction from an external CPU is ignored because access to EEPROM is in process.) (2) Specify an EEPROM address to be written into the 0x20 address. (3) Write a data to be written into the address specified in step (2) in the address 0x21. (4) When 0x01 has been written into the address 0x22, the data specified in the step (3) is written into the EEPROM address specified in the step (2). (When the operation has been completed, ASIC changes the address 0x22 to 0x00 automatically.) (5) Unless the address 0x22 changes to 0x00 as stated in the step (1), any more writing/reading to/from EEPROM cannot be executed. (How to read) (1) Read the address 0x22 to check that it is 0x00. (If the Read data in this address is 0x01or0x02, any instruction from an external CPU is ignored because access to EEPROM is in process.) (2) Specify an EEPROM address to be read out to the 0x20 address. (3) When 0x02 has been written into the address 0x22, reading out from EEPROM to the address specified in the step (2) starts and the read data is written into the address 0x21. (When the operation has been completed, ASIC changes the address 0x22 to 0x00 automatically.) (4) Check that a data in the address 0x22 is 0x00 and then read out the data written into the address 0x21.
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LCY-09033B-25
14.5.
ROM_Map of EEPROM
Table 14-2 shows mapping in EEPROM of this ASIC. Technique to storage in EEPROM is described below individually in detail. Table 14-2: ROM_Map of EEPROM
ADRS 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Content dac_0ch dac_1ch dac_2ch dac_3ch dac_4ch dac_5ch dac_6ch dac_7ch Horizontal display start position adjustment Vertical display start position adjustment Scan direction change setting Charge share adjustment CLS_Hi period adjustment Gate slope adjustment Gamma control Test register Test register Gate output mode setting ADRS 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Content Independent gamma (R)_00 Independent gamma (R)_01 Independent gamma (R)_02 Independent gamma (R)_03 Independent gamma (R)_04 Independent gamma (R)_05 Independent gamma (R)_06 Independent gamma (R)_07 ADRS 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 Content Independent gamma (G)_00 Independent gamma (G)_01 Independent gamma (G)_02 Independent gamma (G)_03 Independent gamma (G)_04 Independent gamma (G)_05 Independent gamma (G)_06 Independent gamma (G)_07 ADRS 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 Content Independent gamma (B)_00 Independent gamma (B)_01 Independent gamma (B)_02 Independent gamma (B)_03 Independent gamma (B)_04 Independent gamma (B)_05 Independent gamma (B)_06 Independent gamma (B)_07 Independent gamma (B)_08 Independent gamma (B)_09 Independent gamma (B)_10 Independent gamma (B)_11 Independent gamma (B)_12 Independent gamma (B)_13 Independent gamma (B)_14 Independent gamma (B)_15 Independent gamma (B)_16 Independent gamma (B)_17 Independent gamma (B)_18 Independent gamma (B)_19 Independent gamma (B)_20 Independent gamma (B)_21 Independent gamma (B)_22 Independent gamma (B)_23 Independent gamma (B)_24 Independent gamma (B)_25 Independent gamma (B)_26 Independent gamma (B)_27 Independent gamma (B)_28 Independent gamma (B)_29 Independent gamma (B)_30 Independent gamma (B)_31 Independent gamma (B)_32 Independent gamma (B)_33 Independent gamma (B)_34 Independent gamma (B)_35 Independent gamma (B)_36 Independent gamma (B)_37 Independent gamma (B)_38 Independent gamma (B)_39 Independent gamma (B)_40 Independent gamma (B)_41 Independent gamma (B)_42 Independent gamma (B)_43 Independent gamma (B)_44 Independent gamma (B)_45 Independent gamma (B)_46 Independent gamma (B)_47 Independent gamma (B)_48 Independent gamma (B)_49 Independent gamma (B)_50 Independent gamma (B)_51 Independent gamma (B)_52 Independent gamma (B)_53 Independent gamma (B)_54 Independent gamma (B)_55 Independent gamma (B)_56 Independent gamma (B)_57 Independent gamma (B)_58 Independent gamma (B)_59 Independent gamma (B)_60 Independent gamma (B)_61 Independent gamma (B)_62 Independent gamma (B)_63
Independent gamma (R)_08 0x88 Independent gamma (R)_09 0x89 Independent gamma (R)_10 0x8A Independent gamma (R)_11 Independent gamma (R)_12 Independent gamma (R)_13 Independent gamma (R)_14 Independent gamma (R)_15 Independent gamma (R)_16 Independent gamma (R)_17 Independent gamma (R)_18 Independent gamma (R)_19 Independent gamma (R)_20 Independent gamma (R)_21 Independent gamma (R)_22 Independent gamma (R)_23 Independent gamma (R)_24 Independent gamma (R)_25 Independent gamma (R)_26 Independent gamma (R)_27 Independent gamma (R)_28 Independent gamma (R)_29 Independent gamma (R)_30 Independent gamma (R)_31 Independent gamma (R)_32 Independent gamma (R)_33 Independent gamma (R)_34 Independent gamma (R)_35 Independent gamma (R)_36 Independent gamma (R)_37 Independent gamma (R)_38 Independent gamma (R)_39 Independent gamma (R)_40 Independent gamma (R)_41 Independent gamma (R)_42 Independent gamma (R)_43 Independent gamma (R)_44 Independent gamma (R)_45 Independent gamma (R)_46 Independent gamma (R)_47 Independent gamma (R)_48 Independent gamma (R)_49 Independent gamma (R)_50 Independent gamma (R)_51 Independent gamma (R)_52 Independent gamma (R)_53 Independent gamma (R)_54 Independent gamma (R)_55 Independent gamma (R)_56 Independent gamma (R)_57 Independent gamma (R)_58 Independent gamma (R)_59 Independent gamma (R)_60 Independent gamma (R)_61 Independent gamma (R)_62 Independent gamma (R)_63 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF
Independent gamma (G)_08 0xC8 Independent gamma (G)_09 0xC9 Independent gamma (G)_10 0xCA Independent gamma (G)_11 Independent gamma (G)_12 Independent gamma (G)_13 Independent gamma (G)_14 Independent gamma (G)_15 Independent gamma (G)_16 Independent gamma (G)_17 Independent gamma (G)_18 Independent gamma (G)_19 Independent gamma (G)_20 Independent gamma (G)_21 Independent gamma (G)_22 Independent gamma (G)_23 Independent gamma (G)_24 Independent gamma (G)_25 Independent gamma (G)_26 Independent gamma (G)_27 Independent gamma (G)_28 Independent gamma (G)_29 Independent gamma (G)_30 Independent gamma (G)_31 Independent gamma (G)_32 Independent gamma (G)_33 Independent gamma (G)_34 Independent gamma (G)_35 Independent gamma (G)_36 Independent gamma (G)_37 Independent gamma (G)_38 Independent gamma (G)_39 Independent gamma (G)_40 Independent gamma (G)_41 Independent gamma (G)_42 Independent gamma (G)_43 Independent gamma (G)_44 Independent gamma (G)_45 Independent gamma (G)_46 Independent gamma (G)_47 Independent gamma (G)_48 Independent gamma (G)_49 Independent gamma (G)_50 Independent gamma (G)_51 Independent gamma (G)_52 Independent gamma (G)_53 Independent gamma (G)_54 Independent gamma (G)_55 Independent gamma (G)_56 Independent gamma (G)_57 Independent gamma (G)_58 Independent gamma (G)_59 Independent gamma (G)_60 Independent gamma (G)_61 Independent gamma (G)_62 Independent gamma (G)_63 0xCB 0xCC 0xCD 0xCE 0xCF 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF
(1)
(2)
00h to 3Fh (Basic register setting part) For the register (marked with ) for auto-loading in the register Map, be sure to store an initial setting data in this area. For an area not for auto-loading, even if any data is stored in EEPROM, it is not stored in the internal register. 40h to FFh (Area to store independent gamma parameter) Independent gamma LUT in ASIC is available for 129 addresses (64 x RGB) x 8 bits. To use the independent gamma function, store the values in 0x40 to 0xFF.
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LCY-09033B-26
15.2.
Fujitsu 8chDAC MB88347 can be recommended as DAC that connection verification was executed.
15.3.
Table 15-1 describes the register regarding DAC control Table 15-1: Description of Register Regarding DAC Control DAC control
address 00h dac_0ch 01h dac_1ch 02h dac_2ch 03h dac_3ch 04h dac_4ch 05h dac_5ch 06h dac_6ch 07h dac_7ch
DAC 7ch setting register DAC 6ch setting register DAC 5ch setting register DAC 4ch setting register DAC 3ch setting register DAC 2ch setting register DAC 1ch setting register DAC 0ch setting register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
dac_0ch[7:0]
dac_1ch[7:0]
0000_0000b
dac_2ch[7:0]
0000_0000b
dac_3ch[7:0]
0000_0000b
dac_4ch[7:0]
0000_0000b
dac_5ch[7:0]
1111_1111b
dac_6ch[7:0]
0111_1000b
dac_7ch
0000_0000b
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LCY-09033B-27
15.4.
(1)
Actual Usage
Use in a fixed set value for mass production For the use in mass production (normal), store a voltage value to be set in EEPROM in advance. Then, ASIC stores a setting data in the ASICs register at the initial loading after FRESET and, based on that, a control instruction to DAC is transferred.
(2)
Adjustment of opposite electrode center value in a process/source driver gradation setting voltage value This register is for auto-loading. To adjust in a process, follow the flow below. (How to adjust the amplitude of opposite electrode signal of address is described below. This applies also to any other set values.) 1. Set the ASIC register address 0x31[0]: als 1 and stop loading from EEPROM. 2. Change the ASIC register address DAC set value to find the most suitable value. (If the amplitude of opposite electrode signal is adjusting, a point that a flicker of liquid crystal minimizes is the most suitable value.) *) As described above, when als = 1, transfer to DAC is performed at every 1V. Even if a register is rewritten at a frequency of 1V or less, nothing is reflected in the display. Pay great attention to a change speed of register value. 3. Write the most suitable value confirmed in the step 2 into EEPROM. For how to write it, refer to 14.4. How to Write/Read to/from EEPROM. 4. Here, an initial value has been stored in EEPROM. From now on, ASIC recognizes this initial value whenever the power supply turns on.
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LCY-09033B-28
16.2.
National Semiconductor 2chADC ADCVO8832 can be recommended ADC that connection verification was executed. Table 16-1: Description of Register Regarding ADC Control ADC control
address 34h 35h adc_data1 adc_data2
ADC 1ch Register ADC 2ch Register
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
adc_data1 adc_data2
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LCY-09033B-29
Example of Horizontal Timing Horizontal Timing for Horizontal Resolution 800 Dots (WVGA)
800
OutData
STHR (STHL)
(803) stb_hl[69]
* For S_SEL = 1, fixed to 5.
STB
gck_hl[70]
(702)
GCK
(CLS polarity is reversed)
(792)
REVV
slp_ctrl[67]
G_SLP
(759)
REVC
(Available for S_SEL = 1)
* Only once after VSY fall
|FS
(Available for S_SEL = 0)
Figure in [ ] is a value for ROMOFF = 1. Figure in ( ) is a standard value. Figure 17-1: Horizontal Timing Chart for Horizontal Resolution 800 Dots (WVGA)
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LCY-09033B-30
17.1.2. CLK
480
OutData
STHR (STHL)
(483) stb_hl[20] * For S_SEL = 1, fixed to 5.
STB
gck_hl[49]
(436)
GCK
(CLS polarity is reversed)
(472)
REVV
slp_ctrl[19]
G_SLP
(465)
REVC
(Available for S_SEL = 1)
|FS
(Available for S_SEL = 0)
Figure in [ ] is a value for ROMOFF = 1. [V = for 240 lines: V = for 272 lines] Figure in ( ) is a standard value. Figure 17-2: Horizontal Timing Chart for Horizontal Resolution 480 Dots (WEGA1/WEGA2)
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LCY-09033B-31
17.1.3. CLK
400
OutData
STHR
(STHL)
(403) stb_hl[16] * For S_SEL = 1, fixed to 5.
STB
gck_hl[40]
(363)
GCK
(CLS polarity is reversed)
(393)
REVV
slp_ctrl[16]
G_SLP
(387)
REVC
(Available for S_SEL = 1)
|FS
(Available for S_SEL = 0)
Figure in [ ] is a value for ROMOFF = 1. Figure in ( ) is a standard value. Figure 17-3: Horizontal Timing Chart for Horizontal Resolution 400 Dots (WQVGA)
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LCY-09033B-32
17.2. 17.2.1.
Example of Vertical Timing Vertical Timing for Vertical Resolution 480 Lines (WVGA)
For G_SEL = 0 DataIn Vsy Hsy REV G_SLP V_CNT |GSPOI GCK OG1 (dummy Line) OG2 (The 1st line on a display)
H1
H2
H3
H1
H2
H3
[1]
[2]
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LCY-09033B-33
For G_SEL=1 DataIn Vsy Hsy REV G_SLP V_CNT SPS CLS OG1
(dummy Line)
H1
H2
H3
H1
H2
H3
OG4
(Line No. 0)
OG5
(The 1st line on a display)
Hi
Hi Hi
MODE1 MODE2
Lo [1] [2]
* In the chart above, [1] and [2] refer to the interlacing two-pulse mode and normal mode, respectively.
Figure 15-4: Vertical Timing Chart for Vertical Resolution 480 Lines (WVGA)
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LCY-09033B-34
17.2.2.
For G_SEL = 0
DataIn Vsy Hsy REV G_SLP V_CNT |GSPOI GCK OG1 (dummy Line) OG2 (The 1st line on a display)
H1
H2
H3
H1
H2
H3
[1]
[2]
Page 34
OG2
(dummy Line)
OG3
(The 1st line on a display)
MODE1 MODE2
Hi
Hi Hi
Lo [1]
[2]
* In the chart above, [1] and [2] refer to the interlacing two-pulse mode and normal mode, respectively.
Figure 17-5: Vertical Timing Chart for Vertical Resolution 240 Lines (WQVGA/WEGA2)
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LCY-09033B-36
17.2.3.
Vsy Hsy REV G_SLP V_CNT |GSPOI GCK OG1 OG13 OG14
(dummy1)
[1]
[2]
OG15
(dummy2)
OG16
(The 1st line on a display) * In the chart above, [1] and [2] refer to the interlacing two-pulse mode and normal mode, respectively. Figure 17-6: Vertical Timing Chart for Vertical Resolution 272 Lines (WEGA1)
Page 36
LCY-09033B-37
Page 37
LCY-09033B-38 <2> If a long period (two years or longer) has elapsed for semiconductor devices that have been stored under in a normal storage environment and using normal storage methods, we recommend checking for solderability and rust on pins before using the semiconductor devices.
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LCY-09033B-39
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LCY-09033B-40
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LCY-09033B-41
21. Marking
This marking drawing shows the marking items and layout of the contents, and does not specify the typeface size of precise position.
Lead-free mark
* Construction of lot number In-house code Week assembled (2 digits) Year assembled (Last 2 digits)
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LCY-09033B-42
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LCY-09033B-43
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LCY-09033B-44
24. Carton
Page 44