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DEPARTMENT OF COMPUTER SCIENCE AND TECHNOLOGY IIT GUWAHATI

CS 223 : COMPUTER ORGANIZATION TECHNOLOGY


LAB REPORT FOR EXPERIMENT No. 2(a) : 4-bit Multiplier using Repeated Addition Method

By Faisal Ali (08010122) Kolli Rajendra (08010127) AND Rishibha Singh Netam(08010141)

Date of Experiment : 25th January & 1st February 2010 Date of Submission : 8th February 2010
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OBJECTIVE:
To design a 4-bit Multiplier using repeated addition method.

CIRCUIT DESIGN:
We have to design a 4-bit multiplier. This can be done by using repeated addition method. That is : A B = A + A + A + .... + A(B times). (1)

Thus, a multiplier designed on repeated addition method will essentially consist of a full adder. To store value of multiplicand, i.e. A, we need a register. Since, a full adder needs all its bit input values simultaneously, register A should be a Parallel In Parallel Out(PIPO) register. Since multiplicand(A) will be added n = multiplier(B) no. of times, we need an presettable Up/Down counter. And since, counter has to stop after n-times we need to use down mode of the counter. The output will be a 8-bit number. The block diagram of the circuit is shown below :

Figure 1: Block Diagram The block D is also a Parallel In Parallel Out(PIPO) register which stores the lower nibble(4 bit) of the product. The block C is an Up counter which is used to store the higher nibble of the product.

COMPONENTS USED:
1. IC 7495 Four Bit Shift/(PIPO) Register(2 Nos.) 2. IC 7493 Four Bit Up counter(1 Nos.) 3. IC 74191 Four Bit Presettable Up-Down Counter(1 Nos.) 4. IC 7483 Four Bit Full Adder(1 Nos.) 5. IC 7404 Hex Inverter(1 Nos.) 6. IC 7408 Quad Two Input AND Gates (1 Nos.)

CIRCUIT IMPLEMENTATION:
As mentioned earlier, since register A has to provide all the bits simultaneously to the full adder, hence, we chose IC 7495 for A as it is a PIPO register. The parallel-in operation facilitates loading the values easily into it. For this we give negative clock pulse to clk2 terminal. For parallel-in parallel-out operation we set the mode terminal to high. IC 7483 is a 4-bit full adder. It takes in two four bit values along with carry-in as input and returns four bits of sum and carry-out bit as output. Since it is a pure combinational circuit with no clock and enable in it and time lag being the propagation delay between input given and output produced, we cannot control the number of times A is added. We need to have another mechanism to control it. Now, the full adder provides four bits of sum and 1 carry-out bit. To store the sum, another register D is used, which is also a PIPO register because it will receive all the bits simultaneously and will transfer the bits stored in it simultaneously to input terminals of full adder as feedback. So IC 7495 was chosen for D as well. Here as well, for parallel-in operation the mode terminal is set to high. Also the loading operation takes place on a negative going edge of clk2. The clk1 is immaterial for parallel-in or parallelout operation and is left open. The carry-out generated by full-adder is stored in an up-counter which is IC 7493(block C). Whenever carry-out bit is high, the counter C is incremented by 1, hence, it represents the higher nibble of output product. This counter is a negative edge triggered counter with two clocks CKA and CKB, where for normal counting operations, CKB is connected to output Q4 . The negative edge clock pulse is given in CKA. IC 7493 has 2 reset terminals which are used to reset when both these terminals are made high

simultaneously. In all the other case it counts upwards. The IC 74191 is a presettable up/down counter. It has active low load terminal which can be used to load values into it. It is used to store information about multiplier i.e. B. The idea behind using it is that, the value of B will be loaded in the counter and it will be set to down count by keeping the U/D terminal high. Till the counter counts, i.e. till its output becomes 0000, the circuit will be enabled. As soon as output become 0000, the circuit will be disabled. To achieve this, the enable of counter is connected to min/max output provided by counter itself. Min/max normally remains low but whenever overow (i.e. 1111 incase of up-count) or underow (i.e. 0000 incase of down-count) occurs, it becomes high. Since the enable signal is active low, so the counter will count downwards till 0000 is reached. At this point min/max becomes 1. So the counter gets disabled and stops counting. To control the circuit using the counter B, we use the following idea: Since the full adder cannot be controlled, we try to control the loading of lower nibble in the register D. The idea is that we will load the output of full adder only B times in D. Thus we have to give B number of negative clock pulses to D. This can be achieved by ANDING inverse of output min/max of counter B with negative clock pulse. So clock pulse will reach D only when counter is at non zero value. We also AND load with this product to ensure that clock pulse will reach D only after counter has started counting (because counter counts when load becomes 1). Thus the expression for clk2 for D is: clk2 = clk (min/max) load There is another problem with the counter IC 7493 used for storing higher nibble of product. It cannot distinguish two consecutive high carry-out signals, i.e. it is not incremented on rst of the two consecutive high carry out signals. It is because it is a negative edge triggered counter. So a negative transition is necessary between two high carry out signals for correct incrementation. To solve this problem, the CKA of IC 7493 is given the following signal: CKA = clk (min/max) cout Thus, we give negative clock pulse (clk ) for the time till counter is enabled ((min/max) = 1) and when high carry out is generated. To generate (min/max) an inverter from IC 7404 is used. To produce the expressions of the clk2 for D and CKA for C three 2-input AND gates are used from IC 7408. This completes the circuit implementation.

CIRCUIT DIAGRAM:

Figure 2: 4-bit Binary Multiplier

OBSERVATIONS:
The multiplier circuit performed multiplication operations correctly, as seen from after given input from table. Sample Input A B 1111 1111 1010 1010 0111 0111 1000 0100 1000 1000 Output C D 1110 0001 0110 0100 0011 0001 0010 0000 0100 0000

Sometimes,the register D holds some garbage value when the circuit is switched on or when an operation has been completed. To ush out its contents input 0000 is given to its terminals and a negative clock edge is given to clk2 or disconnect and reconnect Vcc . Similarly to clear the contents of C, both of its reset terminals are given a positive pulse which resets C.

CONCLUSION:
Integer multiplication operations can be performed by using repeated addition method. This circuit uses this method. But repeated addition takes more time. Multiplication by any method involves repeated addition in some way. That is why multiplication is slower than addition. This circuit can be used as a part of 4 bit ALU with some modications. After making this circuit working of PIPO registers, counters and full adders have become very clear.

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