A Simulation Approach to Optimize the Electrical Parameters of a Vertical Tunnel FET

T.Naveen1 Mr.S.Ravi HOD(ECE)2 Master of Engineering Student1 Professor2 naveenkmr238@gmail.com1 ravi12333@yahoo.co.in2 SKP Engineering College, Tiruvannamalai, Tamilnadu, India

Abstract: Using two-dimensional device simulations, the electrical parameters of gated tunnel fieldeffect transistor (FET) are optimized with a SiGe delta doped layer in the source region. In order to prove the validity of the simulation models we compare simulation results with the experimentally realized tunnel FET on silicon and show that it gives a good match. It is shown that the incorporation of pseudomorphic strained-Si- Ge- layers leads to a significant performance increase. Furthermore, it becomes evident that the improvements are not a direct consequence of bandgap lowering but rather an indirect consequence of tunnel barrier width lowering. This leads to an asymmetry in the n- and the pchannel performance.
I. INTRODUCTION Room-Temperature negative differential conductance has been demonstrated in both direct bandgap materials and silicon three terminal devices. Based on similar band-to-band tunneling principle, tunneling transistors have been proposed as a possible replacement to the conventional metal-oxide semiconductor (MOS) fieldeffect transistor (FET). Recently, a vertically grown tunnel FET with p+-doped layer at the p-source has been experimentally demonstrated as a possible solution to the device scaling limits of the conventional MOSFET. Based on band-to-band tunneling from a heavily doped p-source to the inverted channel, the device showed nearly temperature independent, exponentially increasing input characteristics and perfect saturation in the output characteristics. Since tunneling in silicon is significant for a tunnel barrier width of less than 10 nm, the device was also free from shortchannel effects (SCE) like drain-induced barrier lowering (DIBL), and VT roll off. Furthermore, the reverse-biased p-in diode configuration provided a large source to drain barrier, and hence very low off-state currents of the order of 1 fA/m for a 100-nm channel length were observed. Thus, the tunnel FET showed promise to scaling into the ultrashort channel region. In the forward-biased case, the device showed resonant interband tunneling. Using twodimensional (2-D) computer device simulations, the nchannel vertical tunnel FET performance was then shown to further improve by means of replacing the heavily doped p+ silicon layer at source by a p+ SiGe layer. Since the bandgap, Wg, at the tunneling junction determines the tunnel barrier height, a lower Wg(with SiGe), results in a lower VT and higher ION. Further, it was observed that the subthreshold swing, S, of the tunnel FET is not governed by the thermal limit of 60 mV/decade at room temperature.

This is not unexpected, as the currents are tunneling currents which to a first approximation are independent of temperature. In this work, we investigate in detail, by means of 2-D computer simulations, the n-channel tunnel FET characteristics.

II. DEVICE STRUCTURE AND OPERATION The device consists of a three terminal gated p-i-n diode with a heavily doped 3-nm p+ layer at the p-source end as shown in Fig. 1. This heavily doped p + layer leads to the pinning of the Fermi level at source end. Applying a positive gate voltage, VGS, results in a n-inversion channel at the oxide-silicon interface. This causes the formation of a sharp p+ n+ tunnel junction between the heavily doped psource and the inverted channel. Thus, the gate directly controls the p+ n+ junction width which we define as the tunnel barrier width, . Applying a drain voltage, V DS, pulls the bands further down, thereby lowering . However, this happens only for low VDS as the tunnel widths soon saturate. The device input characteristics are determined by Zener tunneling of a gate-controlled reverse biased p+n+ junction. The output characteristics initially show an exponential behavior (for low VDS) and then perfect saturation. In order to optimize the electrical properties, the incorporation of pseudomorphic strained Si(1-x) Gex at source is investigated below. Since in this case, the valence band is raised relative to the conduction band, we show that the improvement in S is not a direct consequence of lowering Wg, but of lowering of the tunnel width, with increasing Ge content, x. .

III. SIMULATION TOOLS AND MODELS To model band-to-band tunneling generation rate, we have used the field dependent Kanes model. Though Kanes model has been derived for direct bandgap materials and band-to-band tunneling in silicon is phonon assisted, there are currently no commercially available tools to take care of that. However, Kanes model in Medici has been shown to give a good match for band-to-band tunneling in silicon tunnel FET at both low and high temperatures. In the following we also confirm good agreement between simulations with our experimentally realized tunnel FET on silicon. Since the source and drain regions are heavily doped, and tunneling is a strong function of bandgap, we also included the bandgap narrowing model for the simulations. For the simulations, we choose a fixed channel length, L=100 nm, an oxide thickness tox=2 nm, and doping in the n+-drain, p+-source and p+ layer to be 11020 cm-3 . The channel doping is kept at 11012 cm-3 n-type, corresponding to the unintentional doping level during molecular beam epitaxy (MBE) growth.

Thus, the tunnel FET performance is further expected to improve.

Equation (1) is similar to the well known Fowler Nordheim tunneling equation for band-to-band tunneling in silicon, assuming a triangular potential barrier. The tunneling current density J can be written as

where C and Eo are the constants corresponding to Akane and Bkane of (1). Similar expressions have also been derived analytically to explain the gate-induced drain leakage (GIDL) currents and for three terminal silicon tunneling devices based on band-to-band tunneling on similar GIDL phenomena. Depending on the bias conditions and device geometry, does lead to slight variations in the values of A kane and Bkane. However, the basic expression remains the same. In this work, we do not attempt to determine the accurate values of Akane and Bkane, nor to derive an accurate expression for the tunneling in silicon. Thus, using the existing model, we look at the tunnel FET characteristics and electrical parameters. III. THE SIMULATION APPROACH We start by writing the familiar Kanes model for band-to- band tunneling generation rate, GB2B, as a function of electric field, E and bandgap, Wg, across the tunneling junction. The current for the above mentioned GIDL phenomena is directly related to the gate bias, V GS, and the simulation thereby can be reduced to a one-dimensional problem. However, for the tunnel FET, we have a p-i-n diode configuration, and a direct approach to solve the problem requires a solution of 2-D Poissons equation as a function of both VDS and VGS in order to calculate the p-n junction formed by VGS for a given VDS. The depletion width of this p-n junction would then give the tunnel barrier width, . Coupled with the tunnel barrier height, W g, one will then need to solve Schrdingers equation using proper approximations and tools.

where Akane = (e2mo1/2)/(182) and Bkane = (mo1/2)/(2e) are in general functions of carrier effective mass mo, but are assumed to be constants in Medici, e.g., they do not vary with applied voltage. e is the electronic charge and is the Plancks constant. With pseudomorphic strained SiGe, the carrier effective mass is lowered. Thereby, leading to a higher tunneling probability and hence higher currents.

the problem from both of a VGS and VDS dependence to a function of VGS only. For low VDS the tunnel FET characteristics is a function of both VGS and VDS. However, as VDS is increased, the I-V characteristic reaches a perfect saturation, as the tunneling width saturates with increasing VDS.

This approach becomes more complicated, as the free carrier concentration (majority or minority carriers, depending on the gate bias) is nonuniform across the channel. Thus, the solution of 2-D Poissons equation itself would require an analytical as well as numerical approach. In Fig. 2 we show the simulated band diagrams for a tunnel FET at VGS =0 V, and VDS varying from 0 to 1.0 V along the cut-line A-B, close to the Si-SiO2 interface, as indicated in Fig. 1. It is clearly seen that VGS has little influence on the tunneling width, . It should be noted, that while the depletion width of the reverse-biased p-i-n diode increases with increasing VDS, the tunnel width, which is gate controlled is nearly independent of the drain bias. Hence, in the absence of a gate bias, the tunneling widths is controlled by VDS. Thus, the bulk p-i-n diode Zener breakdown limit is reached at relatively large VDS. This is primarily due to the channel resistance. If VGS increases, the channel resistance decreases and the VDS dependence cannot be neglected for low VDS. When VGS is applied, the tunneling width is controlled by the p+-n+ junction formed by the inversion channel and the p+-source region. The tunneling currents are then dominated by VGS at relatively low voltages. In Fig. 3 we show the simulated band diagrams for a tunnel FET at VDS=1.0 V as a function of VGS along the cut-line A-B. As can be seen the p-i-n diode junction fields are much less then the p+-n+ tunnel junction fields due to VGS. The lowering of with VGS is clearly seen. This accounts for the exponentially increasing input characteristics. In Fig. 4 we show the simulated total current (I DS) and the band-to-band tunneling component of the current, IB2B, as a function of VGS at VDS =1.0V. For low VGS, when the reverse biased p-i-n diode characteristics are dominant, we see a nearly constant IDS. This corresponds to the weak inversion region of the tunnel FET and only leakage currents are observed. The tunneling probability is low and thus the band-to-band tunneling current is also low compared to the

For ideal flat-band conditions it is exponentially varying from source to drain end, which itself is quite complicated to solve for a p-i-n diode. Further, a small application of a positive (or negative) VGS introduces a high degree of nonlinearity in carrier concentration. To solve the above problem, we start with a few assumptions to reduce

p-i-n diode leakage current. As VGS is increased further, we reach the strong inversion region and see that the device characteristics undergo a transition from that of a p-i-n diode to that of a tunnel FET.

doping concentrations, oxide thickness, tox and bandgap, Wg, the value of can be determined. In Fig. 7, we have plotted the simulated Log (IDS/VGS2) as a function of inverse VGS, for different values of VDS for the silicon tunnel FET. Apart from the linear behavior, we do see parallel shifts in the curve for low VDS (exponential region of output characteristics) and then the curves coincide (saturation region).

In Fig. 5 we have plotted the simulated E max across the tunneling junction as a function of both VGS (at VGS =1.0 V) and VDS (at VGS =1.0V >VT) for the 2-D device geometry (Fig. 1). As can be seen the p-i-n diode junction fields are much less then the p+n+ tunnel junction fields due to VGS. Thus, for low VGS when the reverse-biased p-i-n diode characteristics are dominant, we see a nearly constant Emax. As VGS is increased, Emax is seen to increase linearly with respect to VGS. Further, at constant VGS,Emax initially increases with respect to VDS and then reaches saturation. Thus, we look at the saturation case where we can assume the device performance to be independent of VDS. In the tunneling region Emax can be written as Emax=DVGS. It should be noted that D now is a function of VDS, oxide thickness,tox doping concentrations in the three regions, and channel length L. Thus, rewriting (1) in terms of VGS, for IDS GB2B, we get

We now turn to the influence of bandgap variation. Fig. 8 shows the simulated input characteristics of a nchannel vertical tunnel FET with Si(1-x)Gex in the 3-nm p+ layer at the source end, as a function of Ge content, x. When the p-i-n diode is reverse biased, we see leakage currents for small VGS, as the tunneling probability is not significant. However, as VGS is increased, tunneling probability and thus the current increases. Thereby leading to large exponentially increasing currents. As x increases, we observe a lowering of VT and increase in ION. The reverse-biased p-i-n diode leakage current, on the other hand,remains independent of x. IV. RESULTS AND DISCUSSION 1. THRESHOLD VOLTAGE VT

A quick way to justify this would be to compare the equation with experimental results. We define the normalized drain current as I DS/VGS2. Taking natural log of the above equation, we get

Thus, plotting Log (IDS/VGS2), with respect to 1/VGS, one would expect a straight line with a slope determined by Bkane/D, while the intercept giving Akane/D2 for constant Wg. In Fig. 6, we have plotted the normalized IDSas a function of inverse VGS from the experimental data for the silicon tunnel FET. It can be seen that the modified Kane model fits the experimental data quite well. Thus justifying the approach used. Further, for a given device parameters, like source/drain

As the tunnel FET output characteristics has only an exponential region (for low VDS) and a saturation region (for large VDS), we define the electrical parameters of the tunnel FET in the saturation region of operation. As the devices are operated at VDS=VDD (the supply voltage), this is not a disadvantage. In Fig. 9 we show the VT dependence on VDS. VT is calculated from the input characteristics by the constant current method. Since the tunneling current is nearly independent of L, we chose a source/drain current IDS which is only normalized with respect to the device width, W (for a conventional MOSFET, IDS is normalized with respect to W/L). Therefore at VGS=VT we define IDS/W = constant = 10-7A/m. With SiGe, the tunneling currents increase with increasing , and therefore VT is lowered significantly.

2.

SUBTHRESHOLD SWING, S

In Fig. 10 we show schematically the band diagram with pseudomorphically strained SiGe at the p-source end. As can be seen from the figure, there are two consequences: along with the bandgap lowering at the tunnel junction, we observe that the tunnel width is lower for SiGe then for Si at constant VGS. As the Ge content, x is increased, the valence band is raised accordingly. Thus, the tunnel width is further reduced. As we will show below, this lowering of tunnel width plays a significant role in determining the tunnel FET characteristics. Further, this also accounts for the significant lowering of VT as the Ge content, x, increases in SiGe tunnel FET. Taking the log of (3) and differentiating it with respect to VGS, we obtain S

Further, from (5), we also see that at constant V GS lowering of Wg would imply an increase in , that is degraded performance. To investigate this in more detail, in Fig. 11 we show S as a function of VGS for Ge content x varying from 0 to 0.5. The values of S are extracted from the simulated IDSVGS curve for each x value. The strong dependence of S on VGS is clearly seen. Also, for low VGS,we see that can be very small, tending to zero for all values of x. Further, the degradation of S with W g at constant VGS can also be seen. This is consistent with (5).

We see that S is directly proportional to VGS (strong dependence) and inversely proportional to W g (weak dependence). This would imply, that for very low VGS, one can get a very low S (large on/off ratio), ideally going to zero as VGS goes to zero. This can be explained in the following way. Considering a simple ideal case of a device with infinite channel length under flat band conditions. This would mean, a zero tunneling probability and only leakage currents. Application of a small VGS would lead to a small but finite tunneling probability. That is when the device undergoes a transition from that of a p-i-n diode to that of a tunnel transistor. Thereby, leading to an infinitely large subthreshold slope or infinitesimal swing.

V.

CONCLUSION [4] J.-H. Chen, S.-C. Wong, and Y.-H. Wang, An analytic three-terminal band-to-band tunneling model on GIDL in MOSFET, IEEE Trans. Electron Device. [5] K.-F. You and C.-Y. Wu, A new quasi-2-D model for hot-carrier band-to-band tunneling current, IEEE Trans. Electron Device. [6] S. Banerjee, W. Richardson, J. Coleman, and A. Chatterjee, A new three-terminal tunnel device, IEEE Electron Device Lett.
[7]

The vertical tunnel FET has been shown to have some remarkable properties and looks very promising as an alternative candidate to the conventional MOSFET for future technologies. Since the tunnel FET has a different current flow mechanism, it follows different scaling rules and parameter definitions then the conventional MOSFET. In this paper, we have presented a simple way to define and explain the observed properties by means of 2-D computer device simulations and compared it with our experimentally demonstrated tunnel FET. We have done some approximations which include the assumption that in the saturation region, the performance of the tunnel FET is independent of VDS. Since the tunnel FET characteristics are determined by the fields at the tunnel junction, these are dominated by the gate-induced p-n junction at the source end. However, for ultra short channel lengths ( <20 nm), this may no longer be valid as the p-i-n diode fields will become comparable. Further, for very thin oxide layers, the vertical gate fields may result in nonlinear dependence of E max as a function of VGS. However, in our 2-D device simulations, for L = 100 nm, and tox = 2 nm, we observe that the p-n junction fields are still dominant and yield a good match with the experimental data.

M. Takayanagi and S. Iwabuchi, Theory of band-toband tunneling under nonuniform electric fields for subthreshold leakage currents,IEEE Trans. Electron Devices.

[8] Scaling the vertical tunnel field-effect transistor with tunnel bandgap modulation and gate workfunction engineering, IEEE Trans.Electron Devices.

VI.

REFREFERENCES

[1] J. Koga, A. Toriumi, Three-terminal silicon surface junction tunneling device for room temperature operation, IEEE Electron Device Lett. [2] K. Bhuwalka, S. Sedlmaier, A. Ludsteck, C. Tolksdorf, J. Schulze, I. Eisele, Vertical tunnel field effect transistor, IEEE Trans. Electron. Devices. [3] J.-C. Gui, Y.-C. Lou, M. H. Chou, M. T. Wang, and F. Shone, A three terminal band-trap-band tunneling model for drain engineering and substrate bias effect on GIDL in MOSFET, IEEE Trans. Electron Devices.