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STRUCTURE NAME OF PRODUCT TYPE FUNCTION

Silicon Monolithic Integrated Circuit DC-AC Inverter Control IC

2ch control with Half-bridge Lamp current and voltage sense feed back control Sequencing easily achieved with Soft Start Control Short circuit protection with Timer Latch Under Voltage Lock Out Short circuit protection with over voltage Mode-selectable the operating or stand-by mode by stand-by pin Synchronous operating the other BD9885FV ICs BURST mode controlled by PWM and DC input Variable to standard Voltage for Lamp current Feed back

Absolute Maximum RatingsTa = 25

Parameter Supply Voltage Operating Temperature Range Storage Temperature Range Power Dissipation Maximum Junction Temperature
*

Symbol VCC Topr Tstg Pd Tjmax

Limits 15 -40+90 -55+125 850* +125

Unit V mW

Pd derated at 8.5mW/ for temperature above Ta = 25 (When mounted on a PCB 70.0mm70.0mm1.6mm)

Recommended operating condition

Parameter Supply voltage CT oscillation frequency BCT oscillation frequency Symbol VCC fCT fBCT Limits 5.014.0 20150 0.050.50 Unit V kHz kHz

REV. B

2/4 Ta=25VCC=7V
Parameter WHOLE DEVICE Operating current Stand-by current OVER VOLTAGE DETECT FB over voltage detect voltage STAND BY CONTROL Stand-by voltage H Stand-by voltage L Stand-by hysteresis TIMER LATCH Timer Latch voltage Timer Latch current OSC BLOCK OSC constant current OSC Max voltage OSC Min voltage MAX DUTY Soft start current IS COMP detect Voltage SS COMP detect voltage SRT ON resistance UVLO BLOCK Operating voltage Lock out voltage Operating voltage (External UVLO) Lock out voltage (External UVLO) FEED BACK BLOCK IS threshold voltage1 IS threshold voltage2 VS threshold voltage IS source current 1 IS source current 2 VS source current OUTPUT BLOCK Pch output voltage H Nch output voltage H Pch output voltage L Nch output voltage L Pch output sink resistance Pch output source resistance Nch output sink resistance Nch output source resistance BURST MODE BLOCK BOSC Max voltage BOSC Min Voltage BOSC constant current REG BLOCK REG output voltage REG source current VREF voltage VREF input voltage range COMP BLOCK Over voltage detect Under voltage detect PROTECT CLOCK Normal output voltage Protect output voltage VCOMPH VCOMPL VPH VPL 2.20 0.590 2.9 2.5 0.640 3.1 2.80 0.690 3.3 0.5 V V V V ICT VoscH VoscL MAXDUTY Iss Visc Vss RSRT VuvloH VuvloL Vuvlo1 Vuvlo2 Vis1 Vis2 Vvs Iis1 Iis2 Ivs VoutPH VoutNH VoutPL VoutNL RsinkP RsourceP RsinkN RsourceN VburH VburL IBCT VREG IREG Vref1 Vref2 1.35/RT 1.8 0.3 44 1.0 0.45 2.0 4.100 3.900 1.900 2.100 1.220 1.220 13.0 VCC-0.3 VCC-0.3 1.94 0.4 1.35/BRT 3.038 5.0 1.220 0.60 1.5/RT 2.0 0.5 46.5 2.0 0.50 2.2 200 4.300 4.100 2.000 2.200 1.250 Vref2 1.250 20.0 VCC-0.1 VCC-0.1 0.1 0.1 8 10 8 10 2.0 0.5 1.5/BRT 3.100 1.250 1.65/RT 2.2 0.7 49 3.0 0.55 2.4 400 4.500 4.300 2.100 2.300 1.280 1.280 1.5 27.0 1.0 0.3 0.3 16 20 16 20 2.06 0.6 1.65/BRT 3.162 1.280 1.60 A V V % A V V V V V V V V V A A A V V V V V V A V mA V V VREF=Open VREF=Applying Voltage DUTY=2.0V DUTY=0VIS=0.5V VREF=Open VREF=Applying Voltage fCT=60kHz fCT=60kHz fCT=60kHz Symbol MIN. 2.20 1.4 -0.3 0.10 1.8 0.5 Limits TYP. 11.0 2 2.40 0.25 2.0 1.0 MAX. 17.0 10 2.60 VCC 0.5 0.40 2.2 1.5 Unit Conditions

Icc1 Icc2 Vovf VstH VstL Vst Vcp Icp

mA A V V V V V A

CT=0.5V

System System

Isink = Isource Isink = Isource

10mA = 10mA 10mA = 10mA

fBCT=0.2kHz fBCT=0.2kHz

This product is not designed for normal operation with in a radio active environment.

REV. B

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Package Dimensions

(Include BURR 10.35)

Device Mark

BD9885FV

Lot No.
SSOP-B28 (Unit:mm)

Block Diagram
VCC REG VREF CT RT BRT BCT DUTY

Pin Description
Pin No. 1 2 Pin Name DUTY BRT BCT RT SRT CT GND FB1 IS1 VS1 FB2 IS2 VS2 VREF FAIL STB COMP1 COMP2 UVLO REG SS SCP P2 N2 PGND N1 P1 VCC Function Control PWM mode and BURST mode External resistor from BRT to GND for adjusting the BURST triangle oscillator External capacitor from BCT to GND for adjusting the BURST triangle oscillator External resistor from SRT to RT for adjusting the triangle oscillator External resistor from SRT to RT for adjusting the triangle oscillator External capacitor from CT to GND for adjusting the triangle oscillator GROUND Error amplifier output Error amplifier input Error amplifier input Error amplifier output Error amplifier input Error amplifier input Reference voltage for amplifier Protect clock output Stand-by switch Under, over voltage detect for 1ch Under, over voltage detect for 2ch External Under Voltage Lock OUT Internal regulator output External capacitor from SS to GND for Soft Start Control External capacitor from SCP to GND for Timer Latch FET driver for 2ch FET driver for 2ch Ground for FET drivers FET driver for 1ch FET driver for 1ch Supply voltage input

REG BLOCK

OSC

BOSC

DUTY BLOCK

3 4

STB

STB BLOCK

SYSTEMON/OFF UVLO BLOCK VCC UVLO

SS FB1 IS1 VS1 F/B BLOCK PWM BLOCK LOGIC BLOCK VCC SS CT OUTPUT BLOCK P1 N1

5 6 7 8 9

FB2 IS2 VS2 F/B BLOCK PWM BLOCK LOGIC BLOCK

VCC SS CT OUTPUT BLOCK P2 N2

10 11 12 13 14 15

PGND GND PROTECT BLOCK FAIL

ISNECE

error

COMP1

COMP2

SCP

SRT

16 17 18 19 20 21 22 23 24 25 26 27 28

REV. B

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NOTE FOR USE

When designing the external circuit, including adequate margins for variation between external devices and the IC.Use adequate margins for steady state and transient characteristics. Recommended Operating Range The circuit functionality is guaranteed within of ambient temperature operation range as long as it is within recommended operating range. The standard electrical characteristic values cannot be guaranteed at other voltages in the operating ranges, however, the variation will be small. Mounting Failures Mounting failures, such as misdirection or miscounts, may harm the device. Electromagnetic Fields A strong electromagnetic field may cause the IC to malfunction. . The GND pin should be the location within 0.3V compared with the PGND pin

BD9885FV has the short circuit protection with Thermal Shut Down System. When STB or Vcc pin re-supplied, They enables to cancel the latch. If It rise the temperature of the chip more than 170(TYP), It make the external FET OFF Absolute maximum ratings are those values that, if exceeded, may cause the life of a device to become significantly shortened. Moreover, the exact failure mode caused by short or open is not defined. Physical countermeasures, such as a fuse, need to be considered when using a device beyond its maximum ratings. About the external FET, the parasitic Capacitor may cause the gate voltage to change, when the drain voltage is switching. Make sure to leave adequate margin for this IC variation. On operating Slow Start Control (SS is less than 2.2V), It does not operate Timer Latch. By STB voltage, BD9885FV is changed to 2 states. Therefore, do not input STB pin voltage between one state and the other state (0.51.4V). The pin connected a connector need to connect to the resistor for electrical surge destruction. This IC is a monolithic IC which (as shown is Fig-1)has P+ substrate and between the various pins. A P-N junction is formed from this P layer of each pin. For example, the relation between each potential is as follows, (When GND > PinB and GND > PinA, the P-N junction operates as a parasitic diode.) (When PinB > GND > PinA, the P-N junction operates as a parasitic transistor.) Parasitic diodes can occur inevitably in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits as well as operation faults and physical damage. Accordingly you must not use methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND(P substrate)voltage to an input pin.
Resistance (PinA) (PinB) C Transistor (NPN) B E GND P P N P substrate GND Parasitic diode N P P substrate GND Parasitic diode (PinB) (PinA) B Parasitic diode GND

C E GND

Other adjacent components

Parasitic diode

Fig-1 Simplified structure of a Bipolar IC

REV. B

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Notes
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