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A Buck-or-Boost Converter Module With Embedded Inductor and Fast Current Limit
David Dening
AbstractThe operation and performance of a four-switch buck-or-boost converter are presented with peak efciencies greater than 90% under various loads. The converter is demonstrated in a module format where the single inductor is embedded within the laminated module substrate. Nominal inductance is 2 H and dc resistance is 120 m. The converter provides a fastacting current limit function when the sensed inductor current exceeds about 1 A. Index TermsBuck-or-boost, current limit, printed circuit board (PCB) inductor.

I. INTRODUCTION

Fig. 1. Buckboost power train architecture is a cascade of the two converters with a single inductor.

HIS module was the result of two development programs. The rst was a concept design for a dcdc converter. The goals were to explore the implementation of a feature rich converter that could provide a step-up/step-down output potential independent of a sagging battery voltage. The module substrate resulted from an effort to embed the inductor for a dcdc converter within a printed circuit board (PCB) laminate material substrate. The converter is sized for a WCDMA power amplier (PA) requiring about 2 W of dc power. The intention was to track the average PA power, and thus simplify the control loop strategy. The converter paper by Midya et al. [1] provided inspiration for this design, but the approach was modied to meet the design requirements. Several features were incorporated into the converter. The input battery voltage can range from 2.5 to 5.0 V. There is a low voltage lock out available; pull PWR low to reset. The output voltage may be set from 1 to 5 V independent of the battery voltage. An analog VSET (0.5 to 2.0 V) controls the output voltage, or a six-bit binary control may be used. Finally, a fast current limit switches to a constant current mode at about 1 A through the inductor; the control reverts to a constant voltage mode when the current is reduced. This paper presents the design details of the buck-or-boost converter and the embedded inductor. The measured performance is followed by a Lessons Learned section. II. POWER TRAIN ARCHITECTURE The buck-or-boost power train architecture shown in Fig. 1 is a buck converter followed by a boost converter with a single

Manuscript received February 17, 2009; revised April 6, 2009 and June 12, 2009; accepted July 13, 2009. Date of current version December 6, 2011. Recommended for publication by Associate Editor A. Rufer. The author is with RF Micro Devices, Greensboro, NC 27409-9421 USA (e-mail: ddening@rfmd.com). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2009.2028425

common inductor. The inductor is about 2 H resulting from a trade-off among inductance, size, and resistance for the boost mode. Although not shown in the gure, the P-FET M4 must be paralleled by an additional N-FET to pass the output current while in the buck mode. At lower output voltages, the headroom to maintain M4 in an ON state disappears. The auxiliary N-FET across M4 is ON while in the buck mode and OFF in the boost mode. The gure illustrates one of the fundamental problems with a buckboost converter design, i.e., there are six high current connections to the semiconductor die. With a goal of minimizing resistance, switching converter die are typically laid out with the power paths at the die edge to allow multiple bond wires. Fig. 2 shows the bonding diagram for this die in the module and illustrates a solution to multiple high current paths. The power devices are laid out across the bottom half of the die as shown in the schematic. P-FETs are on top and twice the size of the N-FETs (at the bottom). The VDDD switching input path comes onto the die from the left and passes to the ground at the bottom. The Vout path comes out of the right side of the die and uses the N-FET (boost converter) ground at the bottom. The two inductor connections use long bond wires from the die center passing over the control circuitry, as shown at the top of the gure. Why use the long bond wires for the inductor connection? First, added bond wire inductance is a plus even though it is small compared to the external inductor size. The inductor connections could be routed to the chip top in multiple metal layers, and the bond wires are connected at the die edge except for the added resistance and noise coupling to the control circuitry. It would take a wide trace (see the ground connections) to handle the current. Plus, the voltage on these inductor nodes will be switching. Getting the inductor signals up in the air minimizes coupling, and the multiple bond wires reduce the series resistance. Finally, as long as bond wires do not cross or pass over another bond-pad, there is no assembly problem.

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Fig. 2.

Module bonding diagram shows how power paths and control signals are routed.

III. CONTROL LOOPS Controlling a buck-or-boost converter without anomalous operation at the crossover point is difcult, especially if the efciency is to be maintained [2], [3]. High efciency means that only one pair of power FETs should switch during each clock period. The problem arises in providing a clean transition between modes and the elimination of mode chatter [4][6]. Fig. 3 shows a conceptual block diagram of the control loop. The clock generation circuitry produces a single sawtooth analog ramp signal and a strobe synchronized to the start of each ramp cycle. The strobe resets both setreset ipops and forces both output P-FETs (M1 and M4) to be turned on at the start of each clock cycle. The rst comparator to switch when comparing the sawtooth ramp to its duty cycle error signal toggles the ipop, locks out the other ipop, and turns ON the appropriate N-FET while turning OFF the corresponding P-FET. This condition remains until it is reset by the strobe at the beginning of the next cycle. During the design cycle, there was difculty in stabilizing the inner control loops since the quiescent current in all the op-amps and analog blocks was being minimized to improve the low current efciency of the converter. Reduced quiescent current has a direct effect on the op-amps unity gain bandwidth. Various types of compensation networks were tried for voltage feedback. The output of the current sense circuit was tried. The accumulated phase shift (time delay) due to the reduced op-amp bandwidth was too large for an acceptable phase margin in the loop.

Switcher stability is provided by operating in continuous mode and using duty cycle feedback. The ideal duty cycle for a buck converter is represented by the following relation between the input and output voltages: D = Vout /Vin . And, for a boost converter D = 1 (Vin /Vout ). (2) (1)

Instead of using the output voltage in a feedback loop, an analog representation of the duty cycle is employed. The most compelling argument for the duty cycle feedback is that the output voltage is directly determined by the duty cycle. Feedback from the output voltage contains a phase shift that accumulates due to the LC lter and the op-amp that would be used in the compensation network. While there is a phase shift due to the RC ltering of the duty cycle, the phase shift associated with the output voltage feedback that accumulates from the LC lter, the compensation network, and the associated op-amp is eliminated. There appears to be a net reduction in the phase delays when using the duty cycle feedback approach. The duty cycle feedback is represented by the RC lters that connect the set reset ipop Q outputs back to the integrator inputs. This approach will lead to a slower transient response since the output voltage error is fed into the loop through an integrator. The rst convention chosen in the control loop design was turning on the P-FETs at the beginning of each cycle. This has

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Fig. 3.

Control system for the buck-or-boost converter uses a digital and an analog lockout to prevent mode chatter.

implications that may not be recognized initially. The buck error voltage is compared to the sawtooth signal to determine the duty cycle. If the error voltage is below the minimum of the sawtooth, the comparator never switches. At the beginning of the next cycle, both P-FETs are reset to ON and the battery is connected to the output. The ramications are that as the output voltage is reduced in the buck mode, it suddenly snaps back to the battery potential. A minimum buck duty cycle (output voltage) is required to avoid this issue. A duty cycle limit function was added to the clock generator/comparator combination. The same circuitry also provided a boost duty cycle limit to avoid the output voltage trying to reach innity (the boost duty cycle approaching 1). The other control loop convention was in dening the top of the sawtooth to be the transition point between the buck and boost modes. In the buck mode, the duty cycle error starts low on the sawtooth for lower output voltages above the minimum and moves up for higher voltages, switching later in the cycle. When the duty cycle error voltage is above the peak sawtooth voltage, the buck mode never switches and the P-FETs could stay ON continuously with the output voltage at the battery voltage. In the boost mode, the duty cycle error starts at the top of the sawtooth where the output voltage is at the battery voltage and moves down to the limiting duty cycle and the maximum output voltage. The asymmetric use of the sawtooth signal between the buck and boost modes requires a sign change in the control loops between the two modes. This is implemented by an inverting integrator for the boost loop and a non-inverting integrator for the buck loop. The sign change also means that there is a common input control convention for both duty cycle loops. The external loop that provides the setpoint for the duty cycle loops

is represented by the integrator with MEASURE and SET as its inputs. A dead zone in the external loop output is provided by the current sources that generate an offset through the buck duty cycle integrator. The external loop integrator compensates for this offset. During a control transient that causes a transition between the buck and boost modes, this offset will produce an integration time delay as the converter settles to its new state. This is a small price to pay for a smooth transition. Dening the top of the sawtooth as the transition between the buck and boost provides the second lockout mechanism to avoid mode chatter. If the desired output voltage has the buck duty cycle error above the sawtooth range, the integrator will be pinned at the positive supply rail. Likewise, if the desired output voltage is below the battery voltage, the boost duty cycle integrator output will be pinned at the positive supply rail. Thus, a comparison of these two integrator outputs may be used to determine if the converter is in the buck or the boost mode. This system works best if the internal controller voltage swing is limited. The internal analog control power supply is provided by a low-dropout regulator set at about 2.4 V. Finally, the digital outputs of the control block are buffered to increase the drive capability while going to the FETs in the power train. As part of the buffering, a break-before-make logic block as shown in Fig. 4 is added to prevent both of the P-FET/NFET pairs from ever being turned on simultaneously. The FETs in the power train are capable of passing currents in excess of 1 A. Under normal operation, the FET current is limited by the inductor, but larger shoot-through spikes are possible if both devices are momentarily ON. The power train drive uses the brute force logic in charging and discharging the gate capacitances. A scaling factor of 8 or

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the attenuated inductor signal, provide dc gain, and further attenuate the switching signals. The third op-amp is congured as a differential low-pass lter to remove the common mode bias offset in the inductor, provide an additional dc gain, and further attenuate the switching signals. V. FAST CURRENT LIMIT In Fig. 3, the control loop is shown to use an integrator function to provide the overall control of the converter. If the output voltage is to be controlled, a measure of the output voltage (a resistor divider) and an externally provided voltage set-point are used for the loop inputs. If the output current is to be controlled, a measure of the current is needed along with a current set-point signal. The most common application of a dcdc converter is to provide an output voltage determined by some set-point control. The voltage is to be maintained to the best of the controllers ability. If the current increases beyond limits, what is to be done? The precedent used in power supplies is to limit the current to some preset value. However, if both the voltage and current loops are controlled by integrators, the slew rate can cause delays and voltage/current glitches during the handover. The classic technique to rapidly slew an integrator-based control loop to a new regulating point is to pre-charge or quickly add charge to the integrator capacitor. Fig. 6 illustrates this technique in implementing a fast current limit. The comparator chooses the most negative signal of the control loop outputs, i.e., the one not pinned at the positive power supply rail. In the gure, the switch bank is set for the voltage loop control and the voltage control integrator is passed to the output, while the voltage integrator capacitor is connected between the op-amp output and the inverting input. While the voltage integrator is controlling the converter, the capacitor for the current control loop is disconnected (as an integrator) and pre-charged between the voltage integrator output and the current control set-point. With no integrator capacitor, the current control op-amp acts as a comparator and exhibits a faster slew rate determined by its internal compensation capacitor. As long as the measured current is below the set-point, the current loop op-amp output (now comparator) will be pinned at the positive power supply rail. If the current measure rises above the set-point, the current op-amp comparator will swing negative below the voltage level of the voltage control loop and the comparator will toggle the switch bank. At this point, the current loop integrator capacitor will be reconnected as a current loop integrator with just the right pre-charged potential to provide a smooth transition. When an integrator is operating correctly, both the inverting and non-inverting op-amp inputs have the same potential. Thus, the current set-point should be the desired potential for one terminal of the capacitor, and the voltage loop output should be the desired potential for the current loop output. After the transition to current control, the voltage loop integrator capacitor will be connected between the current integrator loop output and the voltage set-point for pre-charging, should the current measurement ever drop below the constant current

Fig. 4. Break-before-make logic sequence prevents shoot-through when switching the large FETs in the power train.

10 increasing device sizes was employed for each of the six successive logic stages from the output of the controller to the nal drive for the power train devices. The break-before-make logic was applied recursively to the devices in the inverters in Fig. 4 that drive the nal N-FET and P-FET. This was done to avoid shoot-through in the inverters that are 1/10 the size of the output device. For larger converters, an efciency improvement may be realized in recovering some of the drive energy [7]. IV. INDUCTOR CURRENT MEASUREMENT Determining the current in a dcdc converter can be a difcult design task. Since only the average current for a current limit was desired, the voltage drop across a sense resistor was chosen as the measurement approach. To eliminate the efciency loss due to an additional resistance in the power train, the parasitic inductor resistance was employed as the sense resistor. The downside of this approach is that the converter designer may lose control of the inductor resistance and the current limit sensitivity. This is not a problem for a converter module approach. A summary and examples of other possible current measurement approaches are presented by Forghani-Zadeh et al. [8][11]. Selectively applying low-pass ltering and dc gain can extract the average voltage drop across the inductors dc resistance. The schematic shown in Fig. 5 illustrates the technique. First, the two inductor signals are attenuated by a factor of 3 to get the dc-coupled signals down to the voltage supply range of the op-amps. In buck mode the input of the inductor switches between VBATT and ground and in boost mode the output of the inductor switches between VOUT (higher than VBATT ) and ground. The rst of the low-pass ltering could be supplied by the capacitors between the resistor divider taps and the ground. However, more attenuation of the switching clock can be obtained by connecting these same capacitors between the two resistor divider taps as shown in the gure. An additional 6 dB of attenuation is gained using the same capacitor area by this approach. Note that the switching signal coupled with the nonswitching leg is removed by the common mode rejection of the op-amp. Selectively providing stages of dc gain and high frequency attenuation keeps the op-amps from saturating. The rst two opamps are congured as non-inverting low-pass lters to buffer

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Fig. 5.

DC voltage drop across the inductor is obtained by selectively low-pass ltering and amplifying the differential voltage signal.

Fig. 6.

Fast current limit is possible by pre-charging the capacitors in the voltage and current integrator control loops.

set-point. The voltage control op-amp now becomes a comparator (with the output at the positive power rail) monitoring the output voltage and the voltage set-point. VI. INDUCTOR DESIGN The goal of the inductor development project was to produce an inductor for a switching power supply embedded within the PCB laminate for the module. The starting point is a four-layer laminate. A spiral coil pattern was preferred over the solenoid style [12] to maximize the inductance while minimizing the resistance. The top and bottom foil patterns are dedicated to signal routing, while the two central layers are dedicated to producing the required inductor turns. Plated through-vias supply the vertical interconnections. Construction starts using a double-sided 6 mil core with 2 oz. copper. Through-vias connecting the inductor coils are drilled and plated, increasing the copper layers to 3 oz., and the coil patterns are then etched. A ferrite paste layer is screened on

over the coils (top and bottom) to provide a magnetic path for the eld in the coils. The ferrite paste uses a water-based epoxy emulsion mixed with various size ferrite particles to provide an optimum ferrite lling. The epoxy provides a B stage cure that was compatible with the PCB lamination process. A thin pre-preg and nal copper foil were laminated to create the top and bottom routing layers. Through-vias were drilled and plated, and the top and bottom foil patterns were etched. The layout pattern for the module in Fig. 7 shows how the inductor coils are arranged for maximum inductance. Ground connections for the converter die are shown passing down through the center of the inductor from the die ag on the top foil layer (red). The module is 310 mils square. The size is determined by the inductance (2 H) and the coil trace width to minimize the series resistance. The tan region surrounding the coils is the mask for the ferrite pattern. Passing plated vias through the ferrite pattern is not an issue since the ferrite is non-conducting. The cross-section of a completed module shown in Fig. 8 illustrates how the ferrite material surrounds the thick copper

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Fig. 7.

Layout drawing for the module shows the 11-turn inductor (5.5 turns on each layer).

Fig. 8.

Cross-section of the module shows how the ferrite surrounds the inductor coils to provide an unbroken magnetic path.

used for the coil turns and provides a path for the magnetic eld. Conning the magnetic eld (through the ferrite layers) provides a 5 inductance improvement over bare coils. The inductor for a switching power supply must not saturate while providing the dc current required from the supply. The inductance must also be maintained at the switching frequency of the supply. Fig. 9 shows the performance of the embedded inductor. The inductance is 1.7 to 1.8 H at a nominal 1 A inductor current. Current spikes beyond 2 A do not saturate the ferrite. Switching frequencies at 10 MHz do not degrade the inductance, although losses in the ferrite and the skin effect losses in the copper turns increase the effective AC resistance. The dc resistance of the coil is 120 m. The dc voltage drop (from the dc resistance) is the parameter measured for the current limit function. The skin effect and ferrite losses decrease the efciency.

Fig. 9. Inductor for a dcdc converter must maintain its inductance while passing the converter output current (dc bias current) without saturating the ferrite.

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Fig. 12. Efciency of a buck-or-boost converter peaks when the output voltage is closest to the input supply (V in = 3.0 V for this measurement).

Fig. 10. Photograph of the completed (but un-encapsulated) module shows how the wire bonds carrying the inductor current can pass across the analog portion of the die.

Fig. 11. Transfer function of the buck-or-boost converter is independent of load until the mode switches to constant current.

VII. MODULE PERFORMANCE A photograph of the completed module is shown in Fig. 10. Multiple 1.0 F 0402 capacitors are ganged together for input and output ltering. The photograph shows how the bond wires bridge across the top of the die from the converter power train to the inductor. The cross- sections of the bond wires can be seen above the die in Fig. 8. The measured transfer function of the converter module is shown in Fig. 11. There is little effect due to the output load until the current exceeds the limit threshold. The current limit is controlled by the inductor current, not the converter output current, so that actually the limit value will also depend on the input supply voltage and duty cycle. The minimum duty cycle limits the lowest output voltage. Note that state (000000) is trapped and used as a partial power down. The state is the

binary pattern applied to pins D0D5 (see Fig. 2) when using the digital mode to control the converter output voltage. When the all zeros or (000000) pattern is detected, most of the internal converter functions are shut off to conserve power. The efciency curves for a converter can provide hints to any instability. The data presented in Fig. 12 were measured with various resistive loads at an input voltage of 3.0 V. The switching clock was set at 1.6 MHz for the measurements. The peak efciency was 91% when driving the 5 load which occurs at the transition point between the buck and boost. Assuming that all the converter losses are resistive and that they are all due to the inductor and the series P-FETs, M1 and M4 allow a conservative estimation of the P-FET ON resistance. At the buck/boost transition point, the converter input current equals the output current (ignoring the controller overhead). The output voltage is 2.73 V (91% of 3.0 V) and the current through the 5 load is 546 mA. The total resistance of the two P-FETs and the inductor is then 494 m. After accounting for the inductor resistance the P-FET ON resistance is about 187 m. The NFET switches are expected to have a similar resistance based on device scaling. The transition between the buck and boost modes occurs when the output voltage matches the input voltage. A sudden drop in efciency at this point would indicate mode chatter or even an oscillation. An additional evaluation of the converter stability is provided by the unloaded quiescent current as shown in Fig. 13. The nominal analog and switching requirements are about 4 mA. The extra quiescent current between 0.5 and 2.7 V and above 3.0 V has the same shape as the simulated ripple current in the inductor. These measurements were conducted using the digital mode, so the current at 0. V (state 000000) reects the current required for the band gap and other circuits needed for a rapid start-up from idle mode. The power pin (PWR) can be used for complete shut down. The sudden drop in the quiescent current at the buckboost transition (3.0 V in Fig. 13) has an interesting origin. The maximum buck voltage is a straight pass-through of the input voltage minus the IR losses. As the output is approaching this point, the buck duty cycle error voltage is getting close to the top of the sawtooth signal (see Fig. 3). In fact, the two signals get so close that the comparator cannot respond to trigger the latch and the

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Fig. 13. Shape of the quiescent current plot appears to be determined by the ripple current excursions in the inductor.

Fig. 15. Converter output (top trace) is shown with a triangle waveform applied to the VSET analog input (bottom trace). The input signal offset was chosen to cause the converter to transition between the buck and boost modes.

Fig. 14. Converter output (top trace) is shown when a square wave transient is applied to the VSET analog input (bottom trace). The input signal offset was chosen to cause the converter to switch between the buck mode (bottom half of the output trace) and the boost mode (top half of the output trace) to illustrate that both modes are stable with an input step transient.

remainder of the power train. In the next cycle, the buck duty cycle error integrates lower and the power train is triggered. Instability begins when the power train is triggered with every other sawtooth cycle. This is characterized by a slight increase in noise at the converter output. See [4] for a more detailed explanation of this phenomenon. The output voltage is close to the input supply and the converter only provides a slight perturbation. At the data point where the output voltage is exactly 3.0 V, the quiescent current drops again. At this point, a number of switching cycles are skipped and the power train has the P-FETs ON most of the time. From these data points, it appears to take 2 mA to provide the switching energy for the power train. Transient stability for a step change in the input control signal VSET is shown in Fig. 14. The input control signal offset was selected to force the converter to transition between the buck and boost modes. The top half of the output trace is in the boost mode, while the bottom half is in the buck mode. A dead

Fig. 16. Converter output is shown in the buck mode (top trace) while a square wave current load is applied to the output as indicated by the bottom trace.

time indicated by the plateau in the step transition occurs, while the input voltage control integrator transitions the dead zone offset between the modes, and the duty cycle integrators switch between the buck and boost modes. During this interval the PFETs in the power train are in the ON state. Fig. 15 presents the results of a similar measurement, but using a triangle input wave form to slow the transition between the buck and boost modes. As can be seen in the gures, the converter makes the transition without chatter or oscillation. The effect of a transient load condition is shown in Fig. 16 for the buck mode and in Fig. 17 for the boost mode. A differential current of about 300 mA was generated from a buck converter power stage with a 10 resistor connecting to the output of the buck or boost converter module. A 3.0 V supply powered both

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into the control section. The analog supply was derived from the digital (power train) supply through a low-pass RC lter on the module. Not placing the analog ground pin next to the analog supply pin on the die forced the routing of the analog supply line between the VDDD power buss and the die ag (see Figs. 2, 7, and 10). This was not a problem per se since the bond wires could be used as a jumper, but it forced a break in the ground connection of the input lter capacitors. The input lter capacitors were still grounded through a via to the ground on the back side of the module, but this routing caused that ground line to be longer than the path used for the output lter capacitors. Compare the lter cap ground paths on the left and right sides of Figs. 7 and 10. This extra line inductance for the input lter capacitors caused noticeable ringing in the boost mode. One module, constructed without the closest input bypass capacitor so that bond wires could connect the input capacitor ground pads and the die ag ground, did not exhibit this problem.
Fig. 17. Converter output is shown in the boost mode (top trace) while a square wave current load is applied to the output as indicated by the bottom trace.

IX. CONCLUSION A stable buck-or-boost converter was designed and fabricated using a single inductor with efciencies above 90%. The control system was congured to optimize efciency at the buck/boost transition point by allowing the operation of only one pair of switch devices per cycle. The converter transitions smoothly between the buck and boost modes without chatter and under various load and slew rate conditions. Under excess load conditions, the converter quickly limits current to a preset value. The converter can be used as a packaged part with an external inductor [14], [15], but was demonstrated with a 2 H embedded inductor fabricated within the module substrate. REFERENCES
[1] P. Midya, K. Haddad, and M. Miller, Buck or boost tracking power converter, IEEE Power Electron. Lett., vol. 2, no. 4, pp. 131134, Dec. 2004. [2] B. Sahu and G. A. Rincon-Mora, A low voltage, dynamic, noninverting, synchronous buckboost converter for portable applications, IEEE Trans. Power Electron., vol. 19, no. 2, pp. 443452, Mar. 2004. [3] M. Gaboriault and A. Notman, A high efciency, noninverting, buck boost DCDC converter, in Proc. Nineteenth Annu. IEEE Appl. Power Electron. Conf. Expo. (APEC 2004), vol. 3, pp. 14111415. [4] R. Paul and D. Maksimovic, Smooth transition and ripple reduction in 4switch non-inverting buckboost power converter for WCDMA RF power amplier, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS 2008), May 1821, pp. 32663269. [5] X. Ren, X. Ruan, H. Qian, M. Li, and Q. Chen, Dual-edge modulated four-switch BuckBoost converter, in Proc. IEEE Power Electron. Spec. Conf. (PESC 2008), Jun. 1519, pp. 36353641. [6] L. Jiana, Z. Menglian, W. Xiaobo, and Y. Xiaolang, Design of high efciency buckboost controller IC, in Proc. 9th Int. Conf. Solid-State Integr.-Circuit Technol., 2008, pp. 20122015. [7] Z. Zhang, W. Eberle, P. Lin, Y.-F. Liu, and P. C. Sen, A 1-MHz highefciency 12-V buck voltage regulator with a new current-source gate driver, IEEE Trans. Power Electron., vol. 23, no. 6, pp. 28172827, Nov. 2008. [8] H. P. Forghani-Zadeh and G. A. Rincon-Mora, Current-sensing techniques for DCDC converters, in Proc. 45th Midwest Symp. Circuits Syst. (MWSCAS 2002), Aug. 47, vol. 2, pp. II-577II-580. [9] A. M. Patel and M. Ferdowsi, Advanced current sensing techniques for power electronic converters, in Proc. IEEE Vehicle Power Propulsion Conf. (VPPC 2007), Sep. 912, pp. 524530. [10] F.-F. Ma, W.-Z. Chen, and J.-C. Wu, A monolithic current-mode buck converter with advanced control and protection circuits, IEEE Trans. Power Electron., vol. 22, no. 5, pp. 18361846, Sep. 2007.

circuits. In Fig. 16, the buck-or-boost output voltage was set to 2.0 V, so current ows in and out of the converter as indicated by the power train drive voltage shown in the lower trace. In Fig. 17, the output voltage was set at 3.4 V, so current is always owing out of the converter module. VIII. LESSONS LEARNED Details are discovered after every design that would be corrected on a redesign or would not have been included had they been anticipated. This design had its fair share. For example, the buck-and-boost FET pairs in the power train were segmented with separate drivers, so that banks could be switched to a high impedance output state in an attempt to improve low-power efciency. The P-FETs banks were 3.2, 3.2, and 6.4 cm for a 12.8 cm total width. The N-FETs are half the P-FET size, i.e., 6.4 cm total width. An automatic bank selection based on inductor current was implemented that included appropriate hysteresis. The conclusion was that segmenting the FETs does not signicantly improve the low-power efciency and can even cause stability chatter. However, other investigators have employed segmentation using an open loop control with an improved low current performance [13]. Operational ampliers using a differential FET pair as the input stage can have a signicant offset voltage. This was noticed in the band gap variations, but also in the current sense circuit. The maximum dc voltage drop across the inductor is in the range of 120 mV at 1 A. Without careful device sizing in the amplier, the op-amp could contribute an error that was a substantial fraction of the desired measurement. An external 270 k resistor between Vref and Iref sets the clock frequency to about 1.6 MHz. This is a good trade for ripple and efciency. A redesign could pull that resistor onto the die. The nal lesson learned was related to the die bond-pad locations. The converter was designed to use a separate analog supply and analog ground to avoid coupling switching noise

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[11] W.-R. Liou, M.-L. Yeh, and Y. L. Kuo, A high efciency dual-mode buck converter IC for portable applications, IEEE Trans. Power Electron., vol. 23, no. 2, pp. 667677, Mar. 2008. [12] M. Yamadaya, M. Owa, and H. Matsuo, Small-size boost type DC DC converter with the tiny embedded inductor, in Proc. IEEE 30th Int. Telecommun. Energy Conf. (INTELEC 2008), Sep. 1418, pp. 15. [13] O. Trescases, W. T. Ng, H. Nishio, M. Edo, and T. Kawashima, A digitally controlled DCDC converter module with a segmented output stage for optimized efciency, in Proc. IEEE Int. Symp. Power Semicond. Devices ICs, 2006, pp. 14. [14] M. H. Lim, J. D. van Wyk, F. C. Lee, and K. D. T. Ngo, A class of ceramic-based chip inductors for hybrid integration in power supplies, IEEE Trans. Power Electron., vol. 23, no. 3, pp. 15561564, May 2008. [15] E. C. W. de Jong, B. J. A. Ferreira, and P. Bauer, Toward the next level of PCB usage in power electronic converters, IEEE Trans. Power Electron., vol. 23, no. 6, pp. 31513163, Nov. 2008.

David Dening received the B.S. degree from Clarkson College of Technology in 1967, the M.S. and Ph.D. degrees in physics from Rensselaer Polytechnic Institute in January 1973 and June 1973, respectively, and the M.S.E.E. and Ph.D. degrees in electrical engineering from Virginia Polytechnic Institute in 1975 and 1984, respectively. In 1978, he joined the (then General Electric) Electronics Laboratory, where he was engaged in research on high-temperature ICs and later designed MMIC ampliers. In 1996, he joined RF Micro Devices, Greensboro, NC, where he is currently a Senior Staff Engineer. His current research interests include analog, digital, and RF IC circuit design using CMOS, HBT, and PHEMT technologies. His designs include switch mode power supplies, 100 V monolithic charge pumps, drivers for MEMS switches, and numerous RF ampliers.