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Questions Question 1 Animation: addressing 16 8 bit ROM memory This question consists of a series of images (one per page)

) that form an animation. Flip the pages with your ngers to view this animation (or click on the next button on your viewer) frame-by-frame. The following animation shows how setting the input (address) switches in particular combinations selects individual memory cells inside the ROM, resulting in data stored within those cells to appear at the output (data) lines. Questions to ponder: What is the organization of this particular ROM chip? (e.g. 256 4, 1k 1, etc.) What is the relationship between the hexadecimal numbers stored inside each cell and the alphabetical characters shown below the chip? What code is being used to represent these characters? What character is represented by the hexadecimal code 20? (Hint: this code is used twice in the sequence shown.)

VDD VDD
0

ROM memory IC
1 2 3

0 A0 4D 0 A1 0 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

0 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

1 0 1 1 0 0 1 0

VDD VDD
0

ROM memory IC
1 2 3

1 A0 4D 0 A1 0 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

0 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

1 0 1 0 0 1 1 0

Me

VDD VDD
0

ROM memory IC
1 2 3

0 A0 4D 1 A1 0 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

0 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

1 0 1 1 0 1 1 0

Mem

VDD VDD
0

ROM memory IC
1 2 3

1 A0 4D 1 A1 0 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

0 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

1 1 1 1 0 1 1 0

Memo

VDD VDD
0

ROM memory IC
1 2 3

0 A0 4D 0 A1 1 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

0 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

0 1 0 0 1 1 1 0

Memor

VDD VDD
0

ROM memory IC
1 2 3

1 A0 4D 0 A1 1 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

0 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

1 0 0 1 1 1 1 0

Memory

VDD VDD
0

ROM memory IC
1 2 3

0 A0 4D 1 A1 1 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

0 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 0 0 1 0 0

Memory

VDD VDD
0

ROM memory IC
1 2 3

1 A0 4D 1 A1 1 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

0 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

1 0 0 1 0 0 1 0

Memory I

VDD VDD
0

ROM memory IC
1 2 3

0 A0 4D 0 A1 0 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

1 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

1 1 0 0 1 1 1 0

Memory Is

10

VDD VDD
0

ROM memory IC
1 2 3

1 A0 4D 0 A1 0 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

1 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 0 0 1 0 0

Memory Is

11

VDD VDD
0

ROM memory IC
1 2 3

0 A0 4D 1 A1 0 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

1 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

1 0 1 0 1 0 1 0

Memory Is U

12

VDD VDD
0

ROM memory IC
1 2 3

1 A0 4D 1 A1 0 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

1 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

1 1 0 0 1 1 1 0

Memory Is Us

13

VDD VDD
0

ROM memory IC
1 2 3

0 A0 4D 0 A1 1 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

1 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

1 0 1 0 0 1 1 0

Memory Is Use

14

VDD VDD
0

ROM memory IC
1 2 3

1 A0 4D 0 A1 1 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

1 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

0 1 1 0 0 1 1 0

Memory Is Usef

15

VDD VDD
0

ROM memory IC
1 2 3

0 A0 4D 1 A1 1 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

1 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

1 0 1 0 1 1 1 0

Memory Is Usefu

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VDD VDD
0

ROM memory IC
1 2 3

1 A0 4D 1 A1 1 A2
4

65
5

6D
6

6F
7

72
8

79
9

20
10

49
11

1 A3 73
12

20
13

55
14

73
15

65

66

75

6C

D0 D1 D2 D3 D4 D5 D6 D7

0 0 1 1 0 1 1 0

Memory Is Useful
le 03244

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Answers Answer 1 Nothing to note here!

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Notes Notes 1 The purpose of this animation is to let students study the behavior of this switch circuit and reach their own conclusions. Similar to experimentation in the lab, except that here all the data collection is done visually rather than through the use of test equipment, and the students are able to see things that are invisible in real life.

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