XII INTERNATIONAL CONFERENCE AND SEMINAR EDM2011, SECTION III, JUNE 30 - JULY 4, ERLAGOL 143

Power Consumption Reduction for Configuration

SRAM of Field Programmable Gate Arrays
Denis V. Matyushin
1
, Sergei I. Kurganskii
2
1
Joint Stock Company "Engineering and Design Center "Electronics", Voronezh, Russia
2
Voronezh State University, Voronezh, Russia
Abstract This article describes a method of reducing power
consumption for configuration SRAM cells. Modification of
the SRAM cell is performed taking into account special
characteristics of FPGA configuration memory.
Characteristics of the cells are summarized.
Index Terms Leakage current, asymmetric SRAM, FPGA
I. INTRODUCTION
HE CLASS of Field Programmable Gate Array
(FPGA) is interesting because it is used as a template
for the implementation of the scheme necessary to the
user. Initially the chip consists of arrays of logic blocks,
multipliers and memory blocks that are not connected to
each other. The specific functionality of logic blocks and
their connection are determined after the configuration
process. Due to this, the user may at any time repeat the
configuration process with other data and implement
other device on the basis of the FPGA. Such flexibility is
ensured by using memory cells as configuration elements.
A number of chip transistors and their performance
grow with reduction of process standards. In order to keep
the microcircuit power generally within an acceptable
range, supply voltage and threshold voltage of MOS
transistors are to be reduced. The subthreshold leakage
current increases exponentially with decreasing threshold
voltage. Due to leakage currents for submicron processes
(180 nm or less) consumed power may make a significant
portion of the total power. Drain current in the
subthreshold region is described by [1]:
|
|
.
|

\
|

(
(

|
|
.
|

\
|
=
t
off th gs
t
ds
ds
n
V V V
V
I I
v
v
exp
exp 1
0
, (1)
where
2
0
2
t
s
si
NDEP q
L
W
I v
u
c
= , (2)
ds
V is drain-source voltage, is gate-source voltage,
is threshold voltage, is offset voltage, which
determines the channel current at ,
gs
V
th
V
off
V
0 =
gs
V
t
v is thermal
voltage and equal to , q kT / is carrier mobility,
and are channel width and length, respectively,
is electron charge,
W L q
si
c is silicon permittivity, is
channel doping concentration,
NDEP
s
u is surface potential.
Given that a number of transistors in the configuration
memory may reach 6070% of the total quantity of chip
transistors, leakage current flowing through the
configuration RAM may make a significant portion of
power consumption in the static mode.
II. THEORY
The conventional SRAM cell is composed of two cross-
coupled inverters and two address transistors. The gates
of address transistor are connected by the wordline (WL),
which is charged to zero for hold and to one for read/write
operations. Drains of address transistors are connected to
the complementary bitlines (BL and nBL), which, in their
turn, are connected to inputs of sense amplifier for
reading or to data drivers for writing. The circuitry of the
memory cell based of the 180 nm technology is shown in
Fig. 1. Width of all transistors is chosen minimum and
equal to 0.42 m. Channel length of transistors is shown
in the Figure. When holding the value "0" leakage
currents flow through transistors P1, N2 and N3. Lines
BL and nBL are usually charged to supply voltage.
The main static characteristics of the cell is static noise
margin (SNM), which is defined as the minimum direct
current (DC) voltage noise applied to all nodes in the
scheme that allows to flip state of the cell. The graphical
representation of noise margin is shown as a butterfly
diagram (see Fig. 2). The transient response of the left
inverter shall be constructed: the X axis displays input
voltage, the Y axis displays output voltage. It is
overlapped by the transient response of the right inverter
rotated by 90 degrees. The resulting diagram consists of
two regions, indicating that there are two stable states of
the cell.
Fig. 1. Schematic 6T SRAM cell and leakage current in zero hold mode.
T
ISBN 978-1-61284-795-5/11/$26.00 2011 IEEE
XII INTERNATIONAL CONFERENCE AND SEMINAR EDM2011, SECTION III, JUNE 30 - JULY 4, ERLAGOL 144
Fig. 2. SRAM static noise margin in modes: a) hold, b) read, c) write.
DC noise voltage shifts the characteristic of the left
inverter along the X axis, and right along the Y axis. The
voltage, at which an area degenerates into a point, is
SNM.
Graphically, it can be shown as follows: a square with
the largest size of side is inscribed in each of the domains.
The length of the smaller side will be static noise margin
of the cell. For a symmetric cell area of zero and one, and
therefore the noise margin, are equal. Insertion DC noise
voltage sources are shown in Fig. 3.
Fig. 3. A flip-flop comprised of two inverters. Static noise voltage
sources V
n
are included: a) hold mode, b) read mode.
In the hold mode address transistors are disabled and do
not affect SNM of the cell. In the read mode the address
transistors are open and connected to lines BL and nBL,
which are charged to the supply voltage. This leads to a
shift in the zero level and a smaller noise margin (see
Fig. 2b). In the write mode BL/nBL lines are charged to
opposite values, so the left and right inverters are
connected to different levels through open address
transistors. The characteristics should not be overlapped.
III. RESULTS
According to the results of simulation in HSPICE for
cell voltage 1.8 V and temperature of +125C, static noise
margin is equal to 618 mV in the hold mode, 297 mV and
650 mV in the read-write modes, respectively. Leakage
current flowing through the cell is equal to 1105 pA.
The application of techniques aimed at reducing
leakage currents that are used in RAM arrays or cache
memory, such as reducing supply voltage in the hold
mode [3] or floating ground [4], is impossible. Change in
supply voltage or ground level would reduce the
amplitude of the signals on the DATA and nDATA ports
of cell, and this is unacceptable, because these ports are
directly connected to the logic blocks and the
interconnection matrix and changing levels will lead to
slowdowns or fault FPGA core.
While maintaining signal levels leakage current may be
reduced by increasing length of the transistor channel.
Given that the configuration data are loaded into the
FPGA each time at the beginning of the work cycle and
remain unchanged until power down or reconfiguration it
is sufficient to optimize the cell for storing one value.
Increasing channel length of transistors P1, N2 and N3
will increase reading and writing times of the cell;
however, performance of the cell is of no importance
when used as a configuration cell. Writing into the cell
occurs once after power-up. Reading from a cell is
required for testing of chips in production process and for
verifying the configuration memory in the work cycle.
The main contribution to the overall current
consumption is made by leakage current of the N2
transistor. The reasonable approach to selection of
channel length will be the minimum point of the product
of leakage current value by channel length. This
expression follows from (1) at : 0 =
gs
V
|
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.
|

\
| +

(
(

|
|
.
|

\
|
=
t
off th
t
ds
t
s
si
n
V V
V NDEP q
W f
v
v
v
u
c

exp
exp 1
2
2
(3)
although the channel length is not included explicitly
in (3), at the transition to the long-channel model
threshold voltage and carrier mobility
L
th
V depend on
the effective channel length ; therefore, the
characteristic is not linear. This dependence is shown in
Fig. 4. Thus, let us increase the N2 channel length up to
0.36
eff
L
m. It is reasonable to increase channel length P2
until the following equation is satisfied:
0 0 leakP
leakP
leakN
leakN
I
I
I
I
= , (4)
MATYUSHIN and KURGANSKII: POWER CONSUMPTION REDUCTION 145
where , are leakage currents of transistors
with minimal channel length. Length of the channel P1
will be 0.26
0 leakN
I
0 leakP
I
m; length of the address transistor N3 will
be 0.7 m. This will reduce hold mode SNM up to
565 mV, read mode SNM up to 130 mV. Leakage
current will decrease to 428 pA.
Fig. 4. Production leakage current on channel length versus channel
length.
To restore SNM in the read mode to the previous level it
is necessary to decrease N4 strength. Increasing its length
to 0.7 m restores the noise margin level in read mode to
305 mV, but leads to decreasing noise margin in the write
mode to 230 mV. Strengthening of the transistor N3 will
restore write mode SNM without affecting read mode
SNM. With decreasing channel length of the transistor N3
to 0.4 microns, the noise margin in the write mode rises to
308 mV, leakage current to 481 pA. The further
strengthening of N3 is not required, since the static noise
margin in the read mode remains to be the limiting factor.
The comparative diagrams of noise margin are illustrated
in Fig. 5. The numerical values and the final sizes of the
SRAM cell are summarized in Table I.
Fig. 5. Comparative SNM diagrams of conventional and modified cells.
TABLE I
COMPARATIVE CHARACTERISTICS OF SRAMCELLS
Parameter Conven-
tional cell
Modified
cell
Hold mode SNM, mV 618 565
Read mode SNM, mV 297 305
Write mode SNM, mV 650 308
Hold zero leakage current, pA 1105 481
Hold one leakage current, pA 1105 969
N1 channel length, um 0.18 0.18
N2 channel length, um 0.18 0.36
N3 channel length, um 0.28 0.4
N4 channel length, um 0.28 0.7
P1 channel length, um 0.18 0.26
P2 channel length, um 0.18 0.18
IV. CONCLUSION
Thus, application of the asymmetric cell reduces current
consumption by 2.3 times at holding 0 value and
slightly reduces current consumption at holding 1 value.
In this case SNM level remains unchanged in read/write
modes and slightly decreases in the hold mode. Given that
a number of zeros in the configuration bitstream is at least
80% and may reach 90% or more, the current consumed
by FPGA configuration memory may be reduced
approximately by half mainly due to application of the
asymmetric cell. This is especially important in the FPGA
static mode.
REFERENCES
[1] Morshed, T. H. BSIM4.6.4 MOSFET Model User's manual /
T. H. Morshed, W. M. Yang, M. V. Dunga, X. J. Xi, J. He, W. Liu,
Kanyu, M. Cao, X. Jin, J. J. Ou, M. Chan, A. M. Niknejad, C. Hu //
Department of Electrical Engineering and Computer Sciences
University of California. http://www-
device.eecs.berkeley.edu/~bsim3/bsim4.html
[2] Seevinck, E. Static-Noise Margin Analysis of MOS SRAM Cells /
E. Seevinck, F. List, J. Lohstroh // IEEE Journal of Solid-State
Circuits. Oct. 1987. Vol. SC-22, No. 5. pp. 748-754.
[3] Qin, H. SRAM Leakage Suppression by Minimizing Standby
Supply Voltage / H. Qin, Y. Cao, D. Markovic, A. Vladimirescue,
J. Rabaey // Proc. of 5th International Symposium on Quality
Electronic Design. 2004. pp. 55-60.
[4] Agarwal, A. A Single-Vt Low-Leakage Gated-round Cache for
Deep Submicron / A. Agarwal, H. Li, K. Roy // IEEE Journal of
Solid-State Circuits. Feb. 2003. Vol. 38, No 2. pp. 319-328.
Denis V. Matyushin was born in
Voronezh/Russia in 1979. He received the
diploma of Engineer of Electronics in 2000
from the Voronezh State Technical University
and the Physics and Technology Faculty. Now
he is employee of Joint Stock Company
"Engineering and Design Center "Electronics"
as a ASIC/FPGA designer. His current research
interests include FPGA architecture design.
Sergei I. Kurganskii is a specialist in
designing of programmable logic. He graduated
from the Physical Department of the Voronezh
State University (VSU) in 1976. He received a
Candidate of Science Degree in 1981 and
Doctor of Science Degree in 1997. Since 1998
he has worked as a full professor of the Solid
State Physics and Nanostructures Chair in the
VSU.