Main Memory 64kB Block size 8 bytes Direct Mapped Cache 32 lines How is the 16 bit mem add

d divided Into what line a byte with add below be stored 0001 0001 0001 1011 1100 0011 0011 0100

Main Memory 64kB Block size 8 bytes Two way set associative 32 lines How is the 16 bit mem add divided Into what set a byte with add below be stored 0001 0001 0001 1011 1100 0011 0011 0100

Field Programmable Gate Arrays

LRU: replace the line in CM that has not been used for the longest time, i.e., the least recently used (LRU) line.

LRU replacement can be implemented by attaching a number to each CM line to indicate how recent a line has been used. Every time a CPU reference is made all of these numbers are updated in such a way that the smaller a number the more recent it was used,

i.e., the LRU line is always indicated by the largest number.

Assume the initial state of the 4 CM lines is shown below (the underlined line is the least recently used):

After line B is referenced,

After line C is referenced,

After line D is referenced,

If line E not currently in CM is needed, the LRU CM line A labeled by the largest number 3 will be replaced

A Field Programmable Gate Array (FPGA)

is similar to a PLD, PLDs are generally limited to hundreds of gates, FPGAs support thousands of gates. They are especially popular for prototyping integrated circuit designs. Once the design is set, hardwired chips are produced for faster performance
Field Programmable Gate Arrays (FPGAs) are divided into two major categories: 1. SRAM-based FPGAs 2. Antifuse-based FPGAs

Structure of FPGA

Field Programmable Gate Arrays (FPGAs)

- Field programmable gate array is a VLSI module that can be programmed to implement a digital system consisting of tens of thousands of gates.

Field Programmable Gate Arrays (FPGAs)

- Field programmable gate array is a VLSI module that can be programmed to implement a digital system consisting of tens of thousands of gates. - An FPGA consists of an array of three kinds of programmable devices. . Logic blocks, either combinational and or sequential . Interconnection points (switches) and . Input/output blocks In addition there are wires grouped in vertical and horizontal channels.

Each logic modules can be programmed to implement several switching functions Logic modules used in FPGA are used as look-up tables (LUTs) or multiplexers On chip latches ( memory cells) set with bit patterns to define the chip configuration, called SRAM-FPGA Volatile, programming information not preserved after chip powered down.

Memory cells are loaded during programming phase with binary values that represent

SRAM- FPGA
-Programmable switch -Programmable Multiplexer -Look-up table -Flip-flop

LOOK UP TABLE
X1
0/1 0/1 0/1 0/1

X2

LOOK UP TABLE
X1
1 0 0 1
X1 X2 0 0 0 1 0 1 F 1 0 0 1

1 1

X2

1 0 1 0

AB Y C AB

1 0 1 0

LUTs

A Configurable Logic Block

( CLB)

-These are programmable blocks . -May consists of LUTs,several Multiplexers controlled by memory cells, Flip-flops - Provide outputs.

Programmable interconnects consists of metal segments and programmable switch points used to provide routing of signals -Direct interconnections between horizontal and vertical CLBs -General purpose interconnects consists of vertical and horizontal wiring segments between switch matrices. -Long vertical and horizontal lines span the whole CLB array , providing means for transmitting signals to large number of destinations.

Xilinx Virtex family Configurable Logic Block (CLB) SRAM-based FPGA

SRAM CONTROLLED SWITCH

 One-Digit BCD Adder

One digit BCD adder - The system has nine inputs and five outputs - Performing a modulo16 addition and then a correction factor - First adder produces v = ( x+y+cin ) mod 16 u = 1 if ( x+y+cin) > = 16 = 0 otherwise

T = 1 if u = 1 or v > = 10 = 0 otherwise

System function is S = ( x+y+cin) mod 10 Cout = 1 if (x+y+cin) > = 10 = 0 otherwise

The condition u = 1 or v > = 10 corresponds to the switching function t = u +v3v2+v3v1

s3 = v3 EXOR t (v 2+v1) s2 = v2 EXOR tv1 s1 = v1 EXOR t s0 = v0 cout = t

 One-Digit BCD Adder

Basic Design steps

Design Entry- Schematic entry or behavioral description using HDL. Implementation- Partitioning the design into sub modules that can mapped into CLBs, placement of sub modules onto chips, and routing of signals to connect the sub modules.

Design Verification : which uses in circuit testing, simulation and timing analysis.

Behavioral Description Netlist Map to FPGA blocks Bit Stream Download to FPGAs

FPGA Programming