Ultra Low Voltage High Speed Dierential CMOS Inverter

Omid Mirmotahari and Yngvar Berg

Nanoelectronic Systems (NANO) Department of Informatics University of Oslo, Norway omidmi@ifi.uio.no

Abstract. In this paper we demonstrate and analyse how the dierential ultra low voltage inverter can be designed in order to achieve the most benecial conditions concerning speed, stability and EDP. Keywords are: Ultra Low Voltage (ULV), Floating-Gate (FG) and High-Speed.

Introduction and Background

The transistor is one of the key components that has made possible the plethora of portable electronic gadgets that enriches our everyday life. In the last decade major developments have made low power designs a key objective in addition to speed and silicon area. The consumer market has dramatically increased demands for sophisticated portable electronics such as laptop computers and cellular phones. Portable electronics drive the need for low power and low voltage due to a limited budget set by a xed maximum battery mass, while on the other hand demand for high-performance electronics regarding speed. One of the established merit is the value of EDP, the value is a product of a quadratic dependent delay times the current dissipation during evaluation. In order to lower the energy consumption several approaches exists. One of the most fundamental and eective approach is to lower the supply-voltage [1, 2]. Furthermore, it is called ultra low voltage ULV when the supply voltage is reduced to hundreds of millivolts [3, 4]. However, the scaling of the supply-voltage has the adverse effect of the performance of the design concerning speed. The main challenge is to obtain high speed at as low as possible supply-voltages. To maintain good evaluation response time at ultra low supply-voltages, the threshold voltages of the transistors must also be reduced. Unfortunately, this requires a change in the CMOS fabrication process. Multiple-Vdd technique has been proposed for low voltage high performance circuits designs [5] without changing the fabrication process. Floating-gates (FG) have also been proposed for ultra low voltage and low power (LP) logic [6]. Unfortunately for oating-gates, modern process face signicant gate leakage due to the thin oxide. A ULV oating-gate inverter employing a frequent recharge technique has shown good properties in achieving high speed at ultra low voltages [7]. Even though the ULV gate has shown good performance it also has limitations due the leakage at the semi-oatinggates (SFG). A dierential ULV gate has been proposed by including a keeper
L. Svensson and J. Monteiro (Eds.): PATMOS 2008, LNCS 5349, pp. 328337, 2009. c Springer-Verlag Berlin Heidelberg 2009

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function [8] which is argued to have the speed of an ULV but the stability as a standard CMOS. In this paper we examine the performance aspects of the dierential ULV inverter compared to both standards CMOS and to ULV oating-gate inverter. The main goal is to achieve higher evaluation response even when lowering the supply-voltage. The dierential ULV gate can have a dierent recharge reference voltage, not necessarily Vdd and Gnd, but a higher and lower voltage. The outline of this paper is as follows: in section 2 the dierential ULV gate is thorough presented and the key advantages are pointed out. Section 3 elaborates on the aspects of speed, stability and EDP of the ULV di both compared to CMOS and to ULV oating-gate inverter. Finally, the paper concludes with a discussion on the achieved results. The simulation results demonstrated throughout this paper were obtained by simulation produced in a STM 90nm process environment provided by Cadence.

Dierential ULV Inverter

The ULV oating-gate inverter has been evaluated and demonstrated to achieve an improvement for speed of more than a seven times better than CMOS, while the dierential ULV, hereby referred to as ULV di, has approximately ve times better than CMOS [8]. For the case of ULV inverter, showed in Fig. 1, the leakage plays an crucial role in limiting the operating frequency. The main problem is illustrated with a simulation for Vdd = 250 mV in Fig. 2. The arrows point out two problems, though, both related to each other. The arrow pointing down to the dashed line (the semi-oating-gate of the nMOS) is displaying the problem of not completely turning o the nMOS transistor.

Ci
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Pinv

Ci

pSFG

Nr
Out
In

In -

Pr
nSFG nSFG

Ci

Ninv

Ci

(a) ULV design resembles a UV-floating-gate inverter

(b) ULV design with focus on the output regarding to supply-voltage

Fig. 1. The gure illustrates the ultra low voltage gate. Both designs are logically and electrically equivalent. In (a) the design clearly shows the inverter and the biasing/recharging of the oating-gate, while (b) is designed to emphasise that the output is not directly connected to the supply voltage.

Pr

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0.25

0.2 Signals throufh ULVdiff at Vdd = 0.250 V

Problem

phi In Out pSFG nSFG

0.15

0.1

0.05

0.05 50 100 150 200 250 Time ns 300 350 400 450

Fig. 2. Simulation result demonstrating the signal propagation through the ULV inverter for a Vdd = 250 mV. The main problem for the ULV gate is the leakage and pointed out by the arrows in the plot.

Secondly, the arrow pointing up to the solid line, emphasise the leakage problem both related to the semi-oating-gate of the pMOS leakaging charge and the current ow through the nMOS. In order to completely comprehend how the ULV di is solving the leakage problem a simple description of the signal propagation is given below. Referring to the illustration of the ULV di, presented in Fig. 3, and describe the signals for the gate to the left. PRE The semi oating-gates, nSFG and pSFG, are set to Vdd and Gnd, respectively. The recharge clock, , is turning o. The input signal, In1, is at Vdd /2 and Out is Vdd /2. The gate is said to have obtained the equilibrium state. DUR In1 starts on a falling transition. nSFG and pSFG see this change with an attenuation factor of Ci /Ctot , where Ctot is the total capacitance seen from the semi oating-gate including the parasitic capacitances. The output drivers, Pinv and Ninv , starts pulling the output node up. While evaluating, the semi oating-gates are leaking, for nSFG the leakage is from (Vdd V) to Gnd, while for pMOS it is (Gnd - V) to Gnd. This leakage is the one responsible for the ULV gates low stability.

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Ci
pSFG

Ci

Pinv1

Pinv2

pSFG

Nr Pk
Out1

Pk Nr

In1

In2

Out2

Pr Nk
nSFG

Nk P r

Ci

Ninv1

Ninv2

nSFG

Ci

Fig. 3. The ultra low voltage dierential semi oating-gate inverter including a keeper function, Pk and Nk , is illustrated. Transistor sizes are kept minimum and matched, the input capacitances are scaled relative to obtain the same voltage attenuation for both nSFG and pSFG.

0.25

0.2 Signals throufh ULVdiff at Vdd = 0.250 V

0.15

Solved
0.1

0.05

0.05 50 100 150 200 250 Time ns 300 350 400 450

Fig. 4. Simulation results of the ULV di demonstrating the signal propagation for Vdd = 250 mV. As illustrated by the arrows the challenge of the leakage is solved due to the keeper function included in the design of ULV di.

phi In Out pSFG nSFG

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POST When In1 has reached its rail (Gnd), the output drivers are still evaluating the change and try to pull up the output to the rail. It is here the keeper, Nk , steps in and holds the nSFG to Gnd and makes sure that the output is as close to the rail as possible and hold the value until next recharge period. Note that the Nk is active and not Pk , due to the falling transition. Simulation results in Fig. 4 demonstrate the clear advantage of the keeper function. From the results it is possible to spot the change in output due to the keepers function. For this particular case the keeper steps in at approximately 100.15 ns.

Performance Aspects

The real potential of the ULV di can be extracted by exploiting the use of recharge voltage. Looking back to the previous section, during recharge the recharge transistors, Pr and Nr , are asserting a reference voltage to the SFGs. This reference voltage, hereby called Vddrecharge or Gndrecharge , would in a way

30 25 20 15 10 5 0 0.4 0.35 0.3 0.2 0.25 0.2 0.5 0.15 Vdd (V) 0.6 Recharge vdd (V) 0.4 0.3

Fig. 5. Simulation results for the ULV di for dierent Vddrecharge and Vdd demonstrating the speed of the evaluation relative to standard CMOS. The lower Vddrecharge the higher increase in the evaluation time for the ULV di.

ULVdiff relative to CMOS

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0.07

0.55

0.01
0. 15
0 0.2
5 0.2 5 0.3 0 0.5 0 0.7 90 0. 1.20 1.60 2.00 3.10 4.00 5.20 7.00 8.80 12.6 16.1 20.8
0.4 0.35
0.2 0.3

0.5

0.45 Recharge vdd (V)

0.4

No

is

p in arg em

m ble ro

0.35

0.3

0.25

d ase Inre
0.2

S MO to C tive rela elay d

0.15 0.15

0.2

0.25 Vdd (V)

0.3

Fig. 6. Simulation results for the evaluation time for the ULV di relative to the CMOS. The white area is where the ULV di is improved by the factor given in the plot. The plot also species the disadvantages in the darker areas.

ULVdiff leakage (pA) during evaluation

650 600 550 500 450 400 350 300 0.4 0.35 0.3 0.25 0.2 0.15 Vdd (V) 0.6 0.5 Recharge vdd (V) 0.4

Fig. 7. Simulation results demonstrating the leakage during evaluation time for the ULV di. As evident there is an linear increase, but the levels is given in pA.

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Leakage current (log)

4 0.35

0.4

3 0.6 0.5 0.4 0.3 0.2 Recharge vdd (V) 0.15 0.2 0.25

0.3

Vdd (V)

Fig. 8. Simulation results demonstrating the lekage through the output drivers of the ULV inverter. The results are logaritmic plotted in order to better visualize the data. The current is measures in nA, actually compared to ULV di there is a factor of 4 decades.

ULVdiff stability relative to CMOS (log)

2 1.5 1 0.5 0 0.35 0.5 0.6 0.5 0.4 0.3 0.2 Recharge vdd (V) 0.15 0.2 Vdd (V) 0.25 0.3 0.4

Fig. 9. Simulation results for the ULV di and its stability given by the deviation from the rails relative to CMOS are presented. Interesting points are the local minimum spots visible, which demonstrates better stability obtained than CMOS.

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ULVdiff EDP relative to CMOS (log)

1.5 1 0.5 0 0.5 1 1.5 0.4 0.35 0.3 0.25 0.2 0.15 Vdd (V) 0.6 0.5 Recharge vdd (V) 0.4 0.3 0.2

Fig. 10. Simulation result for the EDP value of the ULV di given as a function of Vdd and the recharge oset, Vddrecharge

alter the threshold behaviour of the respective transistors, Pinv and Ninv . The transistors would become more or less sensitive to the input transition depending on the voltage asserted on the SFGs. In the case of a Vddrecharge > Vdd the ULV di would react faster to a input transition, thus increasing speed. Take one specic environment for example Vdd = 250 mV, Vddrecharge = 300 mV, the dierence in behaviour is described as follows: PRE The semi oating-gates, nSFG and pSFG, are set to Vddrecharge and Gndrecharge , respectively, that is a change of 50 mV from previous. The recharge clock, , is turning o. The input signal, In1, is at Vdd /2 and Out is Vdd /2. DUR In1 starts on a falling transition and makes a change at the nSFG and pSFG with an attenuation factor (same as previous). The voltage at the SFG are becoming Vddrecharge - V for the nMOS, while for pMOS is Gndrecharge - V. The main dierence here is that both SFGs have a higher voltage which makes the transistors more on compared to previous. POST When In1 has reached its rail (Gnd), the output drivers are still evaluating the change and try to pull up the output to the rail. At the nal state, for this particular case, the pMOS has an lower voltage compared to previous, which makes the Pinv more on and resulting higher evaluation speed. The keeper transistor, Nk , holds the nSFG at Gnd. Taking the description above literally one can can expect that asserting as high Vddrecharge voltage as possible would give best outcome in terms of speed. Mainly due to the fact that the Pinv is turned more on while the Ninv is completely

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turned o. Unfortunately, it is not protable to increase the Vddrecharge for any given Vdd . The main challenge is set by the keeper transistors ability to react fast enough and turn o the right output transistor before is makes pull away the output. The higher Vddrecharge is, all the more diculties the keeper transistors have in turning o the right transistor. The ULV di can be controlled by to parameters, one the Vdd and the other one Vddrecharge , to obtain the optimal speed given certain noise-margin. The simulation results presented in Fig. 5 shows the speed improvements relative to standard CMOS inverter. As is evident the speed decreases exponentially by asserting lower Vddrecharge than Vdd . A contour plot based on the same data is presented in Fig. 6 to further illustrate the boundaries both in terms of noise margin and speed improvements. The ULV di has a constant leakage and is actually found to be equal to a single nMOS transistor where Vgs = 0V and Vds = Vdd independent of the Vddrecharge . This comparison for a falling input transition is due to the keeper transistor Nk .Unfortunately, this is not the case for the ULV and would lead to a narrower operational area compared to the ULV di. Simulation results verify the ULV dis leakage and is demonstrated in Fig, 7. The leakage of the ULV gate is dependent both of the Vddrecharge and the Vdd , and found to increase dramatically with the Vddrecharge as presented in Fig. 8. The stability of the gates can be regarded as the deviation from the rails. From the previous plots of leakage it is natural to expect the ULV gate to have an decreased stability as increased Vddrecharge . For the ULV di the stability should be approximately constant, due to the constant leakage and relative to CMOS. Simulation results show optimal points in the surface plotted in Fig. 9. The optimal points are local minimum points and show a linear function for the optimal stability related to both Vddrecharge and Vdd . The results which has not been available due to the noise-margin are set to a maximum. In Fig. 10 the EDP of the ULV di is plotted as function of both Vddrecharge and Vdd .

Conclusion and Discussion

The main goal of this paper has been to elaborate on the timing details and performance in general for the ULV di both in comparison to the ULV gate and to standard CMOS: The fundamental alternation of the performance is given by imposing an oset to the semi-oating-gates. Simulation results presented in this paper show how the speed of the ULV di is altered as a function of the oset, Vddrecharge . At best it is possible to obtain improvements as high as 16 times better for ULV di compared to CMOS. Concerning about the stability of the ULV di it has also been shown by simulation to have a very low and constant leakage. The stability is oset dependent, but the optimal points are found to be 1.5 times better. Compared to the ULV the dierential solution has overall better performance and based on the results provided in this paper we conclude that the keeper function is indispensable.

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References
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