Contents

International Conference on Computer Systems and Technologies - CompSysTech2003

Using the MSSP Module of PIC16F87X Microcontroller in Master Mode for I2C Communications
Nina Bencheva, Volodya Tsonev, Yoana Ruseva
Abstract: The paper considers the utilizing of the master synchronous serial port (MSSP) module of 2 the microcontrollers of the PIC16F87X Microchip family in master mode for I C communications. An algorithm for processing the status of the transfer is presented. 2 Key words: microcontroller PIC16F87X, master synchronous serial port MSSP, I C communications, special function registers.

INTRODUCTION One of the features of the microcontrollers of the PIC16F87X Microchip family is the synchronous serial port (MSSP) module which can be used for I2C communications. This module distinguishes itself from the synchronous serial port (SSP) and the basic synchronous serial port (BSSP), provided in some Microchip microcontrollers, by the availability of an additional control register SSPCON2 designed for hardware implementation of master mode for I2C communication. MSSP can operate as a transmitter and a receiver, in master and slave mode and support seven-bit and ten-bit addressing. It can be used in multi-master mode as well. According to the I2C protocol the transfer is driven by the master device. It specifies the transfer direction, the start (S) and repeated start (Sr) conditions, the slave address, the stop (P) condition and also generates the serial clock pulses for the bus [4]. After each 8-bit transfer (with the most significant bit first) the master microcontroller produces a ninth clock pulse for the acknowledgement bit ( ACK ), sent by the receiver. In the paper an attempt is made to distinguish the activities assigned to the software from those implemented by the hardware. CONFIGURING THE SYNCHRONOUS SERIAL PORT FOR I2C COMMUNICATIONS IN MASTER MODE 2 The configuration of the MSSP module of the PIC 16F87X in I C master mode is executed through five software accessible special function registers [3]: SSP Control Register (SSPCON). It allows control of the I2C mode. SSP Control Register 2 (SSPCON2). Its bits serve for enabling the reception and generating the start, repeated start, stop and acknowledgment conditions. SSPCON2 bits from 0 to six are used only in master mode. SSP Status Register (SSPSTAT). The flags in this register give information about detection of a start or stop bit, for specifying the type of the last byte received - data, address ( D / A ) or the completion of 10-bit address (UA) and about the direction of the data transfer read or write ( R / W ). Serial Receive/Transmit Buffer (SSPBUF). This is the register to which the transfer data is written to or read from. SSP Address Register (SSPADD). In master mode the baud rate is set through this register. The baud rate generator reload value, which has to be written to the SSPADD register, can be calculated using the formula in equation 1: FOSC f (SSPADD) = MSSP 1 , where (1) 4 FOSC is the frequency of the clock generator, fMSSP is the baud rate needed for the transfer. Apart from loading the above mentioned special function registers, in order to initialize the PORTC and to serve the interruptions, certain bits in the following registers have to be programmed: TRISC. This is the data direction register of the parallel bi-directional PORTC. The

International Conference on Computer Systems and Technologies - CompSysTech2003

multiplexed peripheral functions of the pins 3 and 4 of this port are the I2C bus lines SCL and SDA. PIR1 and PIE1. They contain the MSSP interrupt flag bit, SSPIF, and the SSPIE bit for enabling the SSPIF interruption request respectively. PIR2 and PIE2. In these registers are located the MSSP interrupt flag bit, BCLIF, detecting bus collisions when MSSP is configured in master mode and the BCLIE bit for enabling the BCLIF interruption request respectively. INTCON. Its bits 7 and 6 are the peripheral interrupt enable bit, PEIE, and the global interrupt enable bit, GIE respectively. AN ALGORITHM OF THE ? SSP FUNCTION IN MASTER MODE In master mode of PIC 16F87X MSSP the lines SCL and SDA are driven by its hardware which allows the programs describing the algorithms of the start, repeated start, transmitting, receiving and stop conditions to be reduced to several instructions. Completion of the bus conditions is signaled by means of the corresponding flag bits. For example, the algorithm for the start condition initialization (shown in Fig. 1) [3], requires only one instruction (for execution of the activity in the grey colored block) after the MSSP module is initialized.
SSPEN = 1, SSPCON<3:0> = 1000 Idle mode

SEN (SSPCON2<0> = 1) Bus collision detected, set BCLIF, release SCL, clear SEN

No

SDA = 1, SCL = 1? Yes

Load BRG with SSP ADD<6:0>

No Yes SCL= 0 No SDA = 0 Yes Reset BRG Force SDA = 0, load BRG with SSPADD<6:0>, set S bit No BRG rollover Yes

No SCL = 0 Yes Reset BRG

No

BRG rollover Yes

Force SCL = 0, Start condition done, clear SEN and set SSPIF

Fig. 1. Start condition flowchart Fig. 2. presents the flowchart of the algorithm for ? SSP initialization as a part of the main program executed by the microcontroller. Before enabling the MSSP module function, the SCL and SDA pins of PORTC must be programmed to inputs by setting the appropriate TRISC bits. After this the module has to be configured and enabled in master I2C mode. The transferred data will be written to/read from the preliminary specified begin

International Conference on Computer Systems and Technologies - CompSysTech2003

address. It can be either an address of a cell in the microcontroller internal memory or an output register address of a port for interface with the external data bus if an external memory is used. It is assumed that during the operation the master can change the direction of the transfer, that is it can operate as a receiver or as a transmitter.
Start No SSPIF = 1

Yes
Interruptions disabling S1? No S2? Yes No No Yes No No S3? Yes S4? No S5? Yes No

Yes
ACK ?
Yes SSPBUF loading from the begin address in the memory

ACK ?
Yes

ACK ?
No

SSPBUF sending in the memory

Initialization of PORTC Initialization of MSSP Specifying of an initial address in the memory for read/write of the data received/tranmitted Start condition Sending the slave address

SSPBUF loading from the current address in the memory

Yes

End address? No

Yes

End address? No Next address

Next address

ACKsending

Stop condition

Clearing SSPIF to 0

Restart condition
Interruptions enabling

Change of the transfer direction/slave address

End

Fig. 2. Flowchart of the MSSP initialization

Fig. 3. Flowchart of an example algorithm of an interruption service subroutine

The conditions of the transfer under I2C protocol are strictly consecutive and after the completion of each condition specified activities have to be executed by the software. The MSSP module configured in I2C master mode does not allow queuing of events. The completion of each condition on the bus control is indicated by the SSPIF flag bit. The flag setting can be identified by two approaches: using a loop cycle for sampling the flag state (polling) or enabling the SSPIF interrupt request [1, 2]. The particular condition of the bus can be found out by checking the corresponding bits in the SSPSTAT register. Fig. 3. presents the flowchart of an example of a possible algorithm of the SSPIF interruption service subroutine functioning. The algorithm does not show the activities on the data transfer executed by the ? SSP hardware. The example is for 7-bit address mode. In I2C master mode transmission an ACK is automatically generated by the slave hardware when it has recognized its address or has received the data properly. In I2C master mode reception after every write to the buffer the slave has to release the line SCL, so the receiver can send an acknowledgement or stop the transfer. A software overflow check should be performed (SSPOV flag bit = 1) and the slave should be informed. The particular application program will specify the following operations. The flag bit SSPOV has to be cleared by the software.The flag bit BF (buffer full) is cleared when SSPBUF is read. In table 1 the values of the status register flag bits which give the information needed for determination of the MSSP status are shown.

International Conference on Computer Systems and Technologies - CompSysTech2003

SDA list p=16f877 include org goto org bcf bsf movlw movwf bcf movlw movwf movlw bcf movwf movlw bsf movwf movlw movwf bcf btfss goto bcf movlw movwf e2 btfss goto bcf bsf bsf e3 bcf btfss goto bcf goto end <p16f877.inc> 0x00 start 0x10 STATUS,RP1 STATUS,RP0 0xff TRISC INTCON,GIE 0x09 SSPADD 0x38 STATUS,RP0 SSPCON 0x00 STATUS,RP0 SSPSTAT 0x01 SSPCON2 STATUS,RP0 PIR1,SSPIF e1 PIR1,SSPIF 0xCA SSPBUF PIR1,SSPIF e2 PIR1,SSPIF STATUS,RP0 SSPCON2,PEN STATUS,RP0 PIR1,SSPIF e3 PIR1,SSPIF start

SCL

start

; PORTC - inputs ; interruption disabling ; baud rate specification ; I2C master/transmitter mode configuration GIE b7 PEIE b6 b5

SDA

SCL

TRISC INTCON

b4

b3

b2

b1

b0

SSPADD

WCOL SSPOV SMP ; START condition ; MSSP interrupt request? ; START condition fulfilled ; transmit value loading ; I2C write initialization ; MSSP interrupt request? ; word transmitted CKE

SSPEN CKP

SSPM3 SSPM2 SSPM1 SSPM0 SSPCON S R/W UA RSEN BF SEN SSPSTAT SSPCON2

D/A

e1

GCEN ACKSTAT ACKDT ACKEN RCEN PEN

b7

b6

b5

b4

b3 SSPIF SSPIE

b2

b1

b0

SSPBUF PIR1 PIE1

; STOP condition ; MSSP interrupt request? ; STOP condition fulfilled

International Conference on Computer Systems and Technologies - CompSysTech2003

SSPSTAT flag bits State S1 The last state is start. The master is transmitter. The last byte sent is an address. S2 The last state is start. The master is transmitter. The last byte sent is data. S3 The last state is start. The master is receiver. The last byte sent is an address. S4 The last state is start. The master is receiver. The last byte sent is data. S5 The last state is start. The master is receiver. It has not sent an acknowledgement after the last byte sent, because of that the bits R / W and BF of the slave are cleared to 0.

Table1. MSSP flag bits states S BF D/ A R/ W (bit 3) (bit 2) (bit 5) (bit 0) 1 1 1 1 0 0 1 1 0 1 0 1 1 1 0 0

The example in Fig. 3 presents a program for looped transmitting of a byte ( ? ?h) in master transmitter mode which gives a possibility for observing the bus using an oscilloscope. The program is suitable for demonstrating the bus conditions as start, byte transmission, not ACK , and stop. CONCLUSIONS The synchronous serial port module MSSP of the microcontrollers of the PIC16F87X Microchip family enables the hardware communications according to I2C protocol in master mode. This leads to reducing the role of the application software. An interrupt request is generated at the completion of every bus condition which can be used to initiate the next condition. This makes the task of the programmer easier. REFERENCES [1] Bowling S., Using the PICmicro SSP for Slave I2CTM Communication, Microchip Technology Inc., DS 000734A, 2000. 2 [2] Fischer R., Using the PICmicro MSSP module for Master I C Communications, Microchip Technology Inc., DS 000735A, 2000. [3] PICmicro Mid-Range MCU Family Reference Manual, Microchip Technology Inc., 1997. [4] The I2C bus and how to use it, Philips semiconductor, 1992. ABOUT THE AUTHORS Nina Bencheva , Department of Communications, University of Rousse, Phone : +359 82 888 677, E-mail: nbencheva@ecs.ru.acad.bg Volodya Tsonev, Department of Communications, University of Rousse, Phone: +359 82 888 471, E-mail: vol@ru.acad.bg Assoc. Prof. Yoana Ruseva, PhD, Department of Communications, University of Rousse, Phone: +359 82 888 677, E-mail: iruseva@ecs.ru.acad.bg

Contents