Professional Documents
Culture Documents
a+(-a) = 0 Distributed Law x*(y.z) = (x*y) . (x*z) x.(y+z) = (x.y) + (x.z) x+(y.z) = (x+y) . (x+z)
x.(y+z) = (x.y)+(x.z)
x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 Y+z 0 1 1 1 0 1 1 1 x.(y+z) 0 0 0 0 0 1 1 1 x.y 0 0 0 0 0 0 1 1 x.z 0 0 0 0 0 1 0 1 (x.y)+x.z 0 0 0 0 0 1 1 1
Theorems
1a. x+x = x x+x = (x+x).1 = (x+x)(x+x) = x+xx =x+0 =x x.x = x (Remember Duality of 1a) x.x = xx+0 = xx+xx = x(x+x) = x.1 =x
1b.
Theorems
2a. x+1 = 1 x+1 =1.(x+1) = (x+x)(x+1) = (x+x) = x+x =1 X.0 = 0 (Remember Duality of of
2b. 2a)
3.
6a
6b.
(x) = x Complement of x = x Complement of x = (x) = x x+xy = x x+xy = x.1+xy = x(1+y) = x.1 =x x(x+y) = x (Remember Duality of 6a)
x 0 0 1 1
y 0 1 0 1 x=x+xy
xy 0 0 0 1
x+xy 0 0 1 1
x 0 0 1 1
y 0 1 0 1
x+y 0 1 1 1
(x+y) 1 0 0 0
x 1 1 0 0
y 1 0 1 0
xy 1 0 0 0
x xy xy xy
xy
VENN DIAGRAM FOR TWO VARIABLES VENN DIAGRAM ILLUSTRATION X=XY+X
z x+(y+z) xy+xz
z x y F1 y z x F2
(a) F1 = xyz
x
(b) F2 = x+yz
F3
(c) F3 = xyz+xyz+xy
x y
F4
(c) F4 = xy+xz
1.
x+xy = (x+x)(x+y) = 1.(x+y)=x+y 3. x(x+y) = xx+xy = 0+xy=xy 5. xyz+xyz+xy = xz(y+y)+xy = xz+xy 8. xy+xz+yz (Consensus Theorem) =xy+xz+yz(x+x) =xy+xz+xyz+xyz =xy(1+z)+xz(1+y) =xy+xz 13. (x+y)(x+z)(y+z)=(x+y)(x+z) by duality from function 4
Complement of a Function
(A+B+C) = (A+X) = AX = A.(B+C) = A.(BC) = ABC (A+B+C+D+..Z) = ABCD..Z (ABCD.Z) = A+B+C+D+.+Z Example using De Morgans Theorem (Method-1) F1 = xyz+xyz F1 = (xyz+xyz) = (x+y+z)(x+y+z) F2 = x(yz+yz) F2= [x(yz+yz)] = x+(y+z)(y+z)
F1 = xyz + xyz
Dual of F1 = (x+y+z)(x+y+z) Complement F1 = (x+y+z)(x+y+z) F2 = x(yz+yz) Dual of F2=x+(y+z)(y+z] Complement =F2= x+ (y+z)(y+z)
Minterm or a Standard Product n variables forming an AND term provide 2n possible combinations, called minterms or standard products (denoted as m1, m2 etc.). Variable primed if a bit is o Variable unprimed if a bit is 1 Maxterm or a Standard Sum n variables forming an OR term provide 2n possible combinations, called maxterms or standard sums (denoted as M1,M2 etc.). Variable primed if a bit is 1 Variable unprimed if a bit is 0
MINTERMS AND MAXTERMS FOR THREE BINARY VARIABLES MINTERMS x 0 0 0 0 1 1 1 1 y 0 0 1 1 0 0 1 1 z 0 1 0 1 0 1 0 1 Term xyz xyz xyz xyz xyz xyz xyz xyz Designation m0 m1 m2 m3 m4 m5 m6 m7 MAXTERMS Term x+y+z x+y+z x+y+z x+y+z x+y+z x+y+z x+y+z x+y+z Designation M0 M1 M2 M3 M4 M5 M6 M7
f1 = xyz+xyz+xyz f1 = xyz+xyz+xyz+xyz+xyz f1 =(x+y+z)(x+y+z)(x+y+z)(x+y+z) (x+y+z) = M0.M2.M3.M5.M6 = M0M2M3M5M6 f2 = xyz+xyz+xyz+xyz f2 = xyz+xyz+xyz+xyz f2 = (x+y+z)(x+y+z)(x+y+z)(x+y+z) = M0 M1 M2 M4 Canonical Form Boolean functions expressed as a sum of minterms or product of maxterms are said to be in canonical form. M3+m5+m6+m7 or M0 M1 M2 M4
ORing of term
AND terms of variables A,B &C They are minterms of the function
Standard Forms
Sum of Products (OR operations) F1 = y+xy+xyz (AND term/product term) Product of Sums (AND operations) F2=x(y+z)(x+y+z+w)
(OR term/sum term) Non-standard form F3=(AB+CD)(AB+CD) Standard form of F3 F3=ABCD + ABCD
Operator symbols
F0 = 0 F4 = xy F8 = (x+y) F12 = x
F1 = xy F5 = y F9 = xy +xy F13 = x + y
*Equivalence is also known as equality, coincidence, and exclusive NOR 16 logic operations are obtained from two variables x &y Standard gates used in digital design are: complement, transfer, AND, OR , NAND, NOR, XOR & XNOR (equivalence).
Range
Typical
Range
Typical
TTL Vcc=5 2.4-5 3.5 ECL VEE=-5.2 -0.95- -0.7 -0.8 CMOS VDD=3--10 VDD VDD Positive Logic: Logic-1 Negative Logic Logic-0
TTL basic circuit : NAND gate ECL basic circuit: NOR gate CMOS basic circuit: Inverter to construct NAND/NOR
OR X Y F
F=X+Y
GRAPHIC SYMBOL
ALGEBRIC FUNCTION X 0 1 X 0 1
TRUTH TABLE F 1 0 F 0 1
F=X
F=X
NAND
X Y
F=(XY)
X Y 0 0 0 1 1 0 1 1
F 1 1 1 0
NAME
GRAPHIC SYMBOL X Y
ALGEBRIC FUNCTION
TRUTH TABLE X Y 0 0 0 1 1 0 1 1 X Y 0 0 0 1 1 0 1 1 X Y 0 0 0 1 1 0 1 1 F 1 0 0 0 F 0 1 1 0 F 1 0 0 1
NOR
F=(X+Y)
Exclusive-OR (XOR)
X Y
F=XY+XY =XY
Exclusive-NOR or Equivalence
X Y
F=XY+XY =X Y
x Y Z
X Y Z
(X+Y+Z)
X Y Z
(XYZ)
TRUTH TABLE X Y X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Z 0 1 0 1 0 1 0 1 F 0 1 1 0 1 0 0 1 XOR F=X Y Z XNOR (b) Three input gates Odd function Even function 1 0 0 1 0 1 1 0
F=X Y Z
Very popular logic family. It has a extensive list of digital functions. It has a large number of MSI and SSI devices, also has LSI devices.
ECL Emitter Coupled Logic
Used in systems requiring high speed operations. It has a large number of MSI and SSI devices, also LSI devices. Used in circuit requiring high component density It has a large number of MSI and SSI devices, also LSI devices (mostly) Used in systems requiring low power consumption. It has a large number of MSI and SSI devices, also has LSI devices. Used in circuit requiring high component density. Mostly used for LSI functions
VCC
14 13 12 11 10 9 8
GND
GND
TTL gates
VCC 2 16 15
1 2 VCC 1 VCC 2 16
VEE 2 (-5.2V)
15
14
13
12
11
10
VCC 1
VEE (-5.2V)
VDD 14 13
(3-15 V) 12 11 10 9
NC 8
C MOS GATES
6 NC
7 Vss (GND)
NC 16 15 14
NC 13 12 11 10 9
LOGIC VALUE 1
SIGNAL VALUE H
LOGIC VALUE 0
SIGNAL VALUE
L Positive Logic
1 Negative Logic
X L L H H
y L H L H
x y
X 1 1 0 0
y 1 0 1 0
z 0 1 1 1
x y
Truth table for negative logic L=1 H=0 Same gate can function +ive logic NAND or -ive logic NOR +ive logic NOR or -ive logic NAND