ESE 570 Cadence Lab Assignment 1: Logic Simulation in Verilog-XL

Objective Part A:
To learn to create transistor level schematics using Composer, to create structural (gate and transistor level) and functional descriptions of elementary and complex logic functions in a hierarchical system, and to use Verilog-XL simulations to verify functional behavior.

Background Part A:
There are many hierarchies and levels of abstraction in VLSI design into which one could start his/her initial efforts in using the Cadence CAD toolset they range from high-level system design to transistor-level circuit layout. We choose to begin your journey in using Cadence with logic synthesis and simulation. Logic design is an important early step in VLSI circuit design. Verilog-XL is a high-level logic simulation tool available within Cadence that allows the designer to verify the behavior of the circuit in orders of magnitude less time than using circuit level simulators such as SPICE and SPECTRE. This is especially evident when the project being simulated is a complex logic design comprised of many interconnected gates. Furthermore VerilogXL gives the designer a higher level of abstraction to work with than circuit level simulators provide. If you completed the Cadence Tutorial you have created functional, transistor and gate level descriptions for the CMOS inverter using the Cadence schematic entry tool Composer. In this first Cadence lab we will focus on advancing your experience with developing structural and functional descriptions of logic functions suited for hierarchical design, We will also provide you with opportunities to experience the flexibility and power of Verilog-XL as a logic system simulator. Let's start with the functional view of your inverter module inv (out, in), or use the functional description in the Cadence Tutorial section Creating a Behavioral Model for an Inverter. In this functional description replace the line with not (strong1, strong0) #1 (out, in); The modier (strong1, strong0), informs Verilog-XL that the outputs of the inverter will have strengths strong for 1 and 0. The #1 informs Verilog-XL to delay the output by one time unit. The gate strength options, in order of decreasing strength, are as follows: supply, strong, pull, large, weak, medium, small For complementary CMOS gates the output strengths for logic 1 and 0 will always be strong. Strength specications will be useful when simulating circuits where race conditions need to be resolved. The Verilog-XL primitives for elementary logic gates AND, OR, NAND, NOR, XOR, XNOR are and, or, nand, nor, xor, xnor. An illustrative Verilog-XL example is provided at the ESE570 website. not (out, in);

Exercises Part A: (40/100 pts.)

Elementary Combinational Logic Create a transistor level schematic, symbol and Verilog behavioral (or functional) description for the complementary CMOS inverter, 2-input NOR gate and 2-input NAND gate. Do the Verilog-XL simulations for your inverter, NOR gate and NAND gate. Print your schematics, symbols, Verilog functional views and simulations. Provide a simple set of inputs (test vectors) that will verify correct functional behavior. If you completed the inverter while doing the Cadence Tutorial you may use those results for the inverter in this assignment. For your Verilog-XL simulations use timescale 1ns/10ps. For your transistor level schematics use w = 2.4u and l = 0.6 u for all n and p transistors, as used in the tutorial section of Schematic entry using Composer.

Objective Part B:
Using the inverter and gates created in Part A as cells, develop gate and transistor level schematics schematics using Composer and functional descriptions for two-phase static and dynamic flip-flop circuits.

Background Part B:
A dynamic D ip-op is shown in Fig. 1 where clk and clkP are two-phase nonoverlapping clocks and clkp and clkPp are their complements, respectively. Variable d is the input and q is the output. The two phases of the input clock clk and clkP can be generated from the circuit in Fig. 2. An important thing to notice is that the inverter in Fig. 2 serves as a delay element, so its Verilog model must also have a delay.

Figure 1 Dynamic D Flip-flop The Verilog primitive for the CMOS transmission gate is cmos and the input and output arguments are (output, input, clock, clockbar), where clock = clk and clockbar = clkP. The first inverters input will be will be the value of d when clk = 1. However, when clk = 0, there is no logic level at the input to the first inverter because the CMOS transmission gate is off and the d input is disconnected from the circuit. In a real transistor implementation there will be parasitic capacitance that maintains charge and keeps the logic level at the value it was just prior to the CMOS transmission gate turning off, albeit it will eventually leak (or decay) to zero if not refreshed or updated.

In Verilog high impedance or high-Z and physical capacitors are not defined which makes it difficult to model transmission gates and dynamic logic with out some help. Verilog provides the help by modeling this behavior using the declaration trireg (strengtha) #(x, y, z) nodename, where nodename in this case is the node for the input of the first inverter, x, y, z refer to rise delay, fall delay and charge decay time, respectively. This statement effectively attaches a capacitor-like storage element between the node and ground.

Figure 2 Two-phase Non-Overlapping Clock Generator If the dynamic D flip-flop in Fig. 1 does not receive any clock pulse for a long period of time, in fact just enough time for all the charge on the parasitic capacitance to decay to zero, the output will give an erroneous logical state. A static D flip-flop, such as that shown in Fig. 3, does not suffer from this issue.

qm

qs

Figure 3 Static D Flip-Flop The static D flip-flop in Fig. 3 is sometimes referred to as master-slave static D flip-flop where the first stage is the master stage with output qm and second is the slave stage with output qs .

Exercises for Part B: (60/100 pts.)

Dynamic and static D flip-flops a. Using your gates from Part A write a functional description and draw gate and transistor level schematics in Composer to implement the dynamic D flip-flop shown in Fig. 1. b. Do the same for the static D flip-flop shown in Figure 3. c. For the static D flip-flop add the necessary logic function to make it asynchronously resettable with a reset input R. Use the two-phase non-overlapping clock generator in Fig. 2 to provide the requisite clocks in a, b and c with clkin frequency = 25 MHz. Note that the inverter and gate functional and structural descriptions in Part A can serve as cells for your circuits in a, b and c above greatly simplifying the work to implement these circuits. Print your schematics, symbols, Verilog functional views and Verilog-XL simulations. Monitor the inputs, the two-clock phases and the outputs q and qp. Provide a simple set of inputs (test vectors) that will verify correct functional behavior. For your Verilog-XL simulations use timescale 1ns/10ps. In addition, for the dynamic D flip-flop remove the trireg from the functional description and re-simulate. Compare with the simulation that included the trireg.

Cadence Questions: (20/100 pts. extra credit)

a. Your project partner has a Cadence library called lab1 in ~yourpartner/cadence. You need to access his/her library from your Cadence library browser. What should you do? What must your partner do? What commands must you and your partner use to execute this need? b. What is a technology file and how does it relate to a library? c. How do you modify the properties of a transistor? d. How do you label a wire in Cadence? e. Lets assume that Cadence has crashed while you were working on a design (a real possibility!). Now when you try to edit your design, Cadence will not let you - providing the error message that the design is locked. How do you resolve this dilemma? Please note that this cadence Lab Assignment 1 (as well as Cadence Lab Assignment 2) will count 1.5 x the score for each of the seven Text Book Homework Assignments. KRL Updated 19 Mar12