KEYBOARD/DISPLAY CONTROLLER - INTEL 8279

The INTEL 8279 is specially developed for interfacing keyboard and display devices to 8085/8086/8088 microprocessor based system. The important features of 8279 are,

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Simultaneous keyboard and display operations. 8-character keyboard FIFO. 1 6-character display. 1 6-byte display RAM. Programmable scan timing.

Block diagram of 8279:

The functional block diagram of 8279 is shown.

The four major sections of 8279 are keyboard, scan, display and CPU interface.

1. Keyboard section:

The keyboard section consists of eight return lines RL0 - RL7 that can be connected to eight columns of a keyboard matrix. It has two additional input : shift and control/strobe. The keys are automatically debounced. The two operating modes of keyboard section are 2-key lockout and N-key rollover. In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized. In the N-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO. The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM. The FIFO RAM consists of eight registers that can store eight keyboard entries. The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal when there is an entry in FIFO. The format of key code entry in FIFO for scan keyboard mode is,

2. Display section:

The display section has eight output lines divided into two groups A0-A3 and B0-B3. The output lines can be used either as a single group of eight lines or as two groups of four lines, in conjunction with the scan lines for a multiplexed display. The display can be blanked by BD (Blank Display Output) line. The display section consists of 16 x 8 display RAM. The CPU can read from or write into any location of the display RAM.

3. Scan section:

The scan section has a scan counter and four scan lines, SL0 to SL3. These four scan lines can be decoded using a 4 to 16 decoder to generate 16 lines for scanning. The scan lines are common for keyboard and display. The scan lines are connected to the rows of a matrix keyboard and also connected to digit drivers of a multiplexed display, to turn ON/OFF.

4. CPU interface section:

The CPU interface section takes care of data transfer between 8279 and the processor. This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and CPU. It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control register of 8279. The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279. The IRQ (Interrupt request) line goes high whenever data entries are stored in FIFO. This signal is used to interrupt CPU to indicate the availability of data.

PERIPHERAL INTERFACING - PPI INTERFACING (8255)

The 8255 is a widely used, programmable, parallel I/O device. It can be programmed to transfer data under various conditions, from simple I/O to interrupt I/O. It is flexible, versatile and economical and complex. The 8255 has 24 I/O pins that can be grouped primarily into two 8 bit parallel ports: A and B, with the remaining 8 bits a port C. The 8 bits of port C can be used as individual bits or be grouped in two 4-bit ports: CUPPER (CU) and CLOWER (CL), as shown in the figure 1.1. The functions of these ports are defined by writing a control word in the control register.

Figure 1.2 shows all the functions of 8255; classified according to two modes: the Bit Set/Reset (BSR) mode and I/O mode. The BSR mode is used to set or reset the bits in port C. The I/O mode is further divided into three modes: Mode 0, Mode 1 and Mode 2. In Mode 0, all ports function as simple I/O ports. Mode 1 is a hand shake mode whereby Ports A and/or B use bits from port C as handshake signals. In Mode 2 Port A can be set up for bidirectional data transfer using handshaking signals from Port C, and Port B can be set up either in Mode 0 or Mode 1.

Block Diagram of the 8255

CONTROL LOGIC

(Read): This control signal enables the Read operation. When the signal is low, the MPU reads data from a selected I/O Port of the 8255.

(Write): This control signal enables the write operation. When the signal goes low, MPU writes into a selected I/O Port or control register. RESET (Reset): This is an active high signal; it clears the control register and sets all ports in the input mode.

, A0 and A1: Theses are device select signals. Chip Select is connected to a decoded address, and A0 and A1 are generally connected to MPU address lines A0 and A1 respectively

CONTROL WORD Figure 1.5 shows a register called the control register. The contents of this register called control word. This register can be accessed to write a control word when A0 and A1 are at logic 1. This control register is not accessible for a read operation. Bit D7 of the control register specifies either I/O function or the Bit Set/Reset function. If bit D7=1, bits D6-D0 determines I/O functions in various modes. If bit D7=0, Port C operates in the Bit Set/Reset (BSR) mode. The BSR control word does not affect the functions of Port A and Port B.

To communicate with peripherals through the 8255, three steps are necessary:

1. Determine the address of ports A, B and C and of the control register according to the chip select logic and address lines A0 andA1. 2. Write the control word in the control register. (Using RD & WR for read and write) 3. Write I/O instructions to communicate with peripherals through Ports A, B and C.

Operating Modes Mode 0: Simple Input or Output In this mode, ports A, B are used as two simple 8-bit I/O ports and port C as two 4-bit ports. Each port can be programmed to function as simply an input port or an output port. The input/output features in Mode 0 are as follows.

1. Outputs are latched. 2. Inputs are not latched. 3. Ports dont have handshake or interrupt capability. Mode 1: Input or Output with Handshake In this mode, handshake signals are exchanged between the MPU and peripherals prior to data transfer. The features of the mode include the following:

1. Two ports (A and B) function as 8-bit I/O ports. They can be configured as either as input or output ports. 2. Each port uses three lines from port C as handshake signals. The remaining two lines of Port C can be used for simple I/O operations. 3. Input and Output data are latched. 4. Interrupt logic is supported. Mode 2: Bidirectional Data Transfer This mode is used primarily in applications such as data transfer between two computers. In this mode, Port A can be configured as the bidirectional port and Port B either in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals for data transfer. The remaining three signals from port C can be used either as simple I/O or as handshake for port B. BSR (Bit Set/Reset) Mode The BSR mode is concerned only with the eight bits of port C, which can be set or reset by writing an appropriate control word in the control register. A control word with bit D7 =0 is recognized as a BSR control word, and it does not alter any previously transmitted control word with bit D7=1; thus the I/O operations of ports A and B are not affected by a BSR control word. In BSR mode, individual bits of port C can be used for applications such as an on/off switch. Ports A and B are not affected by the BSR Mode.

BSR CONTROL WORD

this control word, when written in the control register, sets or resets one bit at a time,

8259A Block Diagram

INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR): The IRR has eight input lines (IR0-IR7) for interrupts. When these lines go high, the requests are stored in the register. The ISR (In service register) stores the interrupts which are currently in service. PRIORITY RESOLVER This block gives the priority to all interrupts which are stored into IRR. INTERRUPT MASK REGISTER (IMR) The IMR stores the bits which mask the interrupt lines to be masked. DATA BUS BUFFER This 3-state, bidirectional 8-bit buffer is used to interface the 8259A to the system Data Bus. Control words and status information are transferred through the Data Bus Buffer. READ/WRITE CONTROL LOGIC The function of this block is to accept Output commands (RD,WR) from the CPU. This function block also allows the status of the 8259A to be transferred onto the Data Bus. A0 and Chip select determine the port address of the controller. THE CASCADE BUFFER/COMPARATOR This function block stores and compares the IDs of all 8259A's used in the system. The associated three I/O pins (CAS0-2) are outputs when the 8259A is used as a master and are inputs when the 8259A is used as a slave.

8254(8253) Programmable Interval Timer Block Diagram

This interval timer is a software counter, it generates accurate time delays and can be used for realtime clock, an event counter, a square wave generator. It contains 24 pins and require +5 V power supply.