HIGH SPEED SERIAL-SERIAL MULTIPLIER USING ASYNCHRONOUS 1S COUNTER

GUIDE PROJECT MEMBERS

: MR. S.BIBIN SAM PAUL ,AP/ECE

: R.RENGA PRASAD-40408106085 N.VIKRAM -40408106129 M.WASIM FASIL -40408106130

ABSTRACT
Multipliers are the fundamental and essential building blocks of VLSI systems. The design and implementation approaches of multipliers contribute substantially to the area, speed and power consumption of computational intensive VLSI systems . Often, the delay of multipliers dominates the critical path of these systems and due to issues concerning reliability and portability, power consumption is a critical criterion for applications that demand lowpower as its primary metric. The objective of the project is to design a high speed Serial-Serial Multiplier using asynchronous 1s counter for high data rate applications. The multiplier requires only n sampling cycles instead of at least 2n cycles for an n n multiplication in the conventional serial-serial multipliers. The multiplier consists of a serial-serial data accumulation unit and a parallel carry save adder (CSA) array and asynchronous 1s counter to compress the partial products (PP). It replaces conventional full adders and counters with asynchronous 1s counters so that the critical path is limited to only an AND gate and a D flipflop (DFF).This approach reduces the height of the partial product matrix and dissipates only less power compared to conventional multiplier, and has only less additional delay penalty to complete a multiplication compared to the conventional fully parallel CSA array multiplier. This serial-serial multiplier finds application in system-onchip design and hardware cryptography.

PROJECT MODULES
1.Generation of Partial Product as tree structure. 2.Generation of counter based accumulator result. 3.Reduction of partial products and design of fast vector merged adder to add the final outputs of registers. 4.Analysis of Speed and power consumption using CADENCE tool

INTEGRATION OF MODULE 1 AND MODULE 2

Generation of Partial Product as tree structure

The Diagram shows the generation sequence of the PPs with row r generated in cycler , for r=0,1,2,n-1 .PPrC is represented by the center column,PPrR by the columns to the right of the center column and PPrL by the columns to the left.

Architecture of partial product generation and counter based accumulator result

A PP bit corresponding to the middle column of the PP is produced by the center AND gate when a new pair of input bits (Xn-i-1 and Yi) is latched by the two DFFs (top middle) in each clock cycle. In the next cycle, Xn-i-1 and Yi are shifted to the left and right, respectively, to produce the partial product bits with another pair of input bits yi+1and xn-i-2 by the array of AND gates. Each counter changes state at the rising edge of the clock line only if a 1 is produced by its driving AND gate. After cycles, the counters hold the sums of all the 1s in the respective columns and their outputs are latched to the second stage for summation.

Verilog implementation
1. Created D-flipflop module in behaviour modelling. 2. Created left shift register module by instantiating eight D-flipflops in structural modelling. 3. Created right shift register module by instantiating eight D-flipflops in structural modelling. 4. Created partial products module with 15 AND gates and instantiating left and right shift registers. 5. Derived the output of partial products. 6. Created a 4-bit counter by instantiating four D Flip Flops 7. Created eight 3-bit counter by instantiating three D Flip Flops 8. Created four 2-bit counter by instantiating two D Flip Flops 9. Created two 1-bit counter by instantiating one D Flip Flops The output of AND gates is given as input to respective asynchronous 1s counter.Hence the output of the counters gives the no of 1s in the respective columns.

REDUCTION OF PARTIAL PRODUCTS BITS AND FINAL SUMMATION

1. In this module,the final outputs of the counters need to be further reduced to only two rows of partial products by a CSA tree and a carry propagate adder is then used to obtain the final sum. 2. In stage 1,all counter output bits of the same positional weight are arranged in the same column with the least significant bit (LSB) of each counter output aligned at their respective columns and corresponding bitsarranged in diagonal manner.As shown above,four half adders are used in stage 1;their sum and carry are displayed in the stage2. 3. In stage2,the remaining bits in stage 1 are retained . One half adder and nine full adders are used in this stage and their sum and carry are carried to next stage. 4. In stage 3,a ripple carry adder is used to obtain the final sum(i.e) product of the inputs . 5. Thus drastic reduction in column height leads to a much simpler CSA tree,and hence reducing the overall hardware complexity and power consumption.

Verilog implementation
1. Created five half adders and nine full adders. 2. Assigned the respective counter bits in the adders as per the alignment. 3. The generated sum and carry of the adders were given to ripple carry adder to obtain the final sum (i.e)product.

Further Work: Analysis of speed and power consumption have to be done using CADENCE tool.