EXPERIMENT No. - 1 Object: - To design and simulate N-MOS inverter.

Theory: - The Input logic signal is applied to the gate (Vi=Vgs) and output is taken at the drain (Vo = Vds) for input Vi below the (positive) threshold voltage Vt of the NMOS the device is off and Vo = Vdd. At the logic high level of input that is for Vi = Vdd (>Vt) the transistor is ON and the output is nearly at ground level. When the gate to source voltage of an N-MOSFET is large so that Vds < Vgs - Vt is satisfied the MOSFET operates in its linear region much like a passive resister. Hence on E-MOSFET biased in the linear region can be used as load in an inverter. Shows an NMOS inverter with a linear enhancement type NMOS as load. Design consideration of implementation of an inverter circuit. Hence we short circuit the gate of EMOS to its source so that V gs > Vt and the pull up device be always in its ON state the operating mode of MOS device is when the input is at logic low, the output will be at logic high and vice versa the inverter complemented the output in accordance. MOS DEVICE (OFF) MOS DEVICE OHMIC MODE ON SATURATION MODE

5 v M B S 1 S 1 2 9

O O D S O

F F N T E L T A P P

T I A R V

I M

E D = S . T5 M S1 u E = C L. K5 u S Y = T V A L = 0 A L = 1

L 2 0 8 2

EXPERIMENT No. 2 Object: - Design and simulation of CMOS inverter. Theory: - The substrate of each MOS is connected to the source to avoid body effect presence. The input voltage Vi controls the gate bias for both Mn and Mp so neither one driving the other; instead each device operates in a mode complementary to each other. For Vi = Vgsn = 0, Mn is turned off, while Mp is with Vgsp = VDD is turned on so Vo is at logic high level (VDD). For Vi < Vdn, Mn is turned off and Mp is on, with 0 mA source to drain current, hence. Vo = VOH = VDD. As Vi is increased above Vpn, Mn goes to saturation and Vo is now dropping slightly due to conduction of Mn. The saturation condition for Mp is Vsdp Vgsp - |Vsp| - - - (1) Further increase in Vi causes Vd to drop further and eqn.1 is satisfied and Mp is in saturation. At this point Mn and Mp are in saturation and operate as constant current source.
V 1

M M

3 2 N 6 8 0 4

O O D S O

F F N T E L T A P P

T I A R V

D S T M 1 I M E = 2 u s E C L =K 2 u s Y = T V A L = 0 A L = 1

M M

4 2 N 6 6 5 9

EXPERIMENT No. 3 Object: - Design and simulate two input NOR gate. Theory: - NMOS is channel metal oxide semiconductor device. In the N-MOS NOR gate circuit. Three transistor are used one transistor circuit acts as pull up device having its gate and source connected to +VDD. The other two transistor are connected in parallel to each other are pull down device which are connected to the pull-up device in series. When either of the input is high, the corresponding MOS conducts and output is LOW if both MOSFETs are OFF, the output is HIGH.
V 1 0 M B S S 1 1 2 9 1

O O D S O

F F N T E L T A P P

T I M E = D . S5 I M E = .C 5 L K u A Y = R T V A L = V A L = 1

u M T S S 0

L 2 0 8 2 V

O O D S O

F F N T E L T A P P

T I M E = D 1 S u Ts M I M E = 1 L Ks C u A Y = R T V A L = 0 V A L = 1

L 2 0 8 2 V

EXPERIMENT No. 4 Object: - Design and simulate two input NAND gate. Theory: - The circuit of NMOS NAND gate uses three transistor in series. The first transistor is pull-up device known as load and its gate and source are connected to the +VDD. The other two transistors form Pull-Down devices and are known as drivers. Input A and B must be high for all transistors to conduct and force output to go low. If either of input is low, the transistor is OFF and the output is HIGH.

M B S

1 V S 1 2 9 1 0 v 1

O O D S O

F F N T E L T A P P

T I A R V

E D = S T. 5 M u 1 S M E = L K. 5 u S C Y = T V A L = 0 A L = 1

I M

M M

4 6 7 5 9

2 VN

O O D S O

F F N T E L T A P P

T I A R V

E D = S T1 M s 2 u E = L K1 u s C Y = T V A L = 0 A L = 1

I M

5 6 7 5 9

M V2 N

EXPERIMENT No. -9

EXPERIMENT No. 5 Object: - Design and simulate full-adder circuit. Theory: - A full adder is a combinational circuit that performs the arithmetic sum of three input bits and produces an output as sum and a carry. Two of the input variables represent the two significant bits to be added. Third input represents the carry from the previous lower significant position. The two outputs are designated by the symbol S for sum and C for carry. Sum S = x y z And carry C = xy + yz + zx
O O D S O F F N T E L T A P P T I A R V M I M D E S =T M1 m 1 E C L =K 1 m s Y = T V A L = 0 A L = 1 s 1 2 V 7 4 8 6 U 1 A U 3 1 2 7 4 3 8 6
V

2 A

O O D S O O O D S O

F F N T E L T A P P F F N T E L T A P P

T I A R V T I A R V

I M D E S =T M2 m 2 E C L =K 2 m s Y = T V A L = 0 A L = 1 I M D E S =T M3 m 3 E C L =K 3 m s Y = T V A L = 0 A L = 1

s U 1 2 3 7
V

3 A U 1 2 7 4 0 8 U 1 2 7 3 4 3 2
V

4 A 3 5 A

4 0 8

Experiment:6(a)
Program:- Synthesis and simulation of Half Adder.
library IEEE; use IEEE.STD_LOGIC_1164.all; entity add is port( a : in STD_LOGIC; b : in STD_LOGIC; s : out STD_LOGIC; cry : out STD_LOGIC ); end add; architecture beh of add is begin s<= a xor b ; cry<= a and b ; end beh;

OUTPUT:-

Experiment:6(b)
Program:- Synthesis and simulation of Full Adder.
library IEEE; use IEEE.STD_LOGIC_1164.all; entity add is port( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; s : out STD_LOGIC; cry : out STD_LOGIC ); end add; architecture beh of add is begin s<= a xor b xor c; cry<= a and b and c; end beh;

OUTPUT:-

Experiment:-7
Program:- Synthesis and simulation of 3X8 Decoder.

library IEEE; use IEEE.STD_LOGIC_1164.all; entity decoder3_8 is port( I : in STD_LOGIC_VECTOR(2 downto 0); Y : out STD_LOGIC_VECTOR(7 downto 0) ); end decoder3_8; architecture beh of decoder3_8 is begin process(I) begin case I is when "000"=> Y<="10000000"; when "001"=> Y<="01000000"; when "010"=> Y<="00100000"; when "011"=> Y<="00010000"; when "100"=> Y<="00001000"; when "101"=> Y<="00000100"; when "110"=> Y<="00000010"; when others=> Y<="00000001"; end case; end process; end beh;

OUTPUT:-

Experiment:-8(a)
Program:- Synthesis and simulation of 4X1 Multiplexer.
library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux is port( I : in STD_LOGIC_VECTOR(3 downto 0); s : in STD_LOGIC_VECTOR(1 downto 0); y : out STD_LOGIC ); end mux; architecture beh of mux is begin process(s) begin case s is When "00"=>y<=i(0); When "01"=>y<=i(1); When "10"=>y<=i(2); When others=>y<=i(3); end case; end process; end beh;

OUTPUT:-

Experiment:-8(b)

Program:-Synthesis and simulation of 8X1 Multiplexer.

library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux is port( I : in STD_LOGIC_VECTOR(7 downto 0); S : in STD_LOGIC_VECTOR(2 downto 0); Y : out STD_LOGIC ); end mux; --}} End of automatically maintained section architecture beh of mux is begin -- enter your statements here -process(s) begin case s is when "000"=> Y<=I(7); when "001"=> Y<=I(6); when "010"=> Y<=I(5); when "011"=> Y<=I(4); when "100"=> Y<=I(3); when "101"=> Y<=I(2); when "110"=> Y<=I(1); when others => Y<=I(0); end case; end process; end beh;

OUTPUT:-

NAME: - GAURAV BISHT