Professional Documents
Culture Documents
Rev. 7, Mar-2000
ON Semiconductor
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special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by
customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
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DL129/D
03/00
DL129
REV 7
ON Semiconductor
DL129/D
Rev. 7, Mar2000
SCILLC, 2000
Previous Edition 1996
All Rights reserved
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be
validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
CENTRAL/SOUTH AMERICA:
Spanish Phone: 3033087143 (MonFri 8:00am to 5:00pm MST)
Email: ONlitspanish@hibbertco.com
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00180044223781
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JAPAN: ON Semiconductor, Japan Customer Focus Center
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Email: r14525@onsemi.com
ON Semiconductor Website: http://onsemi.com
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2
Table of Contents
Thermal Management . . . . . . . . . . . . . . . . . . . . . . .
Capacitive Loading Effects on
Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Effects on DC and AC
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage Effects on Drive Current
and Propagation Delay . . . . . . . . . . . . . . . . . . . . . . .
Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . .
Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Parametric Values . . . . . . . . . . . . . . . . . . . .
Reduction of Electromagnetic
Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hybrid Circuit Guidelines . . . . . . . . . . . . . . . . . . . . .
SchmittTrigger Devices . . . . . . . . . . . . . . . . . . . . .
Oscillator Design with HighSpeed CMOS . . . . . .
RC Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . .
Printed Circuit Board Layout . . . . . . . . . . . . . . . . . .
Definitions and Glossary of Terms . . . . . . . . . . .
HC vs. HCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Glossary of Terms . . . . . . . . . . . . . . . . . . . . . . . .
Applications Assistance Form . . . . . . . . . . . . . .
24
24
28
28
29
31
31
35
35
35
36
37
38
40
40
40
40
41
43
44
44
45
46
48
49
49
50
51
51
51
52
53
53
53
56
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3
398
398
405
406
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4
CHAPTER 1
Function Selector Guide
Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . 6
Buffers/Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Schmitt Triggers . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . 12
Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FlipFlops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Digital Data Selectors/Multiplexers . . . . . . . . . . 16
Decoders/Demultiplexers/Display Drivers . . . . 17
Analog Switches/Multiplexers/
Demultiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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5
ALPHANUMERIC INDEX
Function
Device Number
MC74HC00A
MC74HC02A
MC74HC03A
MC74HC04A
MC74HCT04A
MC74HCU04A
MC74HC08A
MC74HC14A
MC74HCT14A
MC74HC32A
MC74HC74A
MC74HCT74A
MC74HC86A
MC74HC125A
MC74HC126A
MC74HC132A
MC74HC138A
MC74HCT138A
MC74HC139A
MC74HC157A
MC74HC161A
MC74HC163A
MC74HC164A
MC74HC165A
MC74HC174A
MC74HC175A
MC74HC240A
MC74HC244A
MC74HCT244A
MC74HC245A
MC74HCT245A
MC74HC273A
MC74HCT273A
MC74HC373A
MC74HCT373A
MC74HC374A
MC74HCT374A
MC74HC390A
MC74HC393A
MC74HC540A
MC74HC541A
MC74HCT541A
MC74HC573A
MC74HCT573A
MC74HC574A
MC74HCT574A
MC74HC589A
MC74HC595A
MC74HC4020A
MC74HC4040A
MC74HC4046A
Page
Number
58
62
66
70
74
78
83
87
92
95
99
104
108
112
112
116
120
125
130
134
139
139
151
157
165
169
175
180
185
189
194
199
204
208
214
220
225
230
236
242
246
250
254
260
265
271
276
285
293
299
305
ALPHANUMERIC INDEX
Function
Device Number
MC74HC4051A
MC74HC4052A
MC74HC4053A
MC74HC4060A
MC74HC4066A
MC74HC4316A
MC74HC4538A
MC74HC4851A
MC74HC4852A
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Page
Number
319
319
319
332
341
350
360
371
371
BUFFERS/INVERTERS
Device
Number
MC74
Function
HC04A
HCT04A
HCU04A
HC14A
HCT14A
Hex Inverter
Hex Inverter with LSTTLCompatible Inputs
Hex Unbuffered Inverter
Hex SchmittTrigger Inverter
Hex SchmittTrigger Inverter with LSTTLCompatible
Inputs
HC125A
HC126A
HC240A
HC244A
HCT244A
HC245A
HCT245A
HC540A
HC541A
HCT541A
Functional
Equivalent
LSTTL
Device
74
Functional
Equivalent
CMOS
Device
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
Number
of
Pins
LS04
LS04
LS04
LS14
LS14
*4069
*4069
4069
4584
4584
LS/CMOS
LS/CMOS
LS/CMOS
LS/CMOS
LS/CMOS
14
14
14
14
14
LS125,LS125A
LS126,LS126A
LS240
LS
LS
LS
14
14
20
LS244
LS
20
LS244
LS
20
LS245
LS245
LS
LS
20
20
20
LS541
LS
20
LS541
LS
20
Device
# Pins
Quad Device
Hex Device
Octal Device
NineWide Device
Noninverting Outputs
Inverting Outputs
HC
HCT
04A
HCU
04A
HC
14A
HC
125A
HC
126A
HC
240A
HC
HCT
244A
HC
HCT
245A
14
14
14
14
14
20
20
20
D
D
D
D
D
D
Schmitt Trigger
3State Outputs
OpenDrain Outputs
Common Output Enables
ActiveLow Output Enables
ActiveHigh Output Enables
Separate 4Bit Sections
Separate 2Bit and 4Bit Sections
D
D
Transceiver
Direction Control
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BUFFERS/INVERTERS (Continued)
HC
540A
HC
HCT
541A
# Pins
20
20
Quad Device
Hex Device
Octal Device
NineWide Device
Noninverting Outputs
Inverting Outputs
Device
3State Outputs
OpenDrain Outputs
Common Output Enables
ActiveLow Output Enables
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9
D
D
D
D
GATES
Functional
Equivalent
LSTTL
Device
74
Device
Number
MC74
Function
HC00A
HC02A
HC03A
HC08A
HC32A
HC86A
HC132A
LS00
Functional
Equivalent
CMOS
Device
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
4011
4001
*4011
4081
4071
4070
4093
LS08
LS32
LS86
LS132
LS
Number
of
Pins
14
14
14
14
14
14
14
LS
LS
LS
LS
HC
00A
HC
02A
HC
03A
HC
08A
HC
32A
# Pins
14
14
14
14
14
Single Device
Dual Device
Triple Device
Quad Device
Device
NAND
NOR
AND
OR
Exclusive OR
Exclusive NOR
ANDNOR
ANDOR
2Input
3Input
4Input
8Input
13Input
SchmittTrigger Inputs
OpenDrain Outputs
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10
GATES (Continued)
HC
86A
HC
132A
# Pins
14
14
Single Device
Dual Device
Triple Device
Quad Device
Device
NAND
NOR
AND
OR
Exclusive OR
Exclusive NOR
ANDNOR
ANDOR
2Input
3Input
4Input
8Input
13Input
SchmittTrigger Inputs
OpenDrain Outputs
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11
SCHMITT TRIGGERS
BUS TRANSCEIVERS
Device
Number
MC74
HC14A
HCT14A
HC132A
Function
Functional
Equivalent
CMOS
Device
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
Number
of
Pins
LS14
LS14
4584
4584
LS/CMOS
LS
14
14
LS132
4093
LS
14
Function
Functional
Equivalent
LSTTL
Device
74
Functional
Equivalent
CMOS
Device
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
Number
of
Pins
LS
LS
20
20
Device
Number
MC74
HC245A
HCT245A
Functional
Equivalent
LSTTL
Device
74
LS245
LS245
HC
HCT
245A
Device
# Pins
20
Quad Device
Octal Device
D
D
Buffer
Storage Capability
Inverting Outputs
Noninverting Outputs
D
D
Direction Control
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12
LATCHES
Device
Number
MC74
Functional
Equivalent
LSTTL
Device
74
Function
Functional
Equivalent
CMOS
Device
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
Number
of
Pins
HC373A
HCT373A
LS373
LS373
LS373
LS373
20
20
HC573A
HCT573A
LS373
LS373
LS573
LS573
20
20
HC
HCT
373A
HC
HCT
573A
# Pins
20
20
Single Device
Dual Device
Octal Device
3State Outputs
Common Output Enable, ActiveLow
D
D
D
D
Device
Transparent
Addressable
Readback Capability
Noninverting Outputs
Inverting Outputs
These devices are identical in function and are different in pinout only: HC/HCT373A and HC/HCT573A
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13
FLIPFLOPS
Device
Number
MC74
Function
Functional
Equivalent
LSTTL
Device
74
Functional
Equivalent
CMOS
Device
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
Number
of
Pins
LS74,LS74A
LS74,LS74A
*4013
4013
LS
LS
14
14
4174
4175
LS/CMOS
LS/CMOS
16
16
HC74A
HCT74A
HC174A
HC175A
LS174
LS175
LS273
LS273
LS
LS
20
20
LS374
LS374
LS374
LS374
20
20
LS374
LS374
HC273A
HCT273A
HC374A
HCT374A
HC574A
HCT574A
20
20
*Suggested alternative
HC
HCT
74A
HC
174A
HC
175/A
# Pins
14
16
16
Type
Device
Dual Device
Quad Device
Hex Device
Octal Device
D
D
D
D
Common Reset
ActiveLow Reset
ActiveHigh Reset
D
D
D
D
ActiveLow Set
Common Clock
NegativeTransition Clocking
PositiveTransition Clocking
3State Outputs
Common, ActiveLow Output Enables
Transceiver
Direction Control
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14
FLIPFLOPS (Continued)
HC
HCT
273A
HC
HCT
374A
HC
HCT
574A
# Pins
20
20
20
Type
Dual Device
Quad Device
Hex Device
Octal Device
D
D
D
D
Device
Common Clock
NegativeTransition Clocking
PositiveTransition Clocking
3State Outputs
Common, ActiveLow Output Enables
D
D
Common Reset
ActiveLow Reset
ActiveHigh Reset
ActiveLow Set
Transceiver
Direction Control
These devices are identical in function and are different in pinout only: HC374A and HC574A
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15
Device
Number
MC74
HC157A
HC251
HC253
HC257
Functional
Equivalent
LSTTL
Device
74
Function
LS157
LS251
LS253
LS257B
Functional
Equivalent
CMOS
Device
MC1XXXX
or CDXXXX
*4512
Direct Pin
Compatibility
Number
of
Pins
LS
16
LS
LS
16
16
LS
16
*Suggested alternative
HC
157A
Device
# Pins
16
Description
One of
two 4bit
words is
selected
Single Device
Dual Device
Quad Device
D
D
Common Address
1Bit Binary Address
2Bit Binary Address
3Bit Binary Address
Noninverting Output
Inverting Output
3State Outputs
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16
DECODERS/DEMULTIPLEXERS/DISPLAY DRIVERS
Device
Number
MC74
HC138A
HCT138A
HC139A
Function
Functional
Equivalent
LSTTL
Device
74
Functional
Equivalent
CMOS
Device
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
Number
of
Pins
LS138
LS138
*4028
*4028
LS
LS
16
16
LS139
4556
LS/CMOS
16
1of8 Decoder/Demultiplexer
1of8 Decoder/Demultiplexer with LSTTLCompatible
Inputs
Dual 1of4 Decoder/Demultiplexer
*Suggested alternative
Device
# Pins
Input Description
Output Description
HC
HCT
138A
HC
139A
16
16
3Bit Binary
Address
2Bit Binary
Address
One of 8
One of 4
Single Device
Dual Device
ActiveLow Outputs
ActiveHigh Outputs
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17
DD
D
ANALOG SWITCHES/MULTIPLEXERS/DEMULTIPLEXERS
Device
Number
MC74
HC4051A
HC4052A
HC4053A
HC4066A
KHC4316/A
KHC4851A
KHC4852A
Functional
Equivalent
LSTTL
Device
74
Function
Functional
Equivalent
CMOS
Device
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
Number
of
Pins
4051
4052
4053
4066,4016
CMOS
CMOS
CMOS
CMOS
16
16
16
14
*4016
16
*4051
20
*4052
20
Effect Control
Effect Control
*Suggested alternative
K HighSpeed CMOS design only
# Pins
Description
Single Device
Dual Device
Triple Device
Quad Device
1to1 Multiplexing
2to1 Multiplexing
4to1 Multiplexing
8to1 Multiplexing
HC
4051A
HC
4052A
HC
4053A
16
16
16
14
A 3Bit Address
Selects One of 8
Switches
A 2Bit Address
Selects One of 4
Switches
A 3Bit Address
Selects Varying
Combinations of
the 6 Switches
4 Independently
Controlled
Switches
D
D
HC
4066A
D
D
D
D
D
D
D
D
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HC
4316A
# Pins
Description
HC
4851A
HC
4852A
16
20
20
4 Independently
Controlled Switches
(Has a Separate
Analog Lower
Power Supply)
A 3Bit Address
Selects One of 8
Switches
(Has Injection Current
Protection)
A 3Bit Address
Selects Varying
Combinations of
the 6 Switches
(Has Injection Current
Protection)
Single Device
Dual Device
Triple Device
Quad Device
D
D
1to1 Multiplexing
2to1 Multiplexing
4to1 Multiplexing
8to1 Multiplexing
D
D
D
D
D
D
D
D
D
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19
SHIFT REGISTERS
Device
Number
MC74
Function
Functional
Equivalent
LSTTL
Device
74
HC164A
HC165A
LS164
LS165
HC589A
HC595A
Functional
Equivalent
CMOS
Device
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
Number
of
Pins
*4021
LS
LS
14
16
16
16
*Suggested alternative
HC
164A
HC
165A
HC
589A
HC
595A
# Pins
14
16
16
16
4Bit Register
8Bit Register
D
D
D
D
D
D
D
D
D
D
D
D
Device
PositiveTransition Clocking
ActiveHigh Clock Enable
D
D
3State Outputs
ActiveLow Output Enable
ActiveLow Reset
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D
D
D
COUNTERS
Device
Number
MC74
HC161A
HC163A
HC390A
HC393A
HC4020A
HC4040A
HC4060A
Functional
Equivalent
CMOS
Device
MC1XXXX
or CDXXXX
Functional
Equivalent
LSTTL
Device
74
Direct Pin
Compatibility
Number
of
Pins
LS161,LS161A
LS
16
LS161,LS161A
LS
16
16
16
LS
CMOS
CMOS
CMOS
14
16
16
16
Function
LS393
*4520
4020
4040
4060
*Suggested alternative
# Pins
Single Device
Dual Device
HC
161A
HC
163A
HC
390A
HC
393A
HC
4020A
HC
4040A
HC
4060A
16
16
16
14
16
16
16
4
4
4
4
14
12
12
12
14
10
Ripple Counter
Number of Ripple Counter Internal Stages
Number of Stages with Available Outputs
Count Up
D
D
Separate 2 Section
Separate 5 Section
DD
DD
ActiveHigh Reset
Carry Output
PositiveTransition Clocking
NegativeTransition Clocking
ActiveHigh Clock Enable
ActiveLow Clock Enable
ActiveHigh Count Enable
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21
MISCELLANEOUS DEVICES
Device
Number
MC74
HC4046A
HC4538A
Functional
Equivalent
LSTTL
Device
74
Function
PhaseLocked Loop
Dual Precision Monostable Multivibrator
(Retriggerable, Resettable)
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22
Functional
Equivalent
CMOS
Device
MC1XXXX
or CDXXXX
Direct Pin
Compatibility
Number
of
Pins
4046
4538,4528
CMOS
CMOS
16
16
CHAPTER 2
Design Considerations
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Handling Precautions . . . . . . . . . . . . . . . . . . . . . . . .
Power Supply Sizing . . . . . . . . . . . . . . . . . . . . . . . . .
Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CMOS Latch Up . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Power Dissipation . . . . . . . . . . . . . . . . . .
Thermal Management . . . . . . . . . . . . . . . . . . . . . . .
Capacitive Loading Effects on
Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Effects on DC and AC
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply Voltage Effects on Drive Current
and Propagation Delay . . . . . . . . . . . . . . . . . . . . . . .
Decoupling Capacitors . . . . . . . . . . . . . . . . . . . . . . .
Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Parametric Values . . . . . . . . . . . . . . . . . . . .
Reduction of Electromagnetic
Interference (EMI) . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hybrid Circuit Guidelines . . . . . . . . . . . . . . . . . . . . .
SchmittTrigger Devices . . . . . . . . . . . . . . . . . . . . .
Oscillator Design with HighSpeed CMOS . . . . . .
Printed Circuit Board Layout . . . . . . . . . . . . . . . . . .
Definitions and Glossary of Terms . . . . . . . . . . . . .
Applications Assistance Form . . . . . . . . . . . . . . . . .
http://onsemi.com
23
24
24
28
31
31
38
40
41
43
44
44
45
46
48
49
49
50
51
52
53
56
INTRODUCTION
due to the selfaligning gate feature. This process uses the
gate to define the channel during processing, eliminating
registration errors and, therefore, the need for gate overlaps.
The elimination of the gate overlap significantly lowers the
gate capacitance, resulting in higher speed capability. The
smaller gate length also results in higher drive capability per
unit gate width, ensuring more efficient use of chip area.
Immunity enhancements to electrostatic discharge (ESD)
damage and latch up are ongoing. Precautions should still be
taken, however, to guard against electrostatic discharge and
latch up.
ON Semiconductorss HighSpeed CMOS family has a
broad range of functions from basic gates, flipflops, and
counters to buscompatible devices. The family is made up
of devices that are identical in pinout and are functionally
equivalent to LSTTL devices, as well as the most popular
metalgate devices not available in TTL. Thus, the designer
has an excellent alternative to existing families without
having to become familiar with a new set of device numbers.
N+
P+
N+
P+
P+
N+
N
120 m
POLY
METAL
PSG
OXIDE
HIGHSPEED
SILICONGATE
HSCMOS
N+
N+
P
65 m
P+
P+
N
HANDLING PRECAUTIONS
HighSpeed CMOS devices, like all MOS devices, have
an insulated gate that is subject to voltage breakdown. The
gate oxide for HSCMOS devices breaks down at a
gatesource potential of about 100 volts. Some device inputs
are protected by a resistordiode network (Figure 2). New
input protection structure deletes the poly resistor (Figure 3)
Using the test setup shown in Figure 4, the inputs typically
withstand a > 2 kV discharge.
SILICONGATE
CMOS
INPUT
VCC
SILICONGATE
D1
150
CMOS
INPUT
POLY
50
TO CIRCUIT
D2
GND
VCC
190
VCC
10 M
HIGH VOLTAGE
DC SOURCE
TO CIRCUIT
Diffused
1.5 k
100 pF
TO INPUT
UNDER TEST
VZAP
VCC
OR
GROUND
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24
TTL
Characteristic
Input Current
CMOS
Symbol
LS
ALS
MC14000
HiSpeed
Unit
VCC/EE/DD
5 5%
5 5%
3.0 to 18
2.0 to 6.0
TA
0 to + 70
0 to + 70
40 to + 85
55 to + 125
_C
3.54
VIH min
2.0
2.0
3.54
VIL max
0.8
0.8
1.54
1.04
VOH min
2.7
2.7
VDD 0.05
VCC 0.1
VOL max
0.5
0.5
0.05
0.1
IINH
20
20
IINL
400
200
0.3
03
1.0
10
IOH
0.4
0.4
2.1 @ 2.5 V
4.0 @
VCC 0.8 V
mA
IOL
8.0
8.0
0.44 @ 0.4 V
4.0 @ 0.4 V
mA
0.90/1.354
50(10)2
DCM
0.3/0.7
0.3/0.7
1.454
20
20
50(1)2
TTL
Characteristic
CMOS
Symbol
LS
ALS
MC14000
HiSpeed
Unit
IG
0.4
0.2
0.0001
0.0005
mA
Power/Gate (Quiescent)
PG
2.0
1.0
0.0006
0.001
mW
Propagation Delay
tp
9.0
7.0
125
8.0
ns
18
7.0
0.075
0.01
pJ
fmax
33
35
4.0
40
MHz
fmax
40
45
5.0
40
MHz
Unit
TTL
Characteristic
FlipFlop, Dtype:
tPLH/tPHL(5) (Clock to Q)
Counter:
tPLH/tPHL(5) (Clock to Q)
Product No.
CMOS
LS
ALS
MC14000
HiSpeed
SN74LS00
SN74ALS00
MC14001B
74HC00
Typical
(10)3
(5)3
25
(8)3 10
ns
Maximum
(15)3
10
250
(15)3 20
Product No.
SN74LS74
SN74ALS74
MC14013B
74HC74
Typical
(25)3
(12)3
175
(23)2 25
ns
Maximum
(40)3
20
350
(30)3 32
Product No.
SN74LS163
SN74ALS163
MC14163B
74HC163
Typical
(18)3
(10)3
350
(20)3 22
ns
Maximum
(27)3
24
700
(27)3 29
NOTES:
1. Specifications are shown for the following conditions:
a) VDD (CMOS) = 5.0 V 10% for dc tests, 5.0 V for ac tests; VCC (TTL) = 5.0 V 5% for dc tests, 5.0 V for ac tests
b) Basic Gates: LS00 or equivalent
c) TA = 25_C
d) CL = 50 pF (ALS, HC), 15 pF (LS, 14000 and HiSpeed)
e) Commercial grade product
2. ( ) fanout to LSTTL
3. ( ) CL = 15 pF
4. DC input voltage specifications are proportional to supply voltage over operating range.
5. The number specified is the larger of tPLH and tPHL for each device.
http://onsemi.com
25
VCC
TO OFFBOARD
CONNECTION
R1
CMOS
INPUT
OR
OUTPUT
TO OFFBOARD
CONNECTION
R2
D1
D2
CMOS
INPUT
OR
OUTPUT
GND
Advantage: R2 < R1 for the same level of
protection. Impact on ac and dc
characteristics is minimized.
Figure 5. Networks for Minimizing ESD and Reducing CMOS Latch Up Susceptibility
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26
RECOMMENDED READING
Requirements for Handling ElectrostaticDischarge
Sensitive (ESDS) Devices EIA Standard EIA625
Available by writing to:
Global Engineering Documents
15 Inverness Way East
Englewood, Colorado 80112
Or by calling:
18008547179 in the USA or CANADA or
(303) 3977956 International
S. Cherniak, A Review of Transients and Their Means of
Suppression, Application Note843, ON Semiconductor
Products Inc., 1982.
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27
2
5
NOTES:
1. 1/16 inch conductive sheet stock covering bench-top work
area.
2. Ground strap.
3. Wrist strap In contact with skin.
4. Static neutralizer. (ionized air blower directed at work.
Primarily for use in areas where direct grounding is
impractical.
5. Room humidifier. Primarily for use in areas where the
relative humidity is less than 45%. Caution: building
heating and cooling systems usually dry the air causing
the relative humidity inside a building to be less than
outside humidity.
R=1M
ICC
LATCH
UP MODE
IS
SECONDARY
BREAKDOWN
LOW CURRENT
JUNCTION
AVALANCHE
VS
DATA SHEET MAXIMUM SUPPLY RATING
VCC
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POWER SUPPLY
BATTERY TRICKLE
RECHARGE
CMOS
SYSTEM
BATTERY TRICKLE
RECHARGE
BATTERY BACKUP
SYSTEM
HC4049
HC4050
CMOS
SYSTEM
CMOS
SYSTEM
HC4049
HC4050
A
CPD =
ICC (dynamic)
CL
VCC f
PD = CPDVCC2f + VCCICC
PD = CPDVCC2f + VCCICC + ICCVCC
(1 + 2 + + n)
(HC)
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Gates:
Latches:
FlipFlops:
Decoders/
Switch one address pin which changes two
Demultiplexers: outputs.
= 1812 W
Data Selectors/ Switch one address input with the correMultiplexers: sponding data inputs at opposite logic
levels so that the output switches.
VCC = 5 V
Counters:
Shift
Registers:
Transceivers:
Monostables:
Parity
Generators:
Encoders:
Display
Drivers:
f = 1 kHz
3
50 pF
4
50 pF
f = 1 MHz
POWER (WATTS)
Analog
Switches:
2
10
10 k
SN74LS00
SN74ALS00
2
1m
5
2
100
5
MC7400
VCC = 5 Vdc
MC74HC00
57
2 5 7
2
5 7
2
5 7
2
100 k
1M
10 M
100 M
FREQUENCY @ 50% DUTY CYCLE (Hz)
5 7
1G
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INPUTS
FROM
EDGE
CONNECTOR
100 k
v v
R1
10 pF
v Vin v VCC
HCT
R1 = R2 = HIGH Z
HSCMOS
DEVICE
VCC
R2
RS
HC
OUTPUTS
All HSCMOS outputs, with the exception of the
HCU04A, are buffered to ensure consistent output voltage
and current specifications across the family. All buffered
outputs have guaranteed output voltages of VOL = 0.1 V and
VOH = VCC 0.1 V for Iout 20 A ( 20 HSCMOS
loads).
The output drives for standard drive devices are such
that 74HC/HCT devices can drive ten LSTTL loads and
maintain a VOL 0.4 V and VOH VCC 0.8 V across the
full temperature range; busdriver devices can drive fifteen
LSTTL loads under the same conditions.
The outputs of all HSCMOS devices are limited to
externally forced output voltages of 0.5 Vout VCC
+ 0.5 V. For externally forced voltages outside this range a
http://onsemi.com
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150 W
D1
3 pF
D2
Vin
2 pF
Figure 15. Input Model for Vin > VCC or Vin < GND
Vout
D1
3 pF
D2
2 pF
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32
25
20
15
10
TYPICAL
TA = 25_C
5
EXPECTED MINIMUM *, TA = 25125_C
0
0
0.5
1.0
1.5
Vout, OUTPUT VOLTAGE (V)
20
15
10
TYPICAL
TA = 25_C
EXPECTED MINIMUM *, TA = 25125_C
0
2.0
2.0
1.5
TYPICAL
TA = 25_C
25
20
TA = 25_C
TA = 85_C
15
TA = 125_C
10
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
Vout, OUTPUT VOLTAGE (V)
3.5
4.0
20
TA = 85_C
TA = 125_C
10
4.0
3.5
25
TA = 85_C
TA = 125_C
15
EXPECTED MINIMUM CURVES*
10
5
0
0
1.0
2.0
3.0
4.0
Vout, OUTPUT VOLTAGE (V)
3.0
2.5
2.0
1.5
Vout, OUTPUT VOLTAGE (V)
1.0
0.5
TYPICAL TA = 25_C
TA = 25_C
TA = 25_C
15
0
4.5
4.5
TYPICAL
TA = 25_C
20
25
25
1.0
0.5
Vout, OUTPUT VOLTAGE (V)
5.0
20
TA = 85_C
TA = 125_C
15
EXPECTED MINIMUM CURVES*
10
5
0
6.0
6.0
TYPICAL TA = 25_C
TA = 25_C
5.0
4.0
3.0
2.0
Vout, OUTPUT VOLTAGE (V)
*The expected minimum curves are not guarantees, but are design aids.
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1.0
35
30
25
20
TYPICAL
TA = 25_C
15
10
5
0
0
0.5
1.0
1.5
Vout, OUTPUT VOLTAGE (V)
30
25
20
TYPICAL
TA = 25_C
15
10
5
0
2.0
2.0
1.5
30
35
TA = 25_C
25
TA = 85_C
20
TA = 125_C
15
EXPECTED MINIMUMS*
10
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
Vout, OUTPUT VOLTAGE (V)
3.5
4.0
30
25
TA = 85_C
TA = 125_C
20
15
EXPECTED MINIMUMS*
10
5
0
4.5
4.5
TA = 25_C
TYPICAL
TA = 25_C
4.0
3.5
3.0
2.5
2.0
1.5
Vout, OUTPUT VOLTAGE (V)
1.0
0.5
35
35
TYPICAL
TA = 25_C
30
1.0
0.5
Vout, OUTPUT VOLTAGE (V)
TA = 25_C
25
TA = 85_C
20
TA = 125_C
15
EXPECTED MINIMUMS*
10
5
0
0
1.0
2.0
3.0
4.0
Vout, OUTPUT VOLTAGE (V)
5.0
TA = 25_C
25
TA = 85_C
20
TA = 125_C
15
10
EXPECTED MINIMUMS*
5
0
6.0
6.0
TYPICAL
TA = 25_C
30
5.0
4.0
3.0
2.0
Vout, OUTPUT VOLTAGE (V)
*The expected minimum curves are not guarantees, but are design aids.
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1.0
3STATE OUTPUTS
VCC
HIGH Z
OUTPUT
10 pF
LOW Z
VCC
INPUT/OUTPUT PINS
R1 = R2 = HIGH Z
R1
INTERNAL
CIRCUITRY
OUTPUT
R2
HIGH Z
15 pF
OUTPUT
INTERNAL
CIRCUITRY
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I/O
INTERNAL
CIRCUITRY
BUS
VCC
HIGH Z
Ron
ANALOG
I/O
ENABLE INPUT
(HIGH = 3STATE)
ANALOG
O/I
HIGH Z
GND OR VEE
GND OR VEE
ENABLE INPUT
(LOW = 3STATE)
BUS TERMINATION
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36
VCC
BUS
VCC
VCC
I
(H)
(L)
R
BUS
(a) USING A PULL-UP RESISTOR
Figure 36.
BUS LINES
ENABLE
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VCC
R1
HSCMOS
(LINE DRIVER)
HSCMOS
(RECEIVER)
W
W
R2
R1 = 1.5 k
R1 = 1.0 k
VCC
R3
HSCMOS
HSCMOS
R2
R4
W
W
R1 = R3 = 3.0 k
R2 = R4 = 2 k
1.5
0.5
CMOS LATCH UP
RECOMMENDED READING
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38
PCHANNEL
NCHANNEL
INPUT
VCC
N+
PCHANNEL
OUTPUT
VCC
FIELD OXIDE
P+
P+
OUTPUT
GND
NCHANNEL
OUTPUT
FIELD OXIDE
N+
N SUBSTRATE
N+
P+
FIELD OXIDE
P WELL
PCHANNEL OUTPUT
P WELL RESISTANCE
Q1
P+
VCC
P+
GND
VCC
N+
N+
Q2
N SUBSTRATE RESISTANCE
NCHANNEL OUTPUT
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GND
800
700
600
SOIC
PACKAGE
PLASTIC
DIP
500
400
300
TSSOP
PACKAGE
200
100
40
40
80
120
PD = ICCVCC + ICCVCC
PD = CPDVCC2f
PD = VCCICC
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PD = (CL + CPD)VCC2f
TJ = TA + PD(JA)
where
TJ
TA
PD
PD = VCCICC + VCCICC(, + 2 + + n)
+ (CL + CPD)VCC2f
(2)
TJ = TC + PD(JC)
(3)
(1)
or
No.
Leads
Body
Style
Body
Material
Body
WL
Die
Bonds
Die Area
(Sq. Mils)
Flag Area
(Sg. Mils)
Avg.
Max.
14
16
20
DIL
DIL
DIL
Epoxy
Epoxy
Epoxy
1/4 3/4
1/4 3/4
0.35 0.35
Epoxy
Epoxy
Epoxy
4096
4096
4096
6,400
12,100
14,400
38
34
N/A
61
54
N/A
NOTES:
1. All plastic packages use copper lead frames.
2. Body style DIL is Dual-In-Line.
3. Standard Mounting Method: Dual-In-Line Socket or P/C board with no contact between bottom of package and socket or P/C board.
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AIR FLOW
Time, Hours
Time, Years
80
1,032,200
117.8
90
419,300
47.9
100
178,700
20.4
110
79,600
9.4
120
37,000
4.2
130
17,800
2.0
140
8,900
1.0
300
0.63
400
0.88
0.5
TJ = 90 C
250
TJ = 100 C
0.4
TJ = 110 C
200
TJ = 120 C
TJ = 130 C
Power Dissipation
(mW)
1
1
10
100
TIME, YEARS
PROCEDURE
Figure 43. Failure Rate versus Time
Junction Temperature
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1000
Cdvc
dt
CL = 150 pF
IOS = 17.3 mA
CV
t
so
t =
= 18 ns + 13 ns
CV
I
= 31 ns
or
t =
C(0.5 VCC)
I
tPHL (0 pF) = 18 ns +
= 18 ns + ( 6.5 ns)
tPHL = 11.5 ns
Bus Drivers
VCC
25_C
85_C
125_C
25_C
85_C
125_C
Unit
2.0
4.5
6.0
1.89
18.5
35.2
1.83
15.0
28.0
1.80
13.4
24.6
3.75
37.0
70.6
3.64
30.0
56.1
3.60
26.6
49.2
mA
2.0
4.5
6.0
1.55
17.3
33.4
1.55
14.0
26.5
1.55
12.5
23.2
2.45
27.2
52.6
2.45
22.1
41.7
2.43
19.6
36.5
mA
Parameter
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TEMPERATURE EFFECTS ON
DC AND AC PARAMETERS
1.5
1.0
IOH, IOL
RC, tPLH, tPHL, tTLH, tTHL
0.5
50
50
100
150
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
2.0
3.0
4.0
5.0
6.0
5.0
VCC = 5 Vdc
4.0
TA = 55C
3.0
TA = 125C
2.0
VIL
VIH
TA = 25C
1.0
1.0
2.0
3.0
4.0
5.0
CL = 50 pF
3.0
2.0
1.0
2.0
3.0
4.0
5.0
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44
6.0
V out
DECOUPLING CAPACITORS
IGND
ICC
IGND
ICC
V out
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VCC
INTERFACING
HSCMOS devices have a wide operating voltage range
(VCC = 2 to 6 V) and sufficient current drive to interface with
most other logic families available today. In this section,
various interface schemes are given to aid the designer (see
Figure 50 through Figure 55). The various types of CMOS
devices with their input/output levels and comments are
given in 6.
ON Semiconductor presently has available several
CMOS memories and microprocessors (see 7) which are
designed to directly interface with HighSpeed CMOS.
With these devices now available, the designer has an
attractive alternative to LSTTL/NMOS, and a total
HSCMOS system is now possible. (See SG102, CMOS
System IC Selection Guide, for more information.)
Device designators are as follows:
HC
GND
LSTTL
DEVICE
HCT
HC
DEVICE
3V
GND
HCU
PULL-UP
RESISTOR
GND
LSTTL
DEVICE
HC4049
OR
HC4050
HC
DEVICE
VCC = 2 6 V
GND
STANDARD
CMOS
MC14049UB/14050B
HC
DEVICE
VCC
VDD/VCC
GND
HC OR HCT
DEVICE
DIRECT
INTERFACE
LSTTL
DEVICE
LEVEL
SHIFTER
GND
GND
HSCMOS/
STANDARD CMOS
VCC
STANDARD CMOS/
HSCMOS
GND
LSTTL
DEVICE
DIRECT
INTERFACE
HCT
DEVICE
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46
v v
Device
Input Level
Output Level
Comments
HCXXX
CMOS
CMOS
HC4XXX
CMOS
CMOS
HCUXX
CMOS
CMOS
HCTXXX
TTL
CMOS
CMOS
CMOS
MC14049UB
MC14050B
MC14504B
0.5
Vin
18 V
CMOS or TTL
RECOMMENDED READING
MCM6147
MCM61L47
MCM68HC34
CMOS Microprocessors
MC68HC01
MC68HC03
MC68HC11A8
MC68HC11D4
MC68HC811A2
MC68HC811D4
MC68HC04P3
MC146805E2
MC146805F2
MC146805G2
MC146805H2
MC1468705F2
MC1468705G2
MC68HC05C4
MC68HSC05C4
MC68HC05C8
MC68HC805C4
MC68HC000
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47
variation to the end user. However, this does not hold true for
the mean value of the total devices processed. The mean
value, commonly referred to as a typical value, shifts over
processing and therefore varies from lot to lot or even wafer
to wafer within a lot.
As with all processing or manufacturing, the total devices
being produced fit the normal distribution or bell curve of
Figure 56. In order to guarantee a valid typical value, a
typical number plus a tolerance, would have to be specified
and tested (see Figure 57). However, this would greatly
increase processing costs which would have to be absorbed
by the consumer.
In some cases, the devices actual values are so small that
the resolution of the automatic test equipment determines
the guaranteed limit. An example of this is quiescent supply
current and input leakage current.
Most manufacturers provide typical numbers by one of
two methods. The first method is to simply double or halve,
depending on the parameter, the guaranteed limit to
determine a typical number. This would theoretically put all
processed lots in the middle of the process window. Another
approach to typical numbers is to use a typical value that is
derived from the aforementioned experimental lots.
However, neither method accurately reflects the mean value
of devices any one consumer can expect to receive.
Therefore, the use of typical parametric numbers for
design purposes does not constitute sound engineering
design practice. Worst case analysis dictates the use of
guaranteed minimum or maximum values. The only
possible exception would be when no guaranteed value is
given. In this case a typical value may be used as a ballpark
figure.
MIN
LIMIT
MAX
LIMIT
(a)
(b)
Figure 56.
MEAN (TYP)
VALUE
MAX
VALUE
MIN
REJECT VALUE
REGION
Figure 57.
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REJECT
REGION
REJECT
REGION
REDUCTION OF ELECTROMAGNETIC
INTERFERENCE (EMI)
SHIELDING MANUFACTURERS
General Electric Co., Plastics Group, Pittsfield, MA
Mobay Chemical Corp., Pittsburgh, PA
WilsonFiberfil International, Evansville, IN
American Cyanamid Co., Wayne, NJ
Fillite U.S.A., Inc., Huntington, WV
Transnet Corp., Columbus, OH
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SCHMITTTRIGGER DEVICES
Schmitttrigger devices exhibit the effect of hysteresis.
Hysteresis is characterized by two different switching
threshold levels, one for positivegoing input transitions
and the other for negativegoing input transitions.
Schmitt triggers offer superior noise immunity when
compared to standard gates and inverters. Applications for
Schmitt triggers include line receivers, sine to square wave
converters, noise filters, and oscillators. ON Semiconductor
offers six versatile Schmitttrigger devices in the
HighSpeed CMOS logic family (see 8).
The typical voltage transfer characteristics of a standard
CMOS inverter and a CMOS Schmitttrigger inverter are
compared in Figure 58 and Figure 59. The singular transfer
threshold of the standard inverter is replaced by two distinct
thresholds in a Schmitttrigger inverter. During a
positivegoing transition of Vin, the output begins to go low
after the VT+ threshold is reached. During a negativegoing
Vin transition, Vout begins to go high after the VT threshold
is reached. The difference between VT+ and VT is defined
as VH, the hysteresis voltage.
As a direct result of hysteresis, Schmitttrigger circuits
provide excellent noise immunity and the ability to square
VCC
HC14A
HCT14A
HC132A
Vout
Vin
VCC
VT
VT+
Vout
VH
Vin
VCC
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50
CRYSTAL OSCILLATORS
1/6 HCU04A
OSCin
OSCout2
OSCout1
RC OSCILLATORS
1/6 HCU04A
R1
C1
C2
BUFFER
Vout
R2
BUFFER
Rf
Choosing R1
W W
+
R1
C 2R1 R2 10 R1
C 100 pF
1k
R1 1 M
1
f OSC
2.3 R1C
Rs
1
Cs
Re
Xe
Co
Values are supplied by the crystal manufacturer
(parallel resonant crystal)
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51
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52
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53
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54
tr
tf
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55
Job Title:
Company:
Phone/Position:
CHAPTER 3
Data Sheets
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57
MC74HC00A
Quad 2-Input NAND Gate
HighPerformance SiliconGate CMOS
The MC74HC00A is identical in pinout to the LS00. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 32 FETs or 8 Equivalent Gates
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
1
14
SOIC14
D SUFFIX
CASE 751A
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
1
3
2
1
14
4
6
5
Y = AB
10
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Y3
12
11
13
HC
00A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
Y2
9
8
HC00A
AWLYWW
Y1
Y4
FUNCTION TABLE
PIN 14 = VCC
PIN 7 = GND
Inputs
B4
A4
Y4
B3
A3
Y3
14
13
12
11
10
A1
B1
Y1
A2
B2
Y2
GND
MC74HC00AN
AWLYYWW
Output
L
L
H
H
L
H
L
H
H
H
H
L
ORDERING INFORMATION
58
Device
Package
Shipping
MC74HC00AN
PDIP14
2000 / Box
MC74HC00AD
SOIC14
55 / Rail
MC74HC00ADR2
SOIC14
2500 / Reel
MC74HC00ADT
TSSOP14
96 / Rail
MC74HC00ADTR2
TSSOP14
2500 / Reel
MC74HC00A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
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59
MC74HC00A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
VOH
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
VOL
Iin
ICC
6.0
0.1
1.0
1.0
6.0
1.0
10
40
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Parameter
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V, VEE = 0 V
CPD
22
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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MC74HC00A
tf
INPUT
A OR B
tr
VCC
90%
50%
10%
GND
tPLH
tPHL
90%
50%
10%
OUTPUT Y
tTLH
tTHL
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
A
Y
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MC74HC02A
Quad 2-Input NOR Gate
HighPerformance SiliconGate CMOS
The MC74HC02A is identical in pinout to the LS02. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
1
14
SOIC14
D SUFFIX
CASE 751A
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
MC74HC02AN
AWLYYWW
HC02A
AWLYWW
1
2
1
3
14
Y1
5
4
6
Y2
Y=A+B
8
10
9
HC
02A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
Y3
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
11
13
12
FUNCTION TABLE
Y4
Inputs
PIN 14 = VCC
PIN 7 = GND
PIN ASSIGNMENT
Y1
14
VCC
A1
13
Y4
B1
12
B4
Y2
11
A4
A2
10
Y3
B2
B3
GND
Output
L
L
H
H
L
H
L
H
H
L
L
L
ORDERING INFORMATION
A3
62
Device
Package
Shipping
MC74HC02AN
PDIP14
2000 / Box
MC74HC02AD
SOIC14
55 / Rail
MC74HC02ADR2
SOIC14
2500 / Reel
MC74HC02ADT
TSSOP14
96 / Rail
MC74HC02ADTR2
TSSOP14
2500 / Reel
MC74HC02A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.7
5.2
VOH
2.4 mA
4.0 mA
5.2 mA
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63
MC74HC02A
v
v
v
v
v
v
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
Iin
ICC
2.4 mA
4.0 mA
5.2 mA
VCC
V
55 to
25_C
2.0
4.5
6.0
85_C
125C
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Unit
V
6.0
0.1
1.0
1.0
6.0
1.0
10
40
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
22
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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64
MC74HC02A
tf
INPUT
A OR B
TEST POINT
tr
VCC
90%
50%
10%
OUTPUT
DEVICE
UNDER
TEST
GND
tPLH
tPHL
CL*
90%
50%
10%
OUTPUT Y
tTLH
tTHL
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65
MC74HC03A
Quad 2-Input NAND Gate
with Open-Drain Outputs
HighPerformance SiliconGate CMOS
The MC74HC03A is identical in pinout to the LS03. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC03A NAND gate has, as its outputs, a highperformance
MOS NChannel transistor. This NAND gate can, therefore, with a
suitable pullup resistor, be used in wiredAND applications. Having
the output characteristic curves given in this data sheet, this device can
be used as an LED driver or in any other application that only requires
a sinking current.
Output Drive Capability: 10 LSTTL Loads With Suitable Pullup
Resistor
Outputs Directly Interface to CMOS, NMOS and TTL
High Noise Immunity Characteristic of CMOS Devices
Operating Voltage Range: 2 to 6V
Low Input Current: 1A
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 28 FETs or 7 Equivalent Gates
DESIGN GUIDE
Value
Unit
Criteria
7.0
ea
1.5
ns
5.0
0.0075
pJ
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
1
14
SOIC14
D SUFFIX
CASE 751A
14
PIN 14 = VCC
PIN 7 = GND
* Denotes opendrain outputs
OUTPUT
PROTECTION
DIODE
3,6,8,11
Y*
HC
03A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
FUNCTION TABLE
Inputs
VCC
HC03A
AWLYWW
1
LOGIC DIAGRAM
MC74HC03AN
AWLYYWW
Output
L
L
H
H
L
H
L
H
Z
Z
Z
L
Z = High Impedance
A
B
1,4,9,12
2,5,10,13
ORDERING INFORMATION
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
A1
B1
Y1
A2
B2
Y2
GND
66
Device
Package
Shipping
MC74HC03AN
PDIP14
2000 / Box
MC74HC03AD
SOIC14
55 / Rail
MC74HC03ADR2
SOIC14
2500 / Reel
MC74HC03ADT
TSSOP14
96 / Rail
MC74HC03ADTR2
TSSOP14
2500 / Reel
MC74HC03A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
VOL
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Symbol
Parameter
Condition
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
6.0
0.1
1.0
1.0
ICC
6.0
1.0
10
40
IOZ
6.0
0.5
5.0
10
Iin
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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67
MC74HC03A
AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)
Symbol
Parameter
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
tPLZ,
tPZL
2.0
3.0
4.5
6.0
120
45
24
20
150
60
30
26
180
75
36
31
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
10
10
10
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V, VEE = 0 V
CPD
8.0
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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68
MC74HC03A
VCC
tr
tf
INPUT A
Rpd
OUTPUT
DEVICE
UNDER
TEST
GND
tPZL
tPLZ
HIGH
IMPEDANCE
90%
50%
10%
OUTPUT Y
1k
VCC
90%
50%
10%
10%
TEST
POINT
CL*
VOL
tTHL
25
VCC=5V
TYPICAL
T=25C
20
T=25C
15
T=85C
10
T=125C
EXPECTED MINIMUM*
0
0
2
3
4
VO, OUTPUT VOLTAGE (VOLTS)
*The expected minimum curves are not guarantees, but are design aids.
VCC
+
VR
+
VF
VCC
PULLUP
RESISTOR
A1
B1
A2
B2
An
Bn
1/4
HC03
Y1
1/4
HC03
OUTPUT
LED1
1/4
HC03
1/4
HC03
DESIGN EXAMPLE
CONDITIONS: ID 10mA
USING FIGURE NO TAG TYPICAL
CURVE, at ID=10mA, VDS 0.4V
Y2
LED2
LED
ENABLE
1/4
HC03
VCC
NR + VCC *IVDF * VO
* 0.4V
+ 5V * 1.7V
10mA
+ 290W
Yn
OUTPUT = Y1 Y2 . . . Yn
= A1B1 A2B2 . . . AnBn
USE R = 270
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69
MC74HC04A
Hex Inverter
HighPerformance SiliconGate CMOS
The MC74HC04A is identical in pinout to the LS04 and the
MC14069. The device inputs are compatible with Standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
The device consists of six threestage inverters.
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
MC74HC04AN
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
HC04A
AWLYWW
1
LOGIC DIAGRAM
A1
A2
A3
11
10
13
12
14
HC
04A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
Y1
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Y2
Y3
Y=A
A4
A5
A6
FUNCTION TABLE
Y4
Inputs
Outputs
L
H
H
L
Y5
Y6
A6
Y6
A5
Y5
A4
Y4
14
13
12
11
10
ORDERING INFORMATION
Device
Package
Shipping
MC74HC04AN
PDIP14
2000 / Box
MC74HC04AD
SOIC14
55 / Rail
MC74HC04ADR2
1
A1
Y1
A2
Y2
A3
Y3
GND
70
SOIC14
2500 / Reel
MC74HC04ADT
TSSOP14
96 / Rail
MC74HC04ADTR2
TSSOP14
2500 / Reel
MC74HC04A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
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71
MC74HC04A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
VOH
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
VOL
Iin
ICC
6.0
0.1
1.0
1.0
6.0
1.0
10
40
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Parameter
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
20
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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72
MC74HC04A
tf
INPUT A
tr
VCC
90%
50%
10%
GND
tPLH
tPHL
90%
50%
10%
OUTPUT Y
tTLH
tTHL
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
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73
MC74HCT04A
Hex Inverter
With LSTTLCompatible Inputs
HighPerformance SiliconGate CMOS
The MC74HCT04A may be used as a level converter for interfacing
TTL or NMOS outputs to HighSpeed CMOS inputs.
The HCT04A is identical in pinout to the LS04.
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
MC74HCT04AN
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
HCT04A
AWLYWW
LOGIC DIAGRAM
1
14
A1
A2
A3
Y2
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Y3
Y=A
A4
A5
A6
11
10
13
12
HCT
04A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
Y1
Pin 14 = VCC
Pin 7 = GND
Y4
FUNCTION TABLE
Inputs
Outputs
L
H
H
L
Y5
Y6
A6
Y6
A5
Y5
A4
Y4
14
13
12
11
10
ORDERING INFORMATION
Device
1
A1
2
Y1
3
A2
4
Y2
5
A3
6
Y3
7
GND
74
Package
Shipping
MC74HCT04AN
PDIP14
2000 / Box
MC74HCT04AD
SOIC14
55 / Rail
MC74HCT04ADR2
SOIC14
2500 / Reel
MC74HCT04ADT
TSSOP14
96 / Rail
MC74HCT04ADTR2
TSSOP14
2500 / Reel
MC74HCT04A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
TA
tr, tf
Max
Unit
4.5
5.5
VCC
55
+ 125
_C
500
ns
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75
MC74HCT04A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
Vout = 0.1V
|Iout| 20A
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
VOH
Vin = VIL
|Iout| 20A
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
4.5
3.98
3.84
3.70
VOL
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.40
|Iout| 4.0mA
Vin = VIL
Vin = VIH
|Iout| 20A
|Iout| 4.0mA
Vin = VIH
5.5
0.1
1.0
1.0
ICC
5.5
10
40
ICC
Iin
5.5
55C
25 to 125C
2.9
2.4
mA
1. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + ICC.
Parameter
55 to 25C
85C
125C
Unit
tPLH,
tPHL
15
17
19
21
22
26
ns
tTLH,
tTHL
15
19
22
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
22
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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76
MC74HCT04A
tf
INPUT A
tr
3.0V
2.7V
1.3V
0.3V
GND
tPLH
tPHL
90%
1.3V
10%
OUTPUT Y
tTLH
tTHL
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
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77
MC74HCU04A
Hex Unbuffered Inverter
HighPerformance SiliconGate CMOS
The MC74HCU04A is identical in pinout to the LS04 and the
MC14069UB. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of six singlestage inverters. These inverters
are well suited for use as oscillators, pulse shapers, and in many other
applications requiring a highinput impedance amplifier. For digital
applications, the HC04A is recommended.
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
MC74HCU04AN
AWLYYWW
1
14
Configurations
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 12 FETs or 3 Equivalent Gates
SOIC14
D SUFFIX
CASE 751A
HCU04A
AWLYWW
1
14
HCU
04A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
LOGIC DIAGRAM
A1
A2
A3
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Y1
Y2
PIN ASSIGNMENT
Y3
A1
14
VCC
Y1
13
A6
A2
12
Y6
Y2
11
A5
A3
10
Y5
Y3
A4
GND
Y4
Y=A
A4
A5
A6
11
10
13
12
Y4
Y5
Y6
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
A
Outputs
Y
L
H
H
L
ORDERING INFORMATION
Device
78
Package
Shipping
MC74HCU04AN
PDIP14
2000 / Box
MC74HCU04AD
SOIC14
55 / Rail
MC74HCU04ADR2
SOIC14
2500 / Reel
MC74HCU04ADT
TSSOP14
96 / Rail
MC74HCU04ADTR2
TSSOP14
2500 / Reel
MC74HCU04A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10mW/_C from 65_ to 125_C
SOIC Package: 7mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
No
Limit
ns
TA
tr, tf
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
Vout = 0.5 V*
|Iout|
20 A
2.0
3.0
4.5
6.0
1.7
2.5
3.6
4.8
1.7
2.5
3.6
4.8
l.7
2.5
3.6
4.8
VIL
2.0
3.0
4.5
6.0
0.3
0.5
0.8
1.1
0.3
0.5
0.8
1.1
0.3
0.5
0.8
1.1
Vin = GND
|Iout|
20 A
2.0
4.5
6.0
1.8
4.0
5.5
1.8
4.0
5.5
1.8
4.0
5.5
3.0
4.5
6.0
2.36
3.86
5.36
2.26
3.76
5.26
2.20
3.70
5.20
2.0
4.5
6.0
0.2
0.5
0.5
0.2
0.5
0.5
0.2
0.5
0.5
3.0
4.5
6.0
0.32
0.32
0.32
0.32
0.37
0.37
0.32
0.40
0.40
VOH
Vin = GND
VOL
|Iout|
|Iout|
|Iout|
2.4 mA
4.0 mA
5.2 mA
Vin = VCC
|Iout|
20 A
Vin = VCC
|Iout|
|Iout|
|Iout|
2.4 mA
4.0 mA
5.2 mA
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79
MC74HCU04A
v
v
v
v
Guaranteed Limit
Symbol
Iin
ICC
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
6.0
0.1
1.0
1.0
6.0
10
40
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
*For VCC = 2.0 V, Vout = 0.2 V or VCC 0.2 V.
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
70
40
14
12
90
45
18
15
105
50
21
18
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
15
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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80
MC74HCU04A
TEST POINT
tr
tf
DEVICE
UNDER
TEST
GND
tPLH
tPHL
90%
50%
10%
OUTPUT Y
OUTPUT
VCC
90%
50%
10%
INPUT A
tTHL
tTLH
CL*
LOGIC DETAIL
(1/6 of Device Shown)
VCC
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81
MC74HCU04A
TYPICAL APPLICATIONS
Crystal Oscillator
Stable RC Oscillator
1/6 HCU04A 1/6 HCU04A 1/6 HCU04A
R2
Vout
R2 > > R1
C1 < C2
1/6 HCU04A
R1
R2
R1
C2
C1
Vout
Schmitt Trigger
R2
1 M 1/6 HCU04A
R2 > 6R1
R1
1/6 HCU04A
1/6 HCU04A
INPUT
Vin
OUTPUT
Vout
1M
MultiStage Amplifier
LED Driver
+V
VCC
1/6 HCU04A
INPUT
1/6 HCU04A
1/6 HCU04A
1/6 HCU04A
OUTPUT
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82
MC74HC08A
Quad 2-Input AND Gate
HighPerformance SiliconGate CMOS
The MC74HC08A is identical in pinout to the LS08. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
1
14
SOIC14
D SUFFIX
CASE 751A
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
MC74HC08AN
AWLYYWW
HC08A
AWLYWW
1
1
3
2
14
Y1
4
6
5
HC
08A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
Y2
1
Y = AB
9
8
10
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Y3
12
11
13
Y4
FUNCTION TABLE
Inputs
PIN 14 = VCC
PIN 7 = GND
B4
A4
Y4
B3
A3
Y3
14
13
12
11
10
Output
L
L
H
H
L
H
L
H
L
L
L
H
ORDERING INFORMATION
1
A1
B1
Y1
A2
B2
Y2
GND
83
Device
Package
Shipping
MC74HC08AN
PDIP14
2000 / Box
MC74HC08AD
SOIC14
55 / Rail
MC74HC08ADR2
SOIC14
2500 / Reel
MC74HC08ADT
TSSOP14
96 / Rail
MC74HC08ADTR2
TSSOP14
2500 / Reel
MC74HC08A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
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84
MC74HC08A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
VOH
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
VOL
Iin
ICC
6.0
0.1
1.0
1.0
6.0
1.0
10
40
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Parameter
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V, VEE = 0 V
CPD
20
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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85
MC74HC08A
tr
tf
VCC
90%
INPUT
A OR B
50%
10%
GND
tPLH
tPHL
90%
50%
10%
OUTPUT Y
tTLH
tTHL
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
A
Y
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86
MC74HC14A
Hex Schmitt-Trigger
Inverter
HighPerformance SiliconGate CMOS
The MC74HC14A is identical in pinout to the LS14, LS04 and the
HC04. The device inputs are compatible with Standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
The HC14A is useful to square up slow input rise and fall times.
Due to hysteresis voltage of the Schmitt trigger, the HC14A finds
applications in noisy environments.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 60 FETs or 15 Equivalent Gates
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
1
14
SOIC14
D SUFFIX
CASE 751A
A2
A3
14
A5
A6
11
10
13
12
Y1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Y2
Y3
FUNCTION TABLE
Y4
Inputs
Outputs
L
H
H
L
Pin 14 = VCC
Pin 7 = GND
Y5
Y6
A6
Y6
A5
Y5
A4
Y4
14
13
12
11
10
ORDERING INFORMATION
Device
Package
Shipping
MC74HC14AN
PDIP14
2000 / Box
MC74HC14AD
SOIC14
55 / Rail
MC74HC14ADR2
A1
Y1
A2
Y2
A3
Y3
GND
HC
14A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
Y=A
A4
HC14A
AWLYWW
1
LOGIC DIAGRAM
A1
MC74HC14AN
AWLYYWW
87
SOIC14
2500 / Reel
MC74HC14ADT
TSSOP14
96 / Rail
MC74HC14ADTR2
TSSOP14
2500 / Reel
MC74HC14A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
No Limit*
No Limit*
No Limit*
ns
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88
MC74HC14A
DC CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
Vout = 0.1V
|Iout| 20A
2.0
3.0
4.5
6.0
1.50
2.15
3.15
4.20
1.50
2.15
3.15
4.20
1.50
2.15
3.15
4.20
Vout = 0.1V
|Iout| 20A
2.0
3.0
4.5
6.0
1.0
1.5
2.3
3.0
0.95
1.45
2.25
2.95
0.95
1.45
2.25
2.95
VT max
2.0
3.0
4.5
6.0
0.9
1.4
2.0
2.6
0.95
1.45
2.05
2.65
0.95
1.45
2.05
2.65
VT min
2.0
3.0
4.5
6.0
0.3
0.5
0.9
1.2
0.3
0.5
0.9
1.2
0.3
0.5
0.9
1.2
VHmax
Note 2
2.0
3.0
4.5
6.0
1.20
1.65
2.25
3.00
1.20
1.65
2.25
3.00
1.20
1.65
2.25
3.00
VHmin
Note 2
2.0
3.0
4.5
6.0
0.20
0.25
0.40
0.50
0.20
0.25
0.40
0.50
0.20
0.25
0.40
0.50
VOH
Vin VT min
|Iout| 20A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Symbol
Parameter
VT+ max
VT+ min
Condition
Vin VT min
VOL
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
Iin
ICC
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
6.0
0.1
1.0
1.0
6.0
1.0
10
40
1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
2. VHmin > (VT+ min) (VT max); VHmax = (VT+ max) (VT min).
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89
MC74HC14A
AC CHARACTERISTICS (CL = 50pF, Input tr = tf = 6ns)
Symbol
Parameter
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Cin
Maximum Input Capacitance
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
22
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
tf
INPUT A
tr
VCC
90%
50%
10%
GND
tPLH
tPHL
90%
OUTPUT Y
50%
10%
tTLH
tTHL
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
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90
MC74HC14A
4
3
(VT+)
VHtyp
2
(VT)
3
4
5
VCC, POWER SUPPLY VOLTAGE (VOLTS)
(a) A SchmittTrigger Squares Up Inputs With Slow Rise and Fall Times
VH
Vin
VCC
VH
VT+
VT
Vin
VCC
VT+
VT
GND
GND
VOH
VOH
Vout
Vout
VOL
VOL
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91
MC74HCT14A
Hex Schmitt-Trigger
Inverter with LSTTL
Compatible Inputs
HighPerformance SiliconGate CMOS
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
MC74HCT14AN
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
HCT14A
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
LOGIC DIAGRAM
A1
A2
A3
PIN ASSIGNMENT
Y1
Y2
Y3
Y=A
A4
Y4
PIN 14 = VCC
PIN 7 = GND
A5
A6
11
10
13
12
A1
14
VCC
Y1
13
A6
A2
12
Y6
Y2
11
A5
A3
10
Y5
Y3
A4
GND
Y4
Y5
Y6
ORDERING INFORMATION
Device
FUNCTION TABLE
Input
A
Output
Y
L
H
H
L
92
Package
Shipping
MC74HCT14AN
PDIP14
2000 / Box
MC74HCT14AD
SOIC14
55 / Rail
MC74HCT14ADR2
SOIC14
2500 / Reel
MC74HCT14A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
mW
Tstg
Storage Temperature
65 to + 150
_C
260
_C
_C
Iin
TL
Plastic DIP
SOIC Package
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
TA
tr, tf
Min
Max
Unit
4.5
5.5
VCC
55
+ 125
_C
ns
Temperature Limit
VCC
Volts
Test Conditions
55 to
25_C
85_C
125_C
Symbol
Parameter
VT+ max
Maximum PositiveGoing
Input Threshold Voltage
4.5
5.5
VT+ min
Minimum PositiveGoing
Input Threshold Voltage
4.5
5.5
VT max
Maximum PositiveGoing
Input Threshold Voltage
4.5
5.5
VT min
Minimum PositiveGoing
Input Threshold Voltage
4.5
5.5
VH max
Maximum Hysteresis
Voltage
4.5
5.5
VH min
Minimum Hysteresis
Voltage
4.5
5.5
0.4
0.4
0.4
0.4
0.4
04
VOH
Minimum HighLevel
Output Voltage
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
4.5
3.98
3.84
3.7
Min
Max
Min
1.9
2.1
1.2
1.4
Max
1.9
2.1
1.2
1.4
1.2
1.4
0.5
0.6
Min
Unit
1.9
2.1
1.2
1.4
1.2
1.4
0.5
0.6
1.4
1.5
Max
1.2
1.4
0.5
0.6
1.4
1.5
1.4
1.5
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
(continued)
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93
MC74HCT14A
v
v
v
v
Temperature Limit
Symbol
VOL
Parameter
ICC
ICC
Test Conditions
Min
85_C
Max
Min
125_C
Max
Min
Max
Unit
V
Vin VT+max
|Iout|
20 A
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin VT+max
|Iout|
4.0 mA
4.5
0.26
0.33
0.4
Maximum Input
Leakage Current
5.5
0.1
1.0
1.0
Maximum Quiescent
Supply Current
(per package)
5.5
1.0
10
40
Maximum LowLevel
Output Voltage
Iin
VCC
Volts
55 to
25_C
Additional Quiescent
Supply Current
55_C
25_C to
125_C
2.9
2.4
5.5
mA
Guaranteed Limit
55 to
25_C
Symbol
Parameter
Test Conditions
Min
85_C
Max
Min
125_C
Max
Min
Max
Unit
tPLH,
tPHL
Maximum Propagation
Delay, Input A to Output Y
(L to H)
Fig.
1&2
32
40
48
ns
tTLH,
tTHL
Maximum Output
Transition Time.
Any Output
Fig.
1&2
15
19
22
ns
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
32
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
tf
2.7 V
INPUT A 1.3 V
0.3 V
tr
TEST POINT
3V
OUTPUT
GND
tPLH
DEVICE
UNDER
TEST
tPHL
90%
1.3 V
10%
OUTPUT Y
tTLH
CL*
tTHL
*Includes all probe and jig capacitance
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94
MC74HC32A
Quad 2-Input OR Gate
HighPerformance SiliconGate CMOS
The MC74HC32A is identical in pinout to the LS32. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
1
14
SOIC14
D SUFFIX
CASE 751A
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
1
3
2
1
14
4
6
5
HC
32A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
Y2
Y = A+B
9
8
10
12
11
13
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Y3
Y4
FUNCTION TABLE
Inputs
B4
A4
Y4
B3
A3
Y3
14
13
12
11
10
B1
Y1
A2
HC32A
AWLYWW
Y1
PIN 14 = VCC
PIN 7 = GND
A1
MC74HC32AN
AWLYYWW
B2
Y2
Output
L
L
H
H
L
H
L
H
L
H
H
H
ORDERING INFORMATION
GND
95
Device
Package
Shipping
MC74HC32AN
PDIP14
2000 / Box
MC74HC32AD
SOIC14
55 / Rail
MC74HC32ADR2
SOIC14
2500 / Reel
MC74HC32ADT
TSSOP14
96 / Rail
MC74HC32ADTR2
TSSOP14
2500 / Reel
MC74HC32A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
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96
MC74HC32A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
6.0
0.1
1.0
1.0
VOH
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
VOL
Iin
Parameter
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V, VEE = 0 V
CPD
20
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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97
MC74HC32A
tr
tf
VCC
90%
INPUT
A OR B
50%
10%
GND
tPLH
tPHL
90%
50%
10%
OUTPUT Y
tTLH
tTHL
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
A
Y
B
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98
MC74HC74A
Dual D Flip-Flop with Set
and Reset
HighPerformance SiliconGate CMOS
The MC74HC74A is identical in pinout to the LS74. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two D flipflops with individual Set, Reset,
and Clock inputs. Information at a Dinput is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flipflop. The Set
and Reset inputs are asynchronous.
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
14
SOIC14
D SUFFIX
CASE 751A
14
CLOCK 1
Q1
Q1
PIN ASSIGNMENT
SET 1
PIN 14 = VCC
PIN 7 = GND
13
RESET 2
12
DATA 2
Q2
11
CLOCK 2
RESET 1
14
VCC
DATA 1
13
RESET 2
CLOCK 1
12
DATA 2
SET 1
11
CLOCK 2
Q1
10
SET 2
Q1
Q2
GND
Q2
Q2
10
SET 2
HC
74A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
DATA 1
HC74A
AWLYWW
1
LOGIC DIAGRAM
RESET 1
MC74HC74AN
AWLYYWW
FUNCTION TABLE
Inputs
Outputs
H
L
L
H
H
H
H
H
X
X
X
L
H
X
X
X
H
L
X
X
X
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
ORDERING INFORMATION
Device
*Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously.
99
Package
Shipping
MC74HC74AN
PDIP14
2000 / Box
MC74HC74AD
SOIC14
55 / Rail
MC74HC74ADR2
SOIC14
2500 / Reel
MC74HC74ADT
TSSOP14
96 / Rail
MC74HC74ADTR2
TSSOP14
2500 / Reel
MC74HC74A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
300
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
0
1000
600
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
VOH
2.4 mA
4.0 mA
5.2 mA
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100
MC74HC74A
v
v
v
v
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
Iin
ICC
2.4 mA
4.0 mA
5.2 mA
VCC
V
55 to
25_C
2.0
4.5
6.0
85_C
125_C
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Unit
V
6.0
0.1
1.0
1.0
6.0
2.0
20
80
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
VCC
V
55 to
25_C
125_C
Unit
4.8
10
24
28
4.0
8.0
20
24
MHz
100
75
20
17
125
90
25
21
150
120
30
26
ns
2.0
3.0
4.5
6.0
105
80
21
18
130
95
26
22
160
130
32
27
ns
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
10
10
10
pF
Parameter
fmax
2.0
3.0
4.5
6.0
6.0
15
30
35
tPLH,
tPHL
2.0
3.0
4.5
6.0
tPLH,
tPHL
tTLH,
tTHL
Cin
85_C
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
32
CPD
Power Dissipation Capacitance (Per FlipFlop)*
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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101
MC74HC74A
v
v
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tsu
2.0
3.0
4.5
6.0
80
35
16
14
100
45
20
17
120
55
24
20
ns
th
2.0
3.0
4.5
6.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
ns
2.0
3.0
4.5
6.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
ns
tw
2.0
3.0
4.5
6.0
60
25
12
10
75
30
15
13
90
40
18
15
ns
tw
2.0
3.0
4.5
6.0
60
25
12
10
75
30
15
13
90
40
18
15
ns
tr, tf
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
trec
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102
MC74HC74A
SWITCHING WAVEFORMS
tf
CLOCK
tw
tr
VCC
90%
50%
10%
tw
GND
Q or Q
GND
tPHL
50%
Q OR Q
1/fmax
tPLH
tPHL
tPLH
90%
50%
10%
50%
Q OR Q
tTLH
VCC
50%
SET OR
RESET
trec
tTHL
VCC
50%
CLOCK
Figure 1.
GND
Figure 2.
TEST POINT
VALID
DATA
VCC
50%
OUTPUT
GND
tsu
DEVICE
UNDER
TEST
th
VCC
CL*
50%
CLOCK
GND
Figure 3.
Figure 4.
4, 10
2, 12
5, 9
Q
DATA
3, 11
CLOCK
6, 8
Q
1, 13
RESET
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103
MC74HCT74A
Dual D Flip-Flop with Set
and Reset with LSTTL
Compatible Inputs
HighPerformance SiliconGate CMOS
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
1
14
SOIC14
D SUFFIX
CASE 751A
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
1
2
PIN ASSIGNMENT
RESET 1
14
DATA 1
13
VCC
RESET 2
CLOCK 1
12
DATA 2
SET 1
11
CLOCK 2
SET 2
Q1
Q1
10
Q2
GND
Q2
FUNCTION TABLE
PIN 14 = VCC
PIN 7 = GND
13
Inputs
Outputs
11
Q2
Q2
10
Design Criteria
Value
Units
34
ea.
1.5
ns
5.0
.0075
pJ
Q1
Q1
SET 2
HCT74A
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
LOGIC DIAGRAM
RESET 1
MC74HCT74AN
AWLYYWW
104
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
L
H
X
X
X
H
L
X
X
X
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
ORDERING INFORMATION
Package
Shipping
MC74HCT74AN
Device
PDIP14
2000 / Box
MC74HCT74AD
SOIC14
55 / Rail
MC74HCT74ADR2
SOIC14
2500 / Reel
MC74HCT74A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10mW/_C from 65_ to 125_C
SOIC Package: 7mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
VCC
55
+ 125
_C
500
ns
TA
tr, tf
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
4.5
3.98
3.84
3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.4
5.5
0.1
1.0
1.0
ICC
5.5
2.0
20
80
ICC
VOH
VOL
Iin
5.5
55_C
25_C to 125_C
2.9
2.4
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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105
MC74HCT74A
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
55 to
25_C
v 85_C
v 125_C
Unit
Symbol
Parameter
fmax
30
24
20
MHz
tPLH,
tPHL
24
30
36
ns
tPLH,
tPHL
24
30
36
ns
tTLH,
tTHL
15
19
22
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
32
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Guaranteed Limit
55 to
25_C
Symbol
Parameter
Fig.
Min
Max
85_C
Min
Max
125_C
Min
Max
Units
tsu
15
19
22
ns
th
ns
ns
tw
15
19
22
ns
tw
15
19
22
ns
tr, tf
trec
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106
500
500
500
ns
MC74HCT74A
SWITCHING WAVEFORMS
tw
tr
CLOCK
3V
tf
SET OR
RESET
3V
2.7 V
1.3 V
0.3 V
1.3 V
GND
tPHL
GND
Q OR Q
tw
1.3 V
1/fmax
tPLH
Q OR Q
tPLH
tPHL
1.3 V
Q OR Q
trec
90%
1.3 V
10%
3V
1.3 V
CLOCK
tTLH
tTHL
GND
Figure 1.
Figure 2.
VALID
TEST POINT
3V
DATA
1.3 V
OUTPUT
GND
tsu
DEVICE
UNDER
TEST
th
3V
1.3 V
CL*
GND
CLOCK
*Includes all probe and jig capacitance
Figure 3.
Figure 4.
4, 10
2, 12
5, 9
Q
DATA
3, 11
CLOCK
6, 8
Q
1, 13
RESET
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107
MC74HC86A
Quad 2-Input Exclusive
OR Gate
HighPerformance SiliconGate CMOS
The MC74HC86A is identical in pinout to the LS86. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
MC74HC86AN
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
HC86A
AWLYWW
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
1
14
2
4
Y1
Y2
Y= AB
= AB + AB
10
Y3
PIN 14 = VCC
PIN 7 = GND
12
11
13
14
VCC
B1
13
B4
Y1
12
A4
A2
11
Y4
B2
10
B3
Y2
A3
GND
Y3
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
FUNCTION TABLE
Y4
Inputs
PIN ASSIGNMENT
A1
HC
86A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
Output
L
L
H
H
L
H
L
H
L
H
H
L
ORDERING INFORMATION
108
Device
Package
Shipping
MC74HC86AN
PDIP14
2000 / Box
MC74HC86AD
SOIC14
55 / Rail
MC74HC86ADR2
SOIC14
2500 / Reel
MC74HC86ADT
TSSOP14
96 / Rail
MC74HC86ADTR2
TSSOP14
2500 / Reel
MC74HC86A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
2.4 mA
4.0 mA
5.2 mA
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109
MC74HC86A
v
v
v
v
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
Iin
ICC
2.4 mA
4.0 mA
5.2 mA
VCC
V
55 to
25_C
2.0
4.5
6.0
85_C
125_C
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Unit
V
6.0
0.1
1.0
1.0
6.0
1.0
10
40
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
100
80
20
17
125
90
25
21
150
110
31
26
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
10
10
10
pF
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
33
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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110
MC74HC86A
tr
tf
VCC
90%
50%
INPUT
A OR B
TEST POINT
10%
GND
OUTPUT
tPLH
tPHL
90%
OUTPUT Y
DEVICE
UNDER
TEST
CL*
50%
10%
tTLH
tTHL
*Includes all probe and jig capacitance
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111
MC74HC125A,
MC74HC126A
Quad 3-State Noninverting
Buffers
MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
1
14
A1
Y1
4
9
Y3
10
A3
11
13
12
A4
Y4
11
PIN 14 = VCC
PIN 7 = GND
Output
Inputs
Output
OE
OE
H
L
X
L
L
H
H
L
Z
H
L
X
H
H
L
H
L
Z
HC
12xA
ALYW
TSSOP14
DT SUFFIX
CASE 948G
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
Y3
OE1
14
VCC
A1
13
OE4
Y1
12
A4
OE2
11
Y4
A2
10
OE3
Y2
A3
GND
Y3
Y4
Device
HC126A
14
ORDERING INFORMATION
FUNCTION TABLE
Inputs
13
OE4
HC125A
Y2
10
OE3
12
OE2
HC12xA
AWLYWW
PIN ASSIGNMENT
A2
Y2
Y1
SOIC14
D SUFFIX
CASE 751A
OE1
MC74HC12xAN
AWLYYWW
Package
Shipping
MC74HC12xAN
PDIP14
2000 / Box
MC74HC12xAD
SOIC14
55 / Rail
MC74HC12xADR2
112
SOIC14
2500 / Reel
MC74HC12xADT
TSSOP14
96 / Rail
MC74HC12xADTR2
TSSOP14
2500 / Reel
MC74HC125A, MC74HC126A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
Vout
Iin
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
VCC
Vin, Vout
TA
tr, tf
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
Vout = 0.1 V
|Iout|
20 A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
Vin = VIH
|Iout|
20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH
Vin = VIH
VOL
|Iout|
|Iout|
|Iout|
3.6 mA
6.0 mA
7.8 mA
Vin = VIL
|Iout|
20 A
Vin = VIL
|Iout|
|Iout|
|Iout|
3.6 mA
6.0 mA
7.8 mA
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113
MC74HC125A, MC74HC126A
v
v
v
v
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
6.0
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
6.0
0.5
5.0
10
ICC
6.0
4.0
40
160
Iin
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
90
36
18
15
115
45
23
20
135
60
27
23
ns
tPLZ,
tPHZ
2.0
3.0
4.5
6.0
120
45
24
20
150
60
30
26
180
80
36
31
ns
tPZL,
tPZH
2.0
3.0
4.5
6.0
90
36
18
15
115
45
23
20
135
60
27
23
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
10
10
10
pF
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
30
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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114
MC74HC125A, MC74HC126A
SWITCHING WAVEFORMS
OE (HC125A)
tr
OUTPUT Y
GND
VCC
90%
50%
10%
INPUT A
VCC
OE (HC126A)
GND
50%
GND
tPHL
tPLH
VCC
50%
tf
tPZL tPLZ
90%
50%
10%
OUTPUT Y
tTHL
tTLH
HIGH
IMPEDANCE
50%
10%
VOL
90%
VOH
HIGH
IMPEDANCE
tPZH tPHZ
50%
OUTPUT Y
Figure 1.
Figure 2.
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
OUTPUT
1 k
CL *
VCC
OE
HC125A
(1/4 OF THE DEVICE)
VCC
OE
HC126A
(1/4 OF THE DEVICE)
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115
MC74HC132A
Quad 2-Input NAND Gate
with Schmitt-Trigger Inputs
HighPerformance SiliconGate CMOS
The MC74HC132A is identical in pinout to the LS132. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up
slowly changing waveforms.
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MARKING
DIAGRAMS
14
B1
A2
HC132A
AWLYWW
1
PIN ASSIGNMENT
4
Y2
5
9
8
B3
SOIC14
D SUFFIX
CASE 751A
Y1
Y = AB
A3
1
14
6
B2
MC74HC132AN
AWLYYWW
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
1
3
PDIP14
N SUFFIX
CASE 646
A1
14
VCC
B1
13
B4
Y1
12
A4
A2
11
Y4
B2
10
B3
Y2
A3
GND
Y3
Y3
10
A4 12
11
B4
ORDERING INFORMATION
Y4
Device
13
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
Inputs
Shipping
MC74HC132AN
PDIP14
2000 / Box
MC74HC132AD
SOIC14
55 / Rail
MC74HC132ADR2
SOIC14
2500 / Reel
Output
L
L
H
H
L
H
L
H
H
H
H
L
Package
116
MC74HC132A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
TA
tr, tf
*When Vin
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
no
limit*
ns
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
25_C
40_C to
+ 85_C
55_C to
+ 125_C
Unit
VT+ max
Maximum PositiveGoing
Input Threshold Voltage
(Figure 3)
Vout = 0.1 V
|Iout|
20 A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VT+ min
Minimum PositiveGoing
Input Threshold Voltage
(Figure 3)
Vout = 0.1 V
|Iout|
20 A
2.0
4.5
6.0
1.0
2.3
3.0
0.95
2.25
2.95
0.95
2.25
2.95
VT max
Maximum NegativeGoing
Input Threshold Voltage
(Figure 3)
2.0
4.5
6.0
0.9
2.0
2.6
0.95
2.05
2.65
0.95
2.05
2.65
VT min
Minimum NegativeGoing
Input Threshold Voltage
(Figure 3)
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
VHmax
Note 2
2.0
4.5
6.0
1.2
2.25
3.0
1.2
2.25
3.0
1.2
2.25
3.0
VHmin
Note 2
2.0
4.5
6.0
0.2
0.4
0.5
0.2
0.4
0.5
0.2
0.4
0.5
NOTE: 1. VHmin > (VT+ min) (VT max); VHmax = (VT+ max) + (VT min).
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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117
MC74HC132A
v
v
v
v
Guaranteed Limit
Symbol
VOH
55 to
25_C
2.0
4.5
6.0
Parameter
Test Conditions
VOL
VCC
V
VinVT+ max
Iin
ICC
|Iout|
|Iout|
4.0 mA
5.2 mA
85_C
125_C
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Unit
V
6.0
0.1
1.0
1.0
6.0
1.0
10
40
Guaranteed Limit
VCC
V
55 to
25_C
85_C
125_C
tPLH,
tPHL
2.0
4.5
6.0
125
25
21
155
31
26
190
38
32
ns
tTLH,
tTHL
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
10
10
10
pF
Symbol
Cin
Parameter
Unit
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
24
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
tr
tf
TEST POINT
VCC
90%
50%
10%
INPUT
A OR B
tPHL
90%
50%
10%
OUTPUT
GND
DEVICE
UNDER
TEST
tPLH
tTHL
CL*
tTLH
*Includes all probe and jig capacitance
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118
MC74HC132A
4
3
VHtyp
2
3
4
5
VCC, POWER SUPPLY VOLTAGE (VOLTS)
VHtyp = (VT + typ) (VT typ)
VCC
Vout
Vin
(a) A SCHMITT TRIGGER SQUARES UP INPUTS
(a) WITH SLOW RISE AND FALL TIMES
VCC
VH
VH
Vin
VT +
VT
Vin
VT +
VT
GND
GND
VOH
VOH
Vout
Vout
VOL
VOL
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119
MC74HC138A
1-of-8 Decoder/
Demultiplexer
HighPerformance SiliconGate CMOS
The MC74HC138A is identical in pinout to the LS138. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC138A decodes a threebit Address to oneofeight
activelow outputs. This device features three Chip Select inputs, two
activelow and one activehigh to facilitate the demultiplexing,
cascading, and chipselecting functions. The demultiplexing function
is accomplished by using the Address inputs to select the desired
device output; one of the Chip Selects is used as a data input while the
other Chip Selects are held in their active states.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 100 FETs or 29 Equivalent Gates
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MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
MC74HC138AN
AWLYYWW
1
16
SO16
D SUFFIX
CASE 751B
16
HC138A
AWLYWW
1
16
HC
138A
ALYW
TSSOP16
DT SUFFIX
CASE 948F
16
1
LOGIC DIAGRAM
A0
ADDRESS
INPUTS
A1
A2
15
Y0
14
Y1
13
Y2
12
Y3
11
Y4
10
Y5
9
Y6
7
Y7
2
3
ACTIVELOW
OUTPUTS
CS1
CHIP
SELECT
INPUTS
A
WL
YY
WW
PIN 16 = VCC
PIN 8 = GND
CS2
CS3
FUNCTION TABLE
Inputs
Outputs
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
A0
16
VCC
A1
15
Y0
A2
14
Y1
CS2
13
Y2
CS3
12
Y3
CS1
11
Y4
Y7
10
Y5
GND
Y6
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X
X
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
ORDERING INFORMATION
Device
H = high level (steady state); L = low level (steady state); X = dont care
120
Package
Shipping
MC74HC138AN
PDIP16
2000 / Box
MC74HC138AD
SOIC16
48 / Rail
MC74HC138ADR2
SOIC16
2500 / Reel
MC74HC138ADT
TSSOP16
96 / Rail
MC74HC138ADTR2
TSSOP16
2500 / Reel
MC74HC138A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 .W/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
TA
tr, tf
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55_C to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
2.4 mA
4.0 mA
5.2 mA
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121
MC74HC138A
v
v
v
v
v
v
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
Iin
ICC
2.4 mA
4.0 mA
5.2 mA
VCC
V
55_C to
25_C
2.0
4.5
6.0
85_C
125_C
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Unit
V
6.0
0.1
1.0
1.0
6.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
VCC
V
55_C to
25_C
85_C
125_C
tPLH,
tPHL
2.0
3.0
4.5
6.0
135
90
27
23
170
125
34
29
205
165
41
35
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
110
85
22
19
140
100
28
24
165
125
33
28
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
120
90
24
20
150
120
30
26
180
150
36
31
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
10
10
10
pF
Symbol
Cin
Parameter
Unit
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
55
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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122
MC74HC138A
SWITCHING WAVEFORMS
VALID
INPUT A
VCC
50%
OUTPUT Y
VCC
90%
50%
10%
INPUT CS1
GND
tPLH
tf
tr
VALID
GND
tPLH
tPHL
tPHL
50%
90%
50%
10%
OUTPUT Y
tTLH
tTHL
Figure 2.
Figure 1.
TEST POINT
tr
tf
INPUT
CS2, CS3
VCC
90%
50%
10%
GND
tPHL
OUTPUT Y
OUTPUT
DEVICE
UNDER
TEST
tPLH
CL*
90%
50%
10%
tTHL
tTLH
*Includes all probe and jig capacitance
Figure 3.
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2 (Pins 1, 2, 3)
OUTPUTS
Y0 Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)
CONTROL INPUTS
CS1, CS2, CS3 (Pins 6, 4, 5)
Chip select inputs. For CS1 at a high level and CS2, CS3
at a low level, the chip is selected and the outputs follow the
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123
MC74HC138A
EXPANDED LOGIC DIAGRAM
15
14
A0
A1
13
12
11
A2
3
10
CS3
CS2
Y1
Y2
Y3
Y4
Y5
5
4
CS1
Y0
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124
Y6
Y7
MC74HCT138A
1-of-8 Decoder/
Demultiplexer with LSTTL
Compatible Inputs
HighPerformance SiliconGate CMOS
The MC74HCT138A is identical in pinout to the LS138. The
HCT138A may be used as a level converter for interfacing TTL or
NMOS outputs to High Speed CMOS inputs.
The HCT138A decodes a threebit Address to oneofeight
activelot outputs. This device features three Chip Select inputs, two
activelow and one activehigh to facilitate the demultiplexing,
cascading, and chipselecting functions. The demultiplexing function
is accomplished by using the Address inputs to select the desired
device output; one of the Chip Selects is used as a data input while the
other Chip Selects are held in their active states.
http://onsemi.com
MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
1
MC74HCT138AN
AWLYYWW
1
16
SO16
D SUFFIX
CASE 751B
16
1
HCT138A
AWLYWW
1
16
HCT
138A
ALYW
TSSOP16
DT SUFFIX
CASE 948F
16
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC74HCT138AN
PDIP16
2000 / Box
MC74HCT138AD
SOIC16
48 / Rail
MC74HCT138ADR2
125
SOIC16
2500 / Reel
MC74HCT138ADT
TSSOP16
96 / Rail
MC74HCT138ADTR2
TSSOP16
2500 / Reel
MC74HCT138A
LOGIC DIAGRAM
A0
ADDRESS
INPUTS
A1
A2
FUNCTION TABLE
15
14
13
Inputs
CS3
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
ACTIVELOW
OUTPUTS
Y5
CS2
X
X
L
Y4
10
CS1
Y1
Y3
11
CHIP
SELECT
INPUTS
CS1CS2 CS3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
Y2
12
Y6
Y7
6
4
5
PIN 16 = VCC
PIN 8 = GND
PIN ASSIGNMENT
A0
16
VCC
A1
15
Y0
A2
14
Y1
CS2
13
Y2
CS3
12
Y3
CS1
11
Y4
Y7
10
Y5
Y6
GND
Design Criteria
Value
Units
30.5
ea.
1.5
ns
5.0
.0075
pJ
Outputs
Y0
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126
MC74HCT138A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
VCC
55
+ 125
_C
500
ns
TA
tr, tf
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
4.5
3.98
3.84
3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.4
6.0
0.1
1.0
1.0
ICC
5.5
4.0
40
160
ICC
VOH
VOL
Iin
5.5
55_C
25_C to 125_C
2.9
2.4
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
http://onsemi.com
127
MC74HCT138A
v
v
Guaranteed Limit
Symbol
55 to
25_C
Parameter
85_C
125_C
Unit
tPLH,
tPHL
30
38
45
ns
tPLH,
tPHL
27
34
41
ns
tPLH,
tPHL
30
38
45
ns
tTLH,
tTHL
15
19
22
ns
tr, tf
500
500
500
ns
Cin
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
51
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
15
14
A0
A1
13
12
11
A2
3
10
CS3
CS2
Y1
Y2
Y3
Y4
Y5
5
4
CS1
Y0
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128
Y6
Y7
MC74HCT138A
SWITCHING WAVEFORMS
VALID
tr
VALID
INPUT CS1
1.3 V
GND
tPLH
OUTPUT Y
tPHL
tPHL
90%
1.3 V
10%
tTHL
tTLH
Figure 1.
Figure 2.
tf
tr
3V
2.7 V
1.3 V
0.3 V
INPUT
CS2, CS3
GND
tPHL
tPLH
90%
1.3 V
10%
OUTPUT Y
tTHL
tTLH
Figure 3.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
Figure 4.
http://onsemi.com
129
GND
tPLH
OUTPUT Y
1.3 V
3V
2.7 V
1.3 V
0.3 V
3V
INPUT A
tf
MC74HC139A
Dual 1-of-4 Decoder/
Demultiplexer
HighPerformance SiliconGate CMOS
The MC74HC139A is identical in pinout to the LS139. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 1of4 decoders, each of
which decodes a twobit Address to oneoffour activelow outputs.
Activelow Selects are provided to facilitate the demultiplexing and
cascading functions. The demultiplexing function is accomplished by
using the Address inputs to select the desired device output, and
utilizing the Select as a data input.
ADDRESS
INPUTS
A1a
5
6
7
SELECTa
ADDRESS
INPUTS
A0b
A1b
13
11
10
9
SELECTb
Y0a
Y1a
Y2a
ACTIVELOW
OUTPUTS
Y3a
PIN 16 = VCC
PIN 8 = GND
12
MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
1
1
16
SO16
D SUFFIX
CASE 751B
16
Y0b
Y1b
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
Y2b
SELECTa
16
VCC
A0a
15
SELECTb
A1a
14
Y0a
13
A0b
A1b
Y1a
12
Y0b
Y2a
11
Y1b
Y3a
10
Y2b
GND
Y3b
ACTIVELOW
OUTPUTS
Y3b
ORDERING INFORMATION
15
FUNCTION TABLE
Outputs
Select
A1
A0
Y0
Y1 Y2
Y3
H
L
L
L
L
X
L
L
H
H
X
L
H
L
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
L
H
HC139A
AWLYWW
Device
Inputs
MC74HC139AN
AWLYYWW
PIN ASSIGNMENT
1
14
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Package
Shipping
MC74HC139AN
PDIP16
2000 / Box
MC74HC139AD
SOIC16
48 / Rail
MC74HC139ADR2
SOIC16
2500 / Reel
X = dont care
130
MC74HC139A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VIL
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
4.5
6.0
3.98
5.48
3.84
5.34
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.40
0.40
VOH
VOL
Iin
ICC
4.0 mA
5.2 mA
4.0 mA
5.2 mA
6.0
0.1
1.0
1.0
6.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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131
MC74HC139A
v
v
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tPLH,
tPHL
2.0
4.5
6.0
115
23
20
145
29
25
175
35
30
ns
tPLH,
tPHL
2.0
4.5
6.0
115
23
20
145
29
25
175
35
30
ns
tTLH,
tTHL
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
55
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
tf
tr
OUTPUT Y
VALID
VCC
90%
50%
SELECT 10%
VCC
INPUT A
GND
tPHL
90%
50%
10%
tTHL
VALID
50%
GND
tPLH
tPHL
tPLH
OUTPUT Y
50%
tTLH
Figure 1.
Figure 2.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
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132
MC74HC139A
PIN DESCRIPTIONS
ADDRESS INPUTS
A0a, A1a, A0b, A1b (Pins 2, 3, 14, 13)
OUTPUTS
Y0a Y3a, Y0b Y3b (Pins 4 7, 12, 11, 10, 9)
CONTROL INPUTS
Selecta, Selectb (Pins 1, 15)
SELECT
Y0
Y1
A0
Y2
Y3
A1
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133
MC74HC157A
Quad 2-Input Data
Selectors / Multiplexers
HighPerformance SiliconGate CMOS
The MC74HC157A is identical in pinout to the LS157. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device routes 2 nibbles (A or B) to a single port (Y) as
determined by the Select input. The data is presented at the outputs in
noninverted form. A high level on the Output Enable input sets all four
Y outputs to a low level.
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MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
1
1
16
SO16
D SUFFIX
CASE 751B
16
1
16
1
A
WL
YY
WW
A1
11
A2
14
A3
7
9
B0
NIBBLE
B INPUTS
12
B1
Y0
Y1
Y2
DATA
OUTPUTS
Y3
10
B2
13
B3
SELECT
OUTPUT
ENABLE
PIN 16 = VCC
PIN 8 = GND
1
15
FUNCTION TABLE
Inputs
Output
Enable
Select
Outputs
Y0 Y3
H
L
L
X
L
H
L
A0 A3
B0 B3
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
SELECT
16
A0
15
B0
14
VCC
OUTPUT
ENABLE
A3
Y0
13
B3
A1
12
Y3
B1
11
A2
Y1
10
B2
GND
Y2
ORDERING INFORMATION
Device
X = dont care
A0 A3, B0 B3 = the levels of the
respective DataWord Inputs.
HC
157A
ALYW
TSSOP16
DT SUFFIX
CASE 948F
A0
NIBBLE
A INPUTS
HC157A
AWLYWW
16
LOGIC DIAGRAM
MC74HC157AN
AWLYYWW
134
Package
Shipping
MC74HC157AN
PDIP16
2000 / Box
MC74HC157AD
SOIC16
48 / Rail
MC74HC157ADR2
SOIC16
2500 / Reel
MC74HC157ADT
TSSOP16
96 / Rail
MC74HC157ADTR2
TSSOP16
2500 / Reel
MC74HC157A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
Vout = 0.1 V
|Iout|
20 A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
Vin = VIH
|Iout|
20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH
Vin = VIH
VOL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
Vin = VIL
|Iout|
20 A
Vin = VIL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
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135
MC74HC157A
v
v
v
v
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
6.0
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
6.0
0.5
5.0
10
ICC
6.0
4.0
40
160
Iin
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
105
65
21
18
130
85
26
22
160
115
32
27
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
110
70
22
19
140
90
28
24
165
115
33
28
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
100
60
20
17
125
80
25
21
150
110
30
26
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
33
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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136
MC74HC157A
PIN DESCRIPTIONS
INPUTS
A0, A1, A2, A3 (Pins 2, 5, 11, 14)
CONTROL INPUTS
Select (Pin 1)
OUTPUTS
Y0, Y1, Y2, Y3 (Pins 4, 7, 9, 12)
tr
tf
90%
50%
10%
INPUT A OR B
GND
90%
50%
10%
OUTPUT Y
tTLH
tTLH
tTHL
Figure 1. HC157A
GND
tPHL
tPLH
tPHL
90%
50%
10%
VCC
90%
50%
10%
SELECT
tPLH
OUTPUT Y
tf
VCC
tTHL
tf
VCC
90%
50%
10%
OUTPUT
ENABLE
GND
tPHL
tPLH
90%
50%
10%
OUTPUT Y
tTHL
tTLH
Figure 3. HC157A
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
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137
MC74HC157A
EXPANDED LOGIC DIAGRAM
2
A0
B0
A1
B1
NIBBLE
OUTPUTS
5
7
Y1
11
A3
B3
SELECT
Y0
DATA
OUTPUTS
A2
B2
OUTPUT ENABLE
10
Y2
14
12 Y3
13
15
1
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138
MC74HC161A,
MC74HC163A
Presettable Counters
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MARKING
DIAGRAMS
16
16
1
Device
Count
Mode
Reset Mode
HC161A
Binary
Asynchronous
HC163A
Binary
Synchronous
PRESET
DATA
INPUTS
P1
P2
P3
CLOCK
A
WL
YY
WW
COUNT
ENABLES
13
12
Shipping
PDIP16
2000 / Box
MC74HC16xAD
SOIC16
48 / Rail
MC74HC16xADR2
SOIC16
2500 / Reel
Q0
Q1
PIN ASSIGNMENT
BCD OR
BINARY
OUTPUT
16
CLOCK
15
P0
14
VCC
RIPPLE
CARRY OUT
Q0
P1
13
Q1
P2
12
Q2
P3
11
Q3
ENABLE P
10
ENABLE T
GND
11
ENABLE T
Package
MC74HC16xAN
RESET
ENABLE P
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
Device
14
LOAD
HC16xA
AWLYWW
ORDERING INFORMATION
RESET
SO16
D SUFFIX
CASE 751B
1
LOGIC DIAGRAM
P0
MC74HC16xAN
AWLYYWW
1
16
16
PDIP16
N SUFFIX
CASE 648
15
Q2
Q3
RIPPLE
CARRY
OUT
PIN 16 = VCC
PIN 8 = GND
LOAD
FUNCTION TABLE
Inputs
10
Clock
Output
Reset*
Load
Enable P
Enable T
L
H
H
H
H
X
L
H
H
H
X
X
H
L
X
X
X
H
X
L
Reset
Load Preset Data
Count
No Count
No Count
139
MC74HC161A, MC74HC163A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
TA
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
0
1000
600
500
400
ns
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140
MC74HC161A, MC74HC163A
v
v
v
v
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH
VOL
Iin
ICC
3.6 mA
4.0 mA
5.2 mA
3.6 mA
4.0 mA
5.2 mA
6.0
0.1
1.0
1.0
6.0
4.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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141
MC74HC161A, MC74HC163A
v
v
Guaranteed Limit
Symbol
Parameter
Fig.
VCC
V
55 to
25_C
85_C
125_C
Unit
fmax
1, 7
2.0
3.0
4.5
6.0
6
15
30
35
5
12
24
28
4
10
20
24
MHz
tPLH
1, 7
2.0
3.0
4.5
6.0
120
75
20
16
160
120
23
20
200
150
28
22
ns
1, 7
2.0
3.0
4.5
6.0
145
100
22
18
185
135
25
20
220
150
30
23
ns
tPHL
tPHL
2, 7
2.0
3.0
4.5
6.0
145
100
20
17
185
135
22
19
220
150
25
21
ns
tPLH
3, 7
2.0
3.0
4.5
6.0
110
60
16
14
150
115
18
15
190
140
20
17
ns
3, 7
2.0
3.0
4.5
6.0
135
100
18
15
175
130
20
16
210
160
22
20
ns
1, 7
2.0
3.0
4.5
6.0
120
75
22
18
160
135
27
22
200
150
30
25
ns
1, 7
2.0
3.0
4.5
6.0
145
100
22
20
185
135
28
24
220
150
35
28
ns
tPHL
tPLH
tPHL
tPHL
2, 7
2.0
3.0
4.5
6.0
155
120
22
18
190
140
26
22
230
155
30
25
ns
tTLH,
tTHL
2, 7
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
1, 7
10
10
10
pF
Cin
*Applies to noncascaded/nonsynchronous clocked configurations only with synchronously cascaded counters. (1) Clock to Ripple Carry Out
propagation delays. (2) Enable T or Enable P to Clock setup times and (3) Clock to Enable T or Enable P hold times determine fmax. However,
if Ripple Carry out of each stage is tied to the Clock of the next stage (nonsynchronously clocked) the fmax in the table above is applicable.
See Applications information in this data sheet.
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
45
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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142
MC74HC161A, MC74HC163A
v
v
Guaranteed Limit
Symbol
Parameter
Fig.
VCC
V
55 to
25_C
85_C
125_C
Unit
tsu
2.0
3.0
4.5
6.0
40
20
15
12
60
30
20
18
80
40
30
20
ns
tsu
2.0
3.0
4.5
6.0
60
25
15
12
75
30
20
18
90
40
30
20
ns
tsu
2.0
3.0
4.5
6.0
60
25
20
17
75
30
25
23
90
40
35
25
ns
tsu
2.0
3.0
4.5
6.0
80
35
20
17
95
40
25
23
110
50
35
25
ns
th
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
th
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
th
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
trec
2.0
3.0
4.5
6.0
80
35
15
12
95
40
20
17
110
50
26
23
ns
trec
2.0
3.0
4.5
6.0
80
35
15
12
95
40
20
17
110
50
26
23
ns
tw
2.0
3.0
4.5
6.0
60
25
12
10
75
30
15
13
90
40
18
15
ns
tw
2.0
3.0
4.5
6.0
60
25
12
10
75
30
15
13
90
40
18
15
ns
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
tr, tf
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143
MC74HC161A, MC74HC163A
FUNCTION DESCRIPTION
The HC161A/163A are programmable 4bit synchronous
counters that feature parallel Load, synchronous or
asynchronous Reset, a Carry Output for cascading and
countenable controls.
The HC161A and HC163A are binary counters with
asynchronous Reset and synchronous Reset, respectively.
With the rising edge of the Clock, a low level on Load (Pin
9) loads the data from the Preset Data input pins (P0, P1, P2,
P3) into the internal flipflops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load
is low.
INPUTS
Clock (Pin 2)
Count Enable/Disable
OUTPUTS
Control Inputs
Result at Outputs
Load
Enable P
Enable T
Q0 Q3
Count
No
Count
No
Count
No
Count
CONTROL FUNCTIONS
Resetting
15
14
13
12
11
10
Binary Counters
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144
MC74HC161A, MC74HC163A
SWITCHING WAVEFORMS
tr
90%
50%
10%
CLOCK
tf
tw
VCC
VCC
RESET
GND
GND
tPHL
tw
1/fmax
tPLH
tPHL
50%
ANY
OUTPUT
90%
50%
10%
ANY
OUTPUT
50%
trec
VCC
tTLH
50%
CLOCK
tTHL
GND
Figure 1.
tr
Figure 2.
tf
VCC
90%
50%
10%
ENABLE T
GND
tPLH
th
tsu
tPHL
90%
50%
10%
RIPPLE
CARRY
OUT
50%
RESET
VCC
50%
CLOCK
tTLH
GND
tTHL
Figure 3.
VALID
INPUTS
P0, P1,
P2, P3
VCC
50%
GND
tsu
th
VALID
VCC
LOAD
ENABLE T
OR
ENABLE P
50%
GND
tsu
CLOCK
th
VCC
50%
GND
tsu
trec
th
VCC
VCC
CLOCK
50%
50%
GND
GND
Figure 5.
Figure 6.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
Figure 7.
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145
P0
T0
R
C
C
LOAD
LOAD
P0
P1 4
P2
P3
ENABLE P
ENABLE T
RESET
LOAD
CLOCK
T2
R
C
C
LOAD
LOAD
P2
T3
R
C
C
LOAD
LOAD
P3
Q0
13
Q1
12
Q2
Q2
11
Q3
Q3
15 RIPPLE
CARRY
OUT
R
LOAD
LOAD
Q2
VCC = PIN 16
GND = PIN 8
10
Q1
Q1
Q0
C
C
The flipflops shown in the circuit diagrams are ToggleEnable flipflops. A Toggle
Enable flipflop is a combination of a D flipflop and a T flipflop. When loading data from
Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flipflop. The logic level at the Pn input is then clocked to the Q output of the flipflop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
output of the flipflop low.
MC74HC161A, MC74HC163A
146
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T1
R
C
C
LOAD
LOAD
P1
14
Q0
MC74HC161A, MC74HC163A
Sequence illustrated in waveforms:
1. Reset outputs to zero.
2. Preset to binary twelve.
3. Count to thirteen, fourteen, fifteen, zero, one and two.
4. Inhibit.
RESET (HC161A)
(ASYNCHRONOUS)
RESET (HC163A)
(SYNCHRONOUS)
LOAD
P0
PRESET
DATA
INPUTS
P1
P2
P3
CLOCK (HC161A)
CLOCK (HC163A)
COUNT
ENABLES
ENABLE P
ENABLE T
Q0
Q1
OUTPUTS
Q2
Q3
RIPPLE
CARRY
OUT
12
13 14
15
COUNT
RESET
LOAD
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147
2
INHIBIT
P0
P2
P3
ENABLE P
ENABLE T
RESET
LOAD
T1
R
C
C
LOAD
LOAD
P1
T2
R
C
C
LOAD
LOAD
P2
T3
R
C
C
LOAD
LOAD
P3
13
Q1
9
2
Q1
Q1
12
Q2
Q2
Q2
11
Q3
Q3
15 RIPPLE
CARRY
OUT
VCC = PIN 16
GND = PIN 8
10
1
Q0
Q0
R
LOAD
LOAD
CLOCK
14
Q0
C
C
The flipflops shown in the circuit diagrams are ToggleEnable flipflops. A Toggle
Enable flipflop is a combination of a D flipflop and a T flipflop. When loading data from
Preset inputs P0, P1, P2, and P3, the Load signal is used to disable the Toggle input (Tn) of
the flipflop. The logic level at the Pn input is then clocked to the Q output of the flipflop
on the next rising edge of the clock.
A logic zero on the Reset device input forces the internal clock (C) high and resets the Q
output of the flipflop low.
MC74HC161A, MC74HC163A
148
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P1
T0
R
C
C
LOAD
LOAD
P0
MC74HC161A, MC74HC163A
TYPICAL APPLICATIONS CASCADING
LOAD
INPUTS
LOAD
H = COUNT
L = DISABLE
H = COUNT
L = DISABLE
P0 P1 P2 P3
RIPPLE
CARRY
OUT
ENABLE T
CLOCK
Q0 Q1 Q2 Q3
LOAD
P0 P1 P2 P3
ENABLE P
ENABLE P
INPUTS
INPUTS
LOAD
P0 P1 P2 P3
ENABLE P
RIPPLE
CARRY
OUT
ENABLE T
CLOCK
CLOCK
Q0 Q1 Q2 Q3
RIPPLE
CARRY
OUT
ENABLE T
TO
MORE
SIGNIFICANT
STAGES
Q0 Q1 Q2 Q3
RESET
OUTPUTS
OUTPUTS
OUTPUTS
CLOCK
NOTE: When used in these cascaded configurations the clock fmax guaranteed limits may not apply. Actual performance will depend on
number of stages. This limitation is due to set up times between Enable (Port) and Clock.
INPUTS
INPUTS
INPUTS
LOAD
ENABLE P
ENABLE T
LOAD
P0 P1 P2 P3
ENABLE P
ENABLE T
CLOCK
LOAD
P0 P1 P2 P3
ENABLE P
RIPPLE
CARRY
OUT
LOAD
P0 P1 P2 P3
ENABLE P
RIPPLE
CARRY
OUT
ENABLE T
ENABLE T
CLOCK
CLOCK
CLOCK
Q0 Q1 Q2 Q3
Q0 Q1 Q2 Q3
RIPPLE
CARRY
OUT
Q0 Q1 Q2 Q3
RESET
OUTPUTS
OUTPUTS
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149
OUTPUTS
TO
MORE
SIGNIFICANT
STAGES
MC74HC161A, MC74HC163A
TYPICAL APPLICATIONS VARYING THE MODULUS
HC163A
OTHER
INPUTS
HC163A
Q0
Q1
OTHER
INPUTS
OPTIONAL BUFFER
FOR NOISE REJECTION
Q2
Q0
Q1
OUTPUT
OPTIONAL BUFFER
FOR NOISE REJECTION
Q2
Q3
OUTPUT
Q3
RESET
RESET
The HC163A facilitates designing counters of any modulus with minimal external logic. The output is glitchfree due to
the synchronous Reset.
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150
MC74HC164A
8-Bit Serial-Input/
Parallel-Output Shift
Register
HighPerformance SiliconGate CMOS
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A1
A2
DATA
5
6
10
CLOCK
RESET
QA
14
PDIP14
N SUFFIX
CASE 646
QD
MC74HC164AN
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
HC164A
AWLYWW
1
14
HC
164A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
PIN ASSIGNMENT
QB
QC
QE
11
QF
12
QG
13
QH
MARKING
DIAGRAMS
PARALLEL
DATA
OUTPUTS
PIN 14 = VCC
PIN 7 = GND
A1
14
VCC
A2
13
QH
QA
12
QG
QB
11
QF
QC
10
QE
QD
RESET
GND
CLOCK
FUNCTION TABLE
Inputs
Reset Clock A1 A2 QA QB
L
H
H
H
ORDERING INFORMATION
Outputs
X
X
H
D
X
X
D
H
QH
Device
L L
No Change
D QAn QGn
D QAn QGn
L
Shipping
MC74HC164AN
PDIP14
2000 / Box
MC74HC164AD
SOIC14
55 / Rail
MC74HC164ADR2
D = data input
QAn QGn = data shifted from the preceding
stage on a rising edge at the clock input.
Package
151
SOIC14
2500 / Reel
MC74HC164ADT
TSSOP14
96 / Rail
MC74HC164ADTR2
TSSOP14
2500 / Reel
MC74HC164A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55_C to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
2.4 mA
4.0 mA
5.2 mA
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152
MC74HC164A
v
v
v
v
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
Iin
ICC
2.4 mA
4.0 mA
5.2 mA
VCC
V
55_C to
25_C
2.0
4.5
6.0
85_C
125_C
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Unit
V
6.0
0.1
1.0
1.0
6.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
VCC
V
55_C to
25_C
85_C
125_C
Unit
fmax
2.0
3.0
4.5
6.0
10
20
40
50
10
20
35
45
10
20
30
40
MHz
tPLH,
tPHL
2.0
3.0
4.5
6.0
160
100
32
27
200
150
40
34
250
200
48
42
ns
tPHL
2.0
3.0
4.5
6.0
175
100
35
30
220
150
44
37
260
200
53
45
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Symbol
Cin
Parameter
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
180
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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153
MC74HC164A
v
v
Guaranteed Limit
Symbol
Parameter
VCC
V
55_C to
25_C
85_C
125_C
Unit
tsu
2.0
3.0
4.5
6.0
25
15
7
5
35
20
8
6
40
25
9
6
ns
th
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
2.0
3.0
4.5
6.0
3
3
3
3
3
3
3
3
3
3
3
3
ns
tw
2.0
3.0
4.5
6.0
50
26
12
10
60
35
15
12
75
45
20
15
ns
tw
2.0
3.0
4.5
6.0
50
26
12
10
60
35
15
12
75
45
20
15
ns
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
trec
tr, tf
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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154
MC74HC164A
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 1, 2)
OUTPUTS
Clock (Pin 8)
Reset (Pin 9)
SWITCHING WAVEFORMS
tr
tw
tf
VCC
90%
50%
10%
CLOCK
50%
GND
GND
tPHL
tw
1/fmax
tPLH
Q
VCC
RESET
50%
tPHL
90%
50%
10%
trec
VCC
CLOCK
tTLH
50%
GND
tTHL
Figure 2.
Figure 1.
TEST POINT
OUTPUT
VALID
VCC
A1 OR A2
DEVICE
UNDER
TEST
50%
GND
tsu
CL*
th
VCC
CLOCK
50%
GND
*Includes all probe and jig capacitance
Figure 3.
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155
MC74HC164A
EXPANDED LOGIC DIAGRAM
CLOCK
A1
1
2
A2
R
R
RESET
3
QA
5
QB
6
QC
QD
TIMING DIAGRAM
CLOCK
A1
A2
RESET
QA
QB
QC
QD
QE
QF
QG
QH
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156
10
QE
11
QF
12
QG
13
QH
MC74HC165A
8-Bit Serial or
Parallel-Input/
Serial-Output Shift Register
HighPerformance SiliconGate CMOS
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
MC74HC165AN
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
HC165A
AWLYWW
1
14
TSSOP14
DT SUFFIX
CASE 948G
HC
165A
ALYW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC74HC165AN
PDIP14
2000 / Box
MC74HC165AD
SOIC14
55 / Rail
MC74HC165ADR2
157
SOIC14
2500 / Reel
MC74HC165ADT
TSSOP14
96 / Rail
MC74HC165ADTR2
TSSOP14
2500 / Reel
MC74HC165A
LOGIC DIAGRAM
A
B
PARALLEL
DATA
INPUTS
PIN ASSIGNMENT
11
12
13
D 14
E 3
QH
QH
SERIAL SHIFT/
PARALLEL LOAD
CLOCK
16
VCC
15
CLOCK INHIBIT
14
SERIAL
DATA
OUTPUTS
13
12
11
QH
10
SA
GND
QH
F 4
G 5
H 6
SERIAL
SA 10
DATA
INPUT
SERIAL SHIFT/ 1
PARALLEL LOAD
CLOCK 2
CLOCK INHIBIT
PIN 16 = VCC
PIN 8 = GND
15
FUNCTION TABLE
Serial Shift/
Parallel Load
Inputs
Clock
Inhibit
Clock
L
H
H
H
H
L
L
H
H
X
H
H
X
X = dont care
X
L
L
Internal Stages
Output
SA
X
L
H
AH
QA
QB
QH
ah
X
X
a
L
H
L
H
X
X
L
H
b
QAn
QAn
QAn
QAn
X
X
X
X
No Change
Inhibited Clock
No Change
No Clock
QGn
QGn
QGn
QGn
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158
Operation
Asynchronous Parallel Load
MC74HC165A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
600
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
2.4 mA
4.0 mA
5.2 mA
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159
MC74HC165A
v
v
v
v
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
Iin
ICC
2.4 mA
4.0 mA
5.2 mA
VCC
V
55 to
25_C
2.0
4.5
6.0
85_C
125_C
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Unit
V
6.0
0.1
1.0
1.0
6.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
fmax
2.0
3.0
4.5
6.0
6
18
30
35
4.8
17
24
28
4
15
20
24
MHz
tPLH,
tPHL
2.0
3.0
4.5
6.0
150
52
30
26
190
63
38
33
225
65
45
38
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
175
58
35
30
220
70
44
37
265
72
53
45
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
150
52
30
26
190
63
38
33
225
65
45
38
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
40
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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160
MC74HC165A
v
v
Guaranteed Limit
VCC
V
55 to
25_C
2.0
3.0
4.5
6.0
tsu
tsu
85_C
125_C
75
30
15
13
95
40
19
16
110
55
22
19
ns
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tsu
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
th
2.0
3.0
4.5
6.0
5
5
5
5
5
5
5
5
5
5
5
5
ns
th
2.0
3.0
4.5
6.0
5
5
5
5
5
5
5
5
5
5
5
5
ns
th
2.0
3.0
4.5
6.0
5
5
5
5
5
5
5
5
5
5
5
5
ns
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tw
2.0
3.0
4.5
6.0
70
27
15
13
90
32
19
16
100
36
22
19
ns
tw
2.0
3.0
4.5
6.0
70
27
15
13
90
32
19
16
100
36
22
19
ns
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
Symbol
Parameter
tsu
trec
tr, tf
Unit
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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161
MC74HC165A
PIN DESCRIPTIONS
INPUTS
SA (Pin 10)
OUTPUTS
CONTROL INPUTS
QH, QH (Pins 9, 7)
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162
MC74HC165A
SWITCHING WAVEFORMS
tr
CLOCK
OR CLOCK INHIBIT
tf
VCC
90%
50%
10%
tw
GND
SERIAL SHIFT/
PARALLEL LOAD
tw
1/fmax
tPLH
GND
tPHL
QH OR QH
tTLH
tPHL
tPLH
90%
50%
10%
QH OR QH
VCC
50%
50%
50%
tTHL
VALID
tr
VCC
tf
VCC
90%
50%
10%
INPUT H
INPUTS AH
50%
GND
GND
tPLH
tsu
tPHL
90%
50%
10%
QH OR QH
th
VCC
SERIAL SHIFT/
PARALLEL LOAD
tTLH
GND
tTHL
ASYNCHRONOUS PARALLEL
LOAD
(LEVEL SENSITIVE)
VALID
SERIAL SHIFT/
PARALLEL LOAD
VCC
INPUT SA
50%
VCC
50%
GND
tsu
GND
tsu
th
VCC
CLOCK
OR CLOCK INHIBIT
VCC
CLOCK
OR CLOCK INHIBIT
50%
th
50%
GND
GND
TEST POINT
CLOCK 2 INHIBITED
CLOCK INHIBIT
OUTPUT
VCC
DEVICE
UNDER
TEST
50%
GND
tsu
CLOCK
CL*
trec
VCC
50%
GND
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163
MC74HC165A
EXPANDED LOGIC DIAGRAM
A
B
11
C
12
F
13
G
4
H
5
SERIAL SHIFT/
1
PARALLEL LOAD
9 Q
H
SERIAL DATA 10
INPUT SA
D QA
D QB
D QC
D QF
D QG
D QH
C C
C C
C C
C C
C C
C C
CLOCK 2
CLOCK 15
INHIBIT
TIMING DIAGRAM
CLOCK
CLOCK INHIBIT
SA
SERIAL SHIFT/
PARALLEL LOAD
A
PARALLEL
DATA
INPUTS
QH
QH
H H
L L
CLOCK
INHIBIT
MODE
SERIALSHIFT MODE
PARALLEL LOAD
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164
7 Q
H
MC74HC174A
Hex D Flip-Flop with
Common Clock and Reset
HighPerformance SiliconGate CMOS
The MC74HC174A is identical in pinout to the LS174. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of six D flipflops with common Clock and
Reset inputs. Each flipflop is loaded with a lowtohigh transition of
the Clock input. Reset is asynchronous and activelow.
2 Q0
5
Q1
7 Q2
D2 6
D3 11
10 Q3
12 Q4
D4 13
14
D5
15
NONINVERTING
OUTPUTS
Q5
CLOCK 9
PIN 16 = VCC
PIN 8 = GND
RESET 1
FUNCTION TABLE
Inputs
Output
Reset
Clock
L
H
H
H
H
X
H
L
X
X
L
H
L
No Change
No Change
Design Criteria
Value
Units
40.5
ea.
1.5
ns
5.0
.0075
pJ
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MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
MC74HC174AN
AWLYYWW
1
16
SO16
D SUFFIX
CASE 751B
16
HC174A
AWLYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
RESET
16
VCC
Q0
15
Q5
D0
14
D5
D1
13
D4
Q1
12
Q4
D2
11
D3
Q2
10
Q3
GND
CLOCK
ORDERING INFORMATION
Package
Shipping
MC74HC174AN
Device
PDIP16
2000 / Box
MC74HC174AD
SOIC16
48 / Rail
MC74HC174ADR2
SOIC16
2500 / Reel
165
MC74HC174A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VIL
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VOH
VOL
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166
MC74HC174A
v
v
Guaranteed Limit
Symbol
Parameter
Iin
ICC
VCC
V
55 to
25_C
6.0
0.1
1.0
1.0
6.0
4.0
40
160
Test Conditions
85_C
125_C
Unit
NOTES:
1. Information on typical parametric values along with high frequency or heavy load considerations, can be found in Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + SICC.
v
v
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
fmax
2.0
4.5
6.0
6.0
30
35
4.8
24
28
4.0
20
24
MHz
tPLH
tPHL
2.0
4.5
6.0
110
22
19
140
28
24
165
33
28
ns
tPLH
tPHL
2.0
4.5
6.0
110
21
19
140
28
24
160
32
27
ns
tTLH
tTHL
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
62
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Guaranteed Limit
Symbol
Parameter
Fig.
VCC
V
55 to 25_C
Min
Max
85_C
Min
Max
125_C
Min
Max
Unit
tsu
2.0
4.5
6.0
50
10
9.0
65
13
11
75
15
13
ns
th
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
2.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
tw
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
tw
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
2.0
4.5
6.0
trec
tr, tf
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167
1000
500
400
1000
500
400
1000
500
400
ns
MC74HC174A
EXPANDED LOGIC DIAGRAM
CLOCK
D0
RESET
D1
D2
C
D
5 Q1
C
D
R
C
10
12
15 Q5
Q4
R
C
D5 14
Q3
R
C
D4
Q2
13
D3 11
Q0
SWITCHING WAVEFORMS
CLOCK
tr
90%
50%
10%
tw
tf
VCC
VCC
50%
GND
GND
tPHL
1/fmax
tPLH
Q
tw
RESET
tPHL
90%
50%
10%
trec
VCC
50%
tTLH
CLOCK
tTHL
Figure 1.
GND
Figure 2.
TEST POINT
VALID
OUTPUT
VCC
DATA
DEVICE
UNDER
TEST
50%
GND
tsu
CL*
th
VCC
CLOCK
50%
Figure 3.
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168
MC74HC175A
Quad D Flip-Flop with
Common Clock and Reset
HighPerformance SiliconGate CMOS
The MC74HC175A is identical in pinout to the LS175. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of four D flipflops with common Reset and
Clock inputs, and separate D inputs. Reset (activelow) is
asynchronous and occurs when a low level is applied to the Reset
input. Information at a D input is transferred to the corresponding Q
output on the next positive going edge of the Clock input.
D0
D1
DATA
INPUTS
2
3
7
6
10
11
15
14
D2 12
D3 13
RESET
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
INVERTING
AND
NONINVERTING
OUTPUTS
PIN 16 = VCC
PIN 8 = GND
FUNCTION TABLE
Outputs
Reset
Clock
L
H
H
H
X
H
L
X
16
PDIP16
N SUFFIX
CASE 648
16
1
1
16
SO16
D SUFFIX
CASE 751B
16
HC175A
AWLYWW
1
16
HC
175A
ALYW
TSSOP16
DT SUFFIX
CASE 948F
16
L
H
H
L
L
H
No Change
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
RESET
16
VCC
Q0
15
Q3
Q0
14
Q3
D0
13
D3
D1
12
D2
Q1
11
Q2
Q1
10
Q2
GND
CLOCK
ORDERING INFORMATION
Device
MC74HC175AN
AWLYYWW
Inputs
MARKING
DIAGRAMS
LOGIC DIAGRAM
CLOCK
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169
Package
Shipping
MC74HC175AN
PDIP16
2000 / Box
MC74HC175AD
SOIC16
48 / Rail
MC74HC175ADR2
SOIC16
2500 / Reel
MC74HC175ADT
TSSOP16
96 / Rail
MC74HC175ADTR2
TSSOP16
2500 / Reel
MC74HC175A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
600
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
42
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
2.4 mA
4.0 mA
5.2 mA
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170
MC74HC175A
v
v
v
v
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
Iin
ICC
2.4 mA
4.0 mA
5.2 mA
VCC
V
55 to
25_C
2.0
4.5
6.0
85_C
125_C
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Unit
V
6.0
0.1
1.0
1.0
6.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
fmax
2.0
3.0
4.5
6.0
6
10
30
35
4.8
8.0
24
28
4
6
20
24
MHz
tPLH,
tPHL
2.0
3.0
4.5
6.0
150
75
26
22
190
90
32
28
225
110
38
33
ns
tPHL
2.0
3.0
4.5
6.0
125
70
22
19
155
85
27
24
190
110
34
30
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
35
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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171
MC74HC175A
v
v
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tsu
2.0
3.0
4.5
6.0
100
45
20
17
125
65
25
21
150
85
30
26
ns
th
2.0
3.0
4.5
6.0
5
3
3
3
5
3
3
3
5
3
3
3
ns
2.0
3.0
4.5
6.0
100
45
20
17
125
65
25
21
150
85
30
26
ns
tw
2.0
3.0
4.5
6.0
80
45
16
14
100
65
20
17
120
85
24
20
ns
tw
2.0
3.0
4.5
6.0
80
45
16
14
100
65
20
17
120
85
24
20
ns
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
trec
tr, tf
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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172
MC74HC175A
SWITCHING WAVEFORMS
tw
RESET
tf
CLOCK
tPHL
VCC
90%
50%
10%
tPLH
50%
GND
tPLH
1/fmax
Q or Q
GND
tr
90%
50%
10%
tw
VCC
50%
50%
tPHL
trec
VCC
CLOCK
tTLH
50%
tTHL
GND
Figure 1.
Figure 2.
VALID
VCC
DATA
GND
tsu
th
VCC
CLOCK
50%
GND
Figure 3.
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
Figure 4.
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173
MC74HC175A
EXPANDED LOGIC DIAGRAM
D0
Q0
Q0
Q1
Q1
10
Q2
11
Q2
15
Q3
14
Q3
C
CLOCK
D1
Q
C
C
D2
12
Q
C
C
D3
13
Q
C
C
RESET
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174
MC74HC240A
Octal 3-State Inverting
Buffer/Line Driver/Line
Receiver
HighPerformance SiliconGate CMOS
The MC74HC240A is identical in pinout to the LS240. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed
to be used with 3state memory address drivers, clock drivers, and
other suboriented systems. The device has inverting outputs and two
activelow output enables.
The HC240A is similar in function to the HC244A.
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
MC74HC240AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HC240A
AWLYYWW
1
20
HC
240A
ALYW
TSSOP20
DT SUFFIX
CASE 948G
20
1
LOGIC DIAGRAM
A1
A2
A3
A4
DATA
INPUTS
B1
B2
B3
B4
OUTPUT
ENABLES
18
16
14
12
11
13
15
17
YA1
A
WL
YY
WW
YA2
YA3
PIN ASSIGNMENT
YA4
YB1
INVERTING
OUTPUTS
YB2
YB3
YB4
PIN 20 = VCC
PIN 10 = GND
1
ENABLE A
19
ENABLE B
FUNCTION TABLE
Inputs
A, B
YA, YB
L
L
H
L
H
X
H
L
Z
20
VCC
A1
19
ENABLE B
YB4
18
YA1
A2
17
B4
YB3
16
YA2
A3
15
B3
YB2
14
YA3
A4
13
B2
YB1
12
YA4
GND
10
11
B1
Device
MC74HC240AN
Z = high impedance
ENABLE A
ORDERING INFORMATION
Outputs
Enable A,
Enable B
= Assembly Location
= Wafer Lot
= Year
= Work Week
175
Package
Shipping
PDIP20
1440 / Box
MC74HC240ADW
SOICWIDE
38 / Rail
MC74HC240ADWR2
SOICWIDE
1000 / Reel
MC74HC240ADT
TSSOP20
75 / Rail
MC74HC240ADTR2
TSSOP20
2500 / Reel
MC74HC240A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
Vout = 0.1 V
|Iout|
20 A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
Vin = VIH
|Iout|
20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH
Vin = VIH
VOL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
Vin = VIL
|Iout|
20 A
Vin = VIL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
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176
MC74HC240A
v
v
v
v
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
6.0
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
6.0
0.5
5.0
10
ICC
6.0
4.0
40
160
Iin
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
80
40
16
14
100
50
20
17
120
60
24
20
ns
tPLZ,
tPHZ
2.0
3.0
4.5
6.0
110
60
22
19
140
70
28
24
165
80
33
28
ns
tPZL,
tPZH
2.0
3.0
4.5
6.0
110
60
22
19
140
70
28
24
165
80
33
28
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
10
10
10
pF
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
32
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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177
MC74HC240A
SWITCHING WAVEFORMS
VCC
DATA INPUT
A OR B
ENABLE
tf
tr
GND
VCC
90%
50%
10%
tPZL
tPLZ
HIGH
IMPEDANCE
GND
tPHL
tPLH
OUTPUT Y
90%
50%
10%
OUTPUT
YA OR YB
50%
50%
tPZH
OUTPUT Y
tTHL
tPHZ
10%
VOL
90%
VOH
50%
HIGH
IMPEDANCE
tTLH
Figure 1.
Figure 2.
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
1 k
CL*
PIN DESCRIPTIONS
INPUTS
OUTPUTS
CONTROLS
Enable A, Enable B (Pins 1, 19)
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178
MC74HC240A
LOGIC DETAIL
TO THREE OTHER
A OR B INVERTERS
ONE OF 8
INVERTERS
VCC
DATA
INPUT
A OR B
YA
OR
YB
ENABLE A
OR ENABLE B
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179
MC74HC244A
Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver
HighPerformance SiliconGate CMOS
The MC74HC244A is identical in pinout to the LS244. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed
to be used with 3state memory address drivers, clock drivers, and
other busoriented systems. The device has noninverting outputs and
two activelow output enables.
The HC244A is similar in function to the HC240A.
http://onsemi.com
MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
MC74HC244AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HC244A
AWLYYWW
1
HC
244A
ALYW
TSSOP20
DT SUFFIX
CASE 948G
20
1
LOGIC DIAGRAM
A1
A2
A3
A4
DATA
INPUTS
B1
B2
B3
B4
OUTPUT
ENABLES
18
16
14
12
11
13
15
17
A
WL
YY
WW
YA1
YA2
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
YA3
ENABLE A
20
VCC
YA4
YB1
NONINVERTING
OUTPUTS
YB2
YB3
YB4
A1
19
ENABLE B
YB4
18
YA1
A2
17
B4
YB3
16
YA2
A3
15
B3
YB2
14
YA3
A4
13
B2
YB1
12
YA4
GND
10
11
B1
PIN 20 = VCC
PIN 10 = GND
1
ENABLE A
19
ENABLE B
ORDERING INFORMATION
FUNCTION TABLE
Inputs
Enable A,
Enable B
Device
Outputs
MC74HC244AN
A, B
L
L
L
H
H
X
Z = high impedance
Semiconductor Components Industries, LLC, 1999
20
YA, YB
L
H
Z
180
Package
Shipping
PDIP20
1440 / Box
MC74HC244ADW
SOICWIDE
38 / Rail
MC74HC244ADWR2
SOICWIDE
1000 / Reel
MC74HC244ADT
TSSOP20
75 / Rail
MC74HC244ADTR2
TSSOP20
2500 / Reel
MC74HC244A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
Vout = 0.1 V
|Iout|
20 A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
Vin = VIH
|Iout|
20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH
Vin = VIH
VOL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
Vin = VIL
|Iout|
20 A
Vin = VIL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
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181
MC74HC244A
v
v
v
v
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
6.0
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
6.0
0.5
5.0
10
ICC
6.0
4.0
40
160
Iin
NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
96
50
18
15
115
60
23
20
135
70
27
23
ns
tPLZ,
tPHZ
2.0
3.0
4.5
6.0
110
60
22
19
140
70
28
24
165
80
33
28
ns
tPZL,
tPZH
2.0
3.0
4.5
6.0
110
60
22
19
140
70
28
24
165
80
33
28
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
10
10
10
pF
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
34
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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182
MC74HC244A
SWITCHING WAVEFORMS
tr
tf
DATA INPUT
A OR B
VCC
VCC
90%
50%
10%
ENABLE
A OR B
GND
tPLH
50%
GND
tPHL
90%
50%
10%
OUTPUT
YA OR YB
tPZH
tTHL
HIGH
IMPEDANCE
50%
OUTPUT Y
tTLH
tPLZ
tPZL
OUTPUT Y
tPHZ
10%
VOL
90%
VOH
50%
Figure 1.
HIGH
IMPEDANCE
Figure 2.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
1 k
CL*
PIN DESCRIPTIONS
INPUTS
OUTPUTS
CONTROLS
Enable A, Enable B (Pins 1, 19)
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183
MC74HC244A
LOGIC DETAIL
TO THREE OTHER
A OR B INVERTERS
ONE OF 8
INVERTERS
VCC
DATA
INPUT
A OR B
YA
OR
YB
ENABLE A OR
ENABLE B
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184
MC74HCT244A
Octal 3-State Noninverting
Buffer/Line Driver/
Line Receiver with
LSTTL-Compatible Inputs
HighPerformance SiliconGate CMOS
The MC74HCT244A is identical in pinout to the LS244. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to HighSpeed CMOS inputs. The HCT244A is an octal
noninverting buffer line driver line receiver designed to be used with
3state memory address drivers, clock drivers, and other busoriented
systems. The device has noninverted outputs and two activelow
output enables.
The HCT244A is the noninverting version of the HCT240. See also
HCT241.
DATA INPUTS
B1
B2
B3
B4
18
16
14
12
11
13
15
17
1
OUTPUT ENABLE A
ENABLES ENABLE B 19
YA1
MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
MC74HCT244AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HCT244A
AWLYYWW
1
20
HCT
244A
ALYW
TSSOP20
DT SUFFIX
CASE 948G
20
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
YA2
ENABLE A
20
VCC
YA3
A1
19
ENABLE B
YB4
18
YA1
YA4
YB1
NONINVERTING
OUTPUTS
YB2
YB3
YB4
A2
17
B4
YB3
16
YA2
A3
15
B3
YB2
14
YA3
A4
13
B2
YB1
12
YA4
GND
10
11
B1
PIN 20 = VCC
PIN 10 = GND
ORDERING INFORMATION
FUNCTION TABLE
Inputs
Enable A,
Enable B
Device
Outputs
MC74HCT244AN
A, B
YA, YB
MC74HCT244ADW
L
L
L
L
H
H
H
X
Z
Z = high impedance, X = dont care
Semiconductor Components Industries, LLC, 1999
http://onsemi.com
Package
Shipping
PDIP20
1440 / Box
SOICWIDE
MC74HCT244ADWR2 SOICWIDE
185
38 / Rail
1000 / Reel
MC74HCT244ADT
TSSOP20
75 / Rail
MC74HCT244ADTR2
TSSOP20
2500 / Reel
MC74HCT244A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
VCC
55
+ 125
_C
500
ns
TA
tr, tf
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
4.5
5.5
2
2
2
2
2
2
VIL
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
4.5
3.98
3.84
3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.4
5.5
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
5.5
0.5
5.0
10
ICC
5.5
40
160
VOH
VOL
Iin
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186
MC74HCT244A
ICC
55_C
25_C to 125_C
2.9
2.4
5.5
mA
NOTES:
1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + ICC.
v
v
Guaranteed Limit
Symbol
55 to
25_C
Parameter
85_C
125_C
Unit
tPLH,
tPHL
20
25
30
ns
tPLZ,
tPHZ
26
33
39
ns
tPZL,
tPZH
22
28
33
ns
tTLH,
tTHL
12
15
18
ns
10
10
10
pF
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
55
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
3V
tr
ENABLE
A OR B
tf
INPUT
A OR B
3V
2.7 V
1.3 V
0.3 V
tPLH
tPLZ
HIGH
IMPEDANCE
GND
OUTPUT Y
90%
1.3 V
10%
1.3 V
tPZH
OUTPUT Y
tTHL
tTLH
GND
tPZL
tPHL
OUTPUT
YA OR YB
1.3 V
Figure 1.
tPHZ
1.3 V
187
VOL
90%
VOH
HIGH
IMPEDANCE
Figure 2.
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10%
MC74HCT244A
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
1 k
CL*
Figure 3.
Figure 4.
LOGIC DETAIL
TO THREE OTHER
A OR B INVERTERS
ONE OF 8
BUFFERS
VCC
DATA INPUT
A OR B
YA
OR
YB
ENABLE A OR ENABLE B
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188
MC74HC245A
Octal 3-State Noninverting
Bus Transceiver
HighPerformance SiliconGate CMOS
The MC74HC245A is identical in pinout to the LS245. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC245A is a 3state noninverting transceiver that is used for
2way asynchronous communication between data buses. The device
has an activelow Output Enable pin, which is used to place the I/O
ports into highimpedance states. The Direction control determines
whether data flows from A to B or from B to A.
A4
A5
A6
A7
A8
DIRECTION
OUTPUT ENABLE
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
MC74HC245AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HC245A
AWLYYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
18
17
16
15
14
13
12
11
B1
B2
B3
DIRECTION
20
VCC
A1
19
OUTPUT ENABLE
A2
18
B1
A3
17
B2
B6
A4
16
B3
B7
A5
15
B4
B8
A6
14
B5
A7
13
B6
A8
12
B7
10
11
B8
B
DATA
PORT
B4
B5
1
19
GND
PIN 10 = GND
PIN 20 = VCC
FUNCTION TABLE
ORDERING INFORMATION
Control Inputs
Device
Output
Enable
Direction
Package
Shipping
PDIP20
1440 / Box
MC74HC245ADW
SOICWIDE
38 / Rail
MC74HC245ADWR2
SOICWIDE
1000 / Reel
MC74HC245AN
Operation
X = dont care
189
MC74HC245A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
VI/O
Iin
20
mA
II/O
35
mA
ICC
75
mA
PD
750
500
mW
Tstg
Storage Temperature
65 to + 150
_C
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
TA
tr, tf
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
Vout = 0.1 V
|Iout|
20 A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
Vin = VIH
|Iout|
20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH
Vin = VIH
VOL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
Vin = VIL
|Iout|
20 A
Vin = VIL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
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190
MC74HC245A
v
v
v
v
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
6.0
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
6.0
0.5
5.0
10
ICC
6.0
4.0
40
160
Iin
NOTE: Information on typical parametric values and high frequency or heavy load considerations can be found in Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
75
55
15
13
95
70
19
16
110
80
22
19
ns
tPLZ,
tPHZ
2.0
3.0
4.5
6.0
110
90
22
19
140
110
28
24
165
130
33
28
ns
tPZL,
tPZH
2.0
3.0
4.5
6.0
110
90
22
19
140
110
28
24
165
130
33
28
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
Cin
10
10
10
pF
15
15
15
pF
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
40
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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191
MC74HC245A
SWITCHING WAVEFORMS
VCC
50%
DIRECTION
GND
VCC
tr
OUTPUT
ENABLE
tf
INPUT
A OR B
VCC
90%
50%
10%
GND
tPZL
GND
tPLH
tPHL
A OR B
90%
50%
10%
OUTPUT
B OR A
50%
HIGH
IMPEDANCE
50%
tPZH
A OR B
tPLZ
tPHZ
10%
VOL
90%
VOH
50%
HIGH
IMPEDANCE
tTHL
tTLH
Figure 1.
Figure 2.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
1 k
CL*
Figure 3.
Figure 4.
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192
MC74HC245A
EXPANDED LOGIC DIAGRAM
A1
2
18
A2
3
17
A3
15
OUTPUT ENABLE
B7
9
11
DIRECTION
B6
8
12
A8
B5
7
13
A7
B4
6
14
A6
B3
A
DATA
PORT
A5
B2
4
16
A4
B1
19
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193
B8
B
DATA
PORT
MC74HCT245A
Octal 3-State Noninverting
Bus Transceiver with LSTTL
Compatible Inputs
HighPerformance SiliconGate CMOS
The MC74HCT245A is identical in pinout to the LS245. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High Speed CMOS inputs.
The MC74HCT245A is a 3state noninverting transceiver that is
used for 2way asynchronous communication between data buses.
The device has an activelow Output Enable pin, which is used to
place the I/O ports into highimpedance states. The Direction control
determines whether data flows from A to B or from B to A.
Output Drive Capability: 15 LSTTL Loads
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 A
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 304 FETs or 76 Equivalent Gates
A2
A3
A
DATA
PORT
A4
A5
A6
A7
A8
DIRECTION
18
17
16
15
14
13
12
11
Design Criteria
20
MC74HCT245AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HCT245A
AWLYYWW
1
B2
B3
B4
B5
HCT
245A
ALYW
TSSOP20
DT SUFFIX
CASE 948G
20
B
DATA
PORT
B6
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
B7
DIRECTION
20
VCC
B8
A1
19
OUTPUT ENABLE
A2
18
B1
A3
17
B2
A4
16
B3
A5
15
B4
Value
Units
76
ea
A6
14
B5
1.0
ns
A7
13
B6
5.0
A8
12
B7
0.005
pJ
GND
10
11
B8
20
PIN 20 = VCC
PIN 10 = GND
19
20
PDIP20
P SUFFIX
CASE 738
B1
OUTPUT ENABLE
MARKING
DIAGRAMS
LOGIC DIAGRAM
A1
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FUNCTION TABLE
ORDERING INFORMATION
Control Inputs
Device
Output
Enable
Direction
L
H
X = Dont Care
Operation
MC74HCT245AN
Package
Shipping
PDIP20
1440 / Box
MC74HCT245ADW
MC74HCT245ADWR2 SOICWIDE
194
SOICWIDE
38 / Rail
1000 / Reel
MC74HCT245ADT
TSSOP20
75 / Rail
MC74HCT245ADTR2
TSSOP20
2500 / Reel
MC74HCT245A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
VCC
55
+ 125
_C
500
ns
TA
tr, tf
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
4.5
3.98
3.84
3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.4
VOH
VOL
5.5
0.1
1.0
1.0
ICC
5.5
4.0
40
160
IOZ
Maximum ThreeState
Leakage Current
5.5
0.5
5.0
10
Iin
ICC
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195
MC74HCT245A
v
v
Guaranteed Limit
Symbol
55 to
25_C
Parameter
85_C
125_C
Unit
tPLH,
tPHL
22
28
33
ns
tPLZ,
tPHZ
30
36
42
ns
tPZL,
tPZH
30
36
42
ns
tTLH,
tTHL
12
15
18
ns
10
10
10
pF
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
97
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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196
MC74HCT245A
SWITCHING WAVEFORMS
3.0 V
DIRECTION
1.3 V
1.3 V
GND
3.0 V
tr
tf
INPUT
A OR B
3.0 V
2.7 V
1.3 V
0.3 V
1.3 V
GND
tPZL
tPLZ
HIGH
IMPEDANCE
GND
tPLH
tPHL
90%
1.3 V
10%
OUTPUT
B OR A
OUTPUT
ENABLE
A OR B
1.3 V
tPZH
tTHL
tTLH
A OR B
10%
VOL
90%
VOH
1.3 V
Figure 1.
HIGH
IMPEDANCE
Figure 2.
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
tPHZ
OUTPUT
DEVICE
UNDER
TEST
CL*
1 k
CL*
Figure 3.
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197
MC74HCT245A
EXPANDED LOGIC DIAGRAM
A1
2
18
A2
3
17
A3
A4
B
DATA
PORT
OUTPUT ENABLE
B7
9
11
DIRECTION
B6
8
12
A8
B5
7
13
A7
B4
6
14
A6
B3
5
15
A5
B2
4
16
A
DATA
PORT
B1
19
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198
B8
MC74HC273A
Octal D Flip-Flop with
Common Clock and Reset
HighPerformance SiliconGate CMOS
The MC74HC273A is identical in pinout to the LS273. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of eight D flipflops with common Clock and
Reset inputs. Each flipflop is loaded with a lowtohigh transition of
the Clock input. Reset is asynchronous and active low.
D3
D4
D5
D6
D7
CLOCK
RESET
13
12
15
17
16
18
19
11
Q2
Q3
Q4
NONINVERTING
OUTPUTS
20
HC
273A
ALYW
TSSOP20
DT SUFFIX
CASE 948G
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
20
VCC
Q7
Q0
19
Q7
D0
18
D7
D1
17
D6
Q1
16
Q6
Q2
15
Q5
D2
14
D5
D3
13
D4
Q3
12
Q4
10
11
CLOCK
L
H
H
H
H
X
H
L
X
X
L
H
L
No Change
No Change
GND
Value
Units
66
ea
1.5
ns
5.0
.0075
pJ
HC273A
AWLYYWW
RESET
SOIC WIDE20
DW SUFFIX
CASE 751D
Q6
Clock
20
PIN ASSIGNMENT
Q5
Reset
1
20
Output
Design Criteria
20
MC74HC273AN
AWLYYWW
Q1
FUNCTION TABLE
20
PDIP20
P SUFFIX
CASE 738
Q0
PIN 20 = VCC
PIN 10 = GND
Inputs
MARKING
DIAGRAMS
20
14
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199
ORDERING INFORMATION
Device
MC74HC273AN
Package
Shipping
PDIP20
1440 / Box
MC74HC273ADW
SOICWIDE
38 / Rail
MC74HC273ADWR2
SOICWIDE
1000 / Reel
MC74HC273ADT
TSSOP20
75 / Rail
MC74HC273ADTR2
TSSOP20
2500 / Reel
MC74HC273A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
Vout = 0.1 V
|Iout|
20 A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
Vin = VIH
|Iout|
20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH
Vin = VIH
VOL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
Vin = VIL
|Iout|
20 A
Vin = VIL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
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200
MC74HC273A
v
v
v
v
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
6.0
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
6.0
0.5
5.0
10
ICC
6.0
4.0
40
160
Iin
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
fmax
2.0
3.0
4.5
6.0
6.0
15
30
35
5.0
10
24
28
4.0
8.0
20
24
MHz
tPLH
tPHL
2.0
3.0
4.5
6.0
145
90
29
25
180
120
36
31
220
140
44
38
ns
tPHL
2.0
3.0
4.5
6.0
145
90
29
25
180
120
36
31
220
140
44
38
ns
tTLH
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
48
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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201
MC74HC273A
v
v
Guaranteed Limit
Symbol
Parameter
VCC
Volts
Fig.
55 to 25_C
Min
Max
85_C
Min
Max
125_C
Min
Max
Unit
tsu
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
th
2.0
3.0
4.5
6.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
ns
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
tw
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
tw
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
2.0
3.0
4.5
6.0
trec
tr, tf
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202
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
MC74HC273A
SWITCHING WAVEFORMS
tr
CLOCK
tw
tf
VCC
90%
50%
10%
tw
GND
GND
1/fmax
tPHL
50%
tPLH
Q
VCC
50%
RESET
tPHL
trec
90%
50%
10%
VCC
50%
CLOCK
tTLH
GND
tTHL
Figure 1.
Figure 2.
VALID
VCC
DATA
50%
GND
tsu
th
VCC
CLOCK
50%
GND
Figure 3.
C
D0
DR
C
D1
DR
C
D2
TEST POINT
DR
C
OUTPUT
DEVICE
UNDER
TEST
CL*
DATA
INPUTS
D3
DR
C
D4
13
DR
C
D5
14
DR
C
D7
17
18
11
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203
DR
C
DR
Q0
Q1
Q2
Q3
NONINVERTING
OUTPUTS
12
15
16
19
Q4
Q5
Q6
Q7
MC74HCT273A
Octal D Flip-Flop with
Common Clock and Reset
with LSTTL-Compatible
Inputs
HighPerformance SiliconGate CMOS
The MC74HCT273A may be used as a level converter for
interfacing TTL or NMOS outputs to HighSpeed CMOS inputs.
The HCT273A is identical in pinout to the LS273.
This device consists of eight D flipflops with common Clock and
Reset inputs. Each flipflop is loaded with a lowtohigh transition of
the Clock input. Reset is asynchronous and active low.
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
13
12
14
15
17
MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HCT273A
AWLYYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
16
18
19
11
RESET
20
VCC
Q0
19
Q7
D0
18
D7
D1
17
D6
Q1
16
Q6
Q2
15
Q5
Q5
D2
14
D5
Q6
D3
13
D4
Q3
12
Q4
10
11
CLOCK
Q0
Q1
Q2
Q3
Q4
NONINVERTING
OUTPUTS
Q7
GND
RESET
MC74HCT273AN
AWLYYWW
PIN ASSIGNMENT
LOGIC DIAGRAM
D0
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PIN 20 = VCC
PIN 10 = GND
FUNCTION TABLE
Inputs
ORDERING INFORMATION
Clock
L
H
H
H
H
X
H
L
X
X
L
H
L
No Change
No Change
Device
Output
Reset
MC74HCT273AN
MC74HCT273ADW
Package
Shipping
PDIP20
1440 / Box
SOICWIDE
MC74HCT273ADWR2 SOICWIDE
38 / Rail
1000 / Reel
X = Dont Care
Z = High Impedance
204
MC74HCT273A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
VCC
55
+ 125
_C
500
ns
TA
tr, tf
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
4.5
3.98
3.84
3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.4
5.5
0.1
1.0
1.0
ICC
5.5
4.0
40
160
ICC
VOH
VOL
Iin
5.5
55_C
25_C to 125_C
2.9
2.4
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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205
MC74HCT273A
v
v
Guaranteed Limit
Symbol
Parameter
Fig.
55 to
25_C
85_C
125_C
Unit
fmax
1, 4
30
24
20
MHz
tPLH,
tPHL
1, 4
25
28
35
ns
tPHL
2, 4
25
28
35
ns
tTLH,
tTHL
1, 5
18
20
22
ns
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
30
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Guaranteed Limit
55 to 25_C
Symbol
Parameter
Fig.
Min
Max
85_C
Min
Max
125_C
Min
Max
Unit
tsu
10
12
15
ns
th
3.0
3.0
3.0
ns
5.0
5.0
5.0
ns
tw
12
15
18
ns
tw
12
15
18
ns
tr, tf
trec
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206
500
500
500
ns
MC74HCT273A
SWITCHING WAVEFORMS
tr
CLOCK
tw
tf
3.0 V
3.0 V
2.7 V
1.3 V
0.3 V
tw
GND
GND
tPHL
1/fmax
1.3 V
tPLH
Q
1.3 V
RESET
tPHL
trec
90%
1.3 V
10%
3.0 V
1.3 V
CLOCK
tTLH
GND
tTHL
Figure 1.
Figure 2.
TEST POINT
VALID
OUTPUT
3.0 V
DATA
DEVICE
UNDER
TEST
1.3 V
GND
tsu
th
CL*
3.0 V
CLOCK
1.3 V
GND
*Includes all probe and jig capacitance
Figure 3.
DR
C
D1
DR
C
D2
DR
C
DATA
INPUTS
D3
DR
C
D4
13
DR
C
D5
14
DR
C
D6
D7
CLOCK
RESET
17
DR
C
18
DR
Q0
Q1
Q2
Q3
NONINVERTING
OUTPUTS
11
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207
12
15
16
19
Q4
Q5
Q6
Q7
MC74HC373A
Octal 3-State Non-Inverting
Transparent Latch
HighPerformance SiliconGate CMOS
The MC74HC373A is identical in pinout to the LS373. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
highimpedance state. Thus, data may be latched even when the
outputs are not enabled.
The HC373A is identical in function to the HC573A which has the
data inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
The HC373A is the noninverting version of the HC533A.
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
MC74HC373AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HC373A
AWLYYWW
1
20
HC
373A
ALYW
TSSOP20
DT SUFFIX
CASE 948G
20
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
PDIP20
1440 / Box
MC74HC373ADW
SOICWIDE
38 / Rail
MC74HC373ADWR2
SOICWIDE
1000 / Reel
MC74HC373ADT
TSSOP20
75 / Rail
MC74HC373ADTR2
TSSOP20
2500 / Reel
MC74HC373AN
208
MC74HC373A
PIN ASSIGNMENT
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
LATCH ENABLE
OUTPUT ENABLE
13
12
14
15
17
16
18
19
11
1
Q0
Q1
Q2
Q3
NONINVERTING
OUTPUTS
Q4
Q5
20
VCC
19
Q7
D0
18
D7
D1
17
D6
Q1
16
Q6
Q2
15
Q5
D2
14
D5
D3
13
D4
Q3
12
Q4
10
11
LATCH
ENABLE
Q6
FUNCTION TABLE
Q7
Inputs
Output
Enable
PIN 20 = VCC
PIN 10 = GND
Value
Units
46.5
ea
1.5
ns
5.0
0.0075
pJ
GND
Design Criteria
OUTPUT
ENABLE
Q0
http://onsemi.com
209
Latch
Enable
L
H
L
H
L
L
H
X
X = Dont Care
Z = High Impedance
Output
D
H
L
X
X
H
L
No Change
Z
MC74HC373A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
Vout = 0.1 V
|Iout|
20 A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
Vin = VIH
|Iout|
20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH
Vin = VIH
VOL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
Vin = VIL
|Iout|
20 A
Vin = VIL
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
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210
MC74HC373A
v
v
v
v
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
6.0
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
6.0
0.5
5.0
10
ICC
6.0
4.0
40
160
Iin
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tPLH
tPHL
2.0
3.0
4.5
6.0
125
80
25
21
155
110
31
26
190
130
38
32
ns
tPLH
tPHL
2.0
3.0
4.5
6.0
140
90
28
24
175
120
35
30
210
140
42
36
ns
tPLZ
tPHZ
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL
tPZH
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tTLH
tTHL
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
10
10
10
pF
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
36
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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211
MC74HC373A
v
v
Guaranteed Limit
Symbol
Parameter
Fig.
VCC
Volts
55 to 25_C
Min
85_C
Max
Min
125_C
Max
Min
Max
Unit
tsu
2.0
3.0
4.5
6.0
25
20
5.0
5.0
30
25
6.0
6.0
40
30
8.0
7.0
ns
th
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
50
5.0
5.0
5.0
5.0
5.0
ns
tw
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
tr, tf
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
SWITCHING WAVEFORMS
tr
tf
INPUT D
tw
VCC
90%
50%
10%
LATCH ENABLE
GND
tPLH
GND
tPHL
Figure 1.
VCC
GND
tPLZ
VALID
HIGH
IMPEDANCE
50%
tPZH
Figure 2.
50%
tPZL
50%
tTHL
tTLH
OUTPUT
ENABLE
tPHL
tPLH
90%
50%
10%
VCC
50%
INPUT D
tsu
10%
VOL
90%
VOH
tPHZ
1.3 V
VCC
50%
GND
th
VCC
LATCH ENABLE
50%
GND
HIGH
IMPEDANCE
Figure 3.
Figure 4.
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212
MC74HC373A
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
1 k
OUTPUT
CL*
Figure 5.
Figure 6.
D1
4
D
D2
7
D
LE
D3
8
D
LE
D4
13
D
LE
D5
14
D
LE
D6
17
D
LE
D7
18
D
LE
LE
LE
11
1
2
Q0
5
Q1
6
Q2
9
Q3
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213
12
Q4
15
Q5
16
Q6
19
Q7
MC74HCT373A
Octal 3-State Noninverting
Transparent Latch with
LSTTL-Compatible Inputs
HighPerformance SiliconGate CMOS
The MC74HCT373A may be used as a level converter for
interfacing TTL or NMOS outputs to HighSpeed CMOS inputs.
The HCT373A is identical in pinout to the LS373.
The eight latches of the HCT373A are transparent Dtype latches.
While the Latch Enable is high the Q outputs follow the Data Inputs.
When Latch Enable is taken low, data meeting the setup and hold
times becomes latched.
The Output Enable does not affect the state of the latch, but when
Output Enable is high, all outputs are forced to the highimpedance
state. Thus, data may be latched even when the outputs are not
enabled.
The HCT373A is identical in function to the HCT573A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT533A, which has
inverting outputs.
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
MC74HCT373AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HCT373A
AWLYYWW
1
20
HCT
373A
ALYW
TSSOP20
DT SUFFIX
CASE 948G
20
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
ENABLE A
20
VCC
A1
19
ENABLE B
YB4
18
YA1
A2
17
B4
YB3
16
YA2
A3
15
B3
YB2
14
YA3
A4
13
B2
YB1
12
YA4
GND
10
11
B1
ORDERING INFORMATION
Device
MC74HCT373AN
MC74HCT373ADW
Package
Shipping
PDIP20
1440 / Box
SOICWIDE
MC74HCT373ADWR2 SOICWIDE
214
38 / Rail
1000 / Reel
MC74HCT373ADT
TSSOP20
75 / Rail
MC74HCT373ADTR2
TSSOP20
2500 / Reel
MC74HCT373A
PIN ASSIGNMENT
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
LATCH ENABLE
OUTPUT ENABLE
13
12
14
15
17
16
18
19
11
1
20
VCC
19
Q7
D0
18
D7
D1
17
D6
Q1
16
Q6
Q1
Q2
15
Q5
Q2
D2
14
D5
D3
13
D4
Q3
12
Q4
10
11
LATCH
ENABLE
Q3
NONINVERTING
OUTPUTS
Q4
GND
Q5
Q6
FUNCTION TABLE
Q7
Inputs
PIN 20 = VCC
PIN 10 = GND
Value
Units
49
ea.
1.5
ns
5.0
.0075
pJ
Q0
Design Criteria
OUTPUT
ENABLE
Q0
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215
Output
Output
Enable
Latch
Enable
L
L
L
H
H
H
L
X
H
L
X
X
H
L
No Change
Z
X = dont care
Z = high impedance
MC74HCT373A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
VCC
55
+ 125
_C
500
ns
TA
tr, tf
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
4.5
3.98
3.84
3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.4
5.5
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
5.5
0.5
5.0
10
ICC
5.5
4.0
40
160
VOH
VOL
Iin
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216
MC74HCT373A
v
v
ICC
5.5
55_C
25_C to 125_C
2.9
2.4
mA
Guaranteed Limit
Symbol
55 to
25_C
Parameter
85_C
125_C
Unit
tPLH,
tPHL
28
35
42
ns
tPLH,
tPHL
32
40
48
ns
tPLZ,
tPHZ
30
38
45
ns
tPZL,
tPZH
35
44
53
ns
tTLH,
tTHL
12
15
18
ns
10
10
10
pF
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
65
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Guaranteed Limit
Symbol
55 to
25_C
Parameter
85_C
125_C
Unit
tsu
10
13
15
ns
th
10
13
15
ns
tw
12
15
18
ns
tr, tf
500
500
500
ns
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217
MC74HCT373A
EXPANDED LOGIC DIAGRAM
D0
3
D1
4
D
D2
7
D
LE
D3
8
D
LE
D4
13
D
LE
D5
14
D
LE
D6
17
D
LE
D7
18
D
LE
LE
LE
LATCH 11
ENABLE
OUTPUT 1
ENABLE
2
Q0
5
Q1
6
Q2
9
Q3
12
Q4
15
Q5
16
Q6
19
Q7
SWITCHING WAVEFORMS
tr
tf
INPUT D
tw
3V
2.7 V
1.3 V
0.3 V
LATCH ENABLE
GND
tPLH
GND
tPHL
tTLH
3V
GND
tPLZ
VALID
3V
HIGH
IMPEDANCE
1.3 V
tPZH
Figure 2.
1.3 V
tPZL
1.3 V
tTHL
Figure 1.
OUTPUT
ENABLE
tPHL
tPLH
90%
1.3 V
10%
3V
1.3 V
1.3 V
10%
VOL
90%
VOH
INPUT D
GND
tsu
tPHZ
1.3 V
1.3 V
LATCH ENABLE
th
3V
1.3 V
GND
HIGH
IMPEDANCE
Figure 3.
Figure 4.
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218
MC74HCT373A
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
1 k
CL*
Figure 5.
Figure 6.
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219
MC74HC374A
Octal 3-State Non-Inverting
D Flip-Flop
HighPerformance SiliconGate CMOS
The MC74HC374A is identical in pinout to the LS374. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the clock. The Output Enable input does not affect the states of
the flipflops, but when Output Enable is high, the outputs are forced
to the highimpedance state; thus, data may be stored even when the
outputs are not enabled.
The HC374A is identical in function to the HC574A which has the
input pins on the opposite side of the package from the output. This
device is similar in function to the HC534A which has inverting
outputs.
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
13
12
14
15
17
16
18
19
11
Q0
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
MC74HC374AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HC374A
AWLYYWW
1
20
HC
374A
ALYW
TSSOP20
DT SUFFIX
CASE 948G
20
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
Q1
OUTPUT
ENABLE
Q0
20
VCC
19
Q7
D0
18
D7
D1
17
D6
Q5
Q1
16
Q6
Q6
Q2
15
Q5
Q7
D2
14
D5
D3
13
D4
Q3
12
Q4
10
11
CLOCK
Q2
Q3
NONINVERTING
OUTPUTS
Q4
PIN 20 = VCC
PIN 10 = GND
GND
FUNCTION TABLE
Inputs
Output
Enable
L
L
L
H
Output
Clock
L,H,
X
H
L
X
X
H
L
No Change
Z
ORDERING INFORMATION
Device
MC74HC374AN
X = dont care
Z = high impedance
Semiconductor Components Industries, LLC, 1999
220
Package
Shipping
PDIP20
1440 / Box
MC74HC374ADW
SOICWIDE
38 / Rail
MC74HC374ADWR2
SOICWIDE
1000 / Reel
MC74HC374ADT
TSSOP20
75 / Rail
MC74HC374ADTR2
TSSOP20
2500 / Reel
MC74HC374A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
2.0
4.5
6.0
1.90
4.40
5.90
1.90
4.40
5.90
1.90
4.40
5.90
3.0
4.5
6.0
2.48
2.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
2.4 mA
6.0 mA
7.8 mA
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221
MC74HC374A
v
v
v
v
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
2.4 mA
6.0 mA
7.8 mA
VCC
V
55 to
25_C
2.0
4.5
6.0
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
0.10
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
85_C
125_C
Unit
V
6.0
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
6.0
0.5
5.0
10
ICC
6.0
40
160
Iin
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
fmax
2.0
3.0
4.5
6.0
6
15
30
35
5
10
24
28
4
8
20
24
MHz
tPLH
tPHL
2.0
3.0
4.5
6.0
125
80
25
21
155
110
31
26
190
130
38
32
ns
tPLZ
tPHZ
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPLZ
tPHZ
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tTLH
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
34
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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222
MC74HC374A
v
v
Guaranteed Limit
Symbol
Parameter
VCC
Volts
Fig.
55 to 25_C
Min
85_C
Max
Min
Max
125_C
Min
Max
Unit
tsu
2.0
3.0
4.5
6.0
50
40
10
9
65
50
13
11
75
60
15
13
ns
th
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
50
5.0
5.0
5.0
5.0
5.0
5.0
ns
tw
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
2.0
3.0
4.5
6.0
tr, tf
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
SWITCHING WAVEFORMS
CLOCK
tr
90%
50%
tf
VCC
VCC
10%
OUTPUT
ENABLE
50%
GND
GND
tPZL
tPLZ
tPZH
tPHZ
HIGH
IMPEDANCE
tW
1/fmax
tPLH
50%
tPHL
90%
Q
50%
10%
Q
tTLH
50%
Figure 2.
VALID
VCC
DATA
50%
GND
th
tsu
VCC
CLOCK
50%
GND
Figure 3.
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223
VOL
90%
VOH
HIGH
IMPEDANCE
tTHL
Figure 1.
10%
MC74HC374A
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
1 k
OUTPUT
CL*
Figure 4.
Figure 5.
D1
4
D
C
Clock
D2
7
Q
D3
8
D
D4
13
D
D5
14
D
D6
17
D
D7
18
D
11
Output 1
Enable
2
Q0
5
Q1
6
Q2
9
Q3
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224
12
Q4
15
Q5
16
Q6
19
Q7
MC74HCT374A
Octal 3-State Noninverting
D Flip-Flop with
LSTTL-Compatible Inputs
HighPerformance SiliconGate CMOS
The MC74HCT374A may be used as a level converter for
interfacing TTL or NMOS outputs to HighSpeed CMOS inputs.
The HCT374A is identical in pinout to the LS374.
Data meeting the setup and hold time is clocked to the outputs with
the rising edge of Clock. The Output Enable does not affect the state of
the flipflops, but when Output Enable is high, the outputs are forced
to the highimpedance state. Thus, data may be stored even when the
outputs are not enabled.
The HCT374A is identical in function to the HCT574A, which has
the input pins on the opposite side of the package from the output pins.
This device is similar in function to the HCT534A, which has
inverting outputs.
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
MC74HCT374AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HCT374A
AWLYYWW
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC74HCT374ADW
Package
Shipping
PDIP20
1440 / Box
SOICWIDE
38 / Rail
MC74HCT374ADWR2 SOICWIDE
225
HCT
374A
ALYW
TSSOP20
DT SUFFIX
CASE 948G
20
MC74HCT374AN
20
1000 / Reel
MC74HCT374ADT
TSSOP20
75 / Rail
MC74HCT374ADTR2
TSSOP20
2500 / Reel
MC74HCT374A
PIN ASSIGNMENT
OUTPUT
ENABLE
Q0
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
13
12
14
15
17
16
18
19
Q0
Q1
Q2
Q3
Q4
NONINVERTING
OUTPUTS
Q5
20
VCC
19
Q7
D0
18
D7
D1
17
D6
Q1
16
Q6
Q2
15
Q5
D2
14
D5
D3
13
D4
Q3
12
Q4
10
11
CLOCK
GND
Q6
Q7
FUNCTION TABLE
11
Inputs
OUTPUT ENABLE
Output
Enable
PIN 20 = VCC
PIN 10 = GND
L
L
L
H
Value
Units
Design Criteria
69
ea.
1.5
ns
5.0
.0075
pJ
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226
Output
Clock
L,H,
X
H
L
X
X
H
L
No Change
Z
X = dont care
Z = high impedance
MC74HCT374A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
VCC
55
+ 125
_C
500
ns
TA
tr, tf
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
4.5
3.98
3.84
3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.4
5.5
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
5.5
0.5
5.0
10
ICC
5.5
4.0
40
160
VOH
VOL
Iin
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227
MC74HCT374A
v
v
ICC
55_C
25_C to 125_C
2.9
2.4
5.5
mA
Guaranteed Limit
55 to
25_C
85_C
125_C
Unit
fmax
30
24
20
MHz
tPLH,
tPHL
31
39
47
ns
tPLZ,
tPHZ
30
38
45
ns
tPZL,
tPZH
30
38
45
ns
tTLH,
tTHL
12
15
18
ns
10
10
10
pF
15
15
15
pF
Symbol
Cin
Cout
Parameter
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
65
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Guaranteed Limit
55 to
25_C
85_C
125_C
tsu
12
15
18
ns
th
5.0
5.0
5.0
ns
tw
12
15
18
ns
500
500
500
ns
Symbol
tr, tf
Parameter
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228
Unit
MC74HCT374A
SWITCHING WAVEFORMS
tr
CLOCK
tf
3V
OUTPUT
ENABLE
VCC
2.7 V
1.3 V
0.3 V
tw
GND
GND
Q
1/fmax
tPLH
Q
1.3 V
tPZL
tPLZ
tPZH
tPHZ
tPHL
90%
1.3 V
10%
Q
tTLH
HIGH
IMPEDANCE
1.3 V
10%
VOL
90%
VOH
1.3 V
HIGH
IMPEDANCE
tTHL
Figure 1.
Figure 2.
VALID
3V
DATA
1.3 V
GND
tsu
th
3V
CLOCK
1.3 V
GND
Figure 3.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
1 k
OUTPUT
CL*
Figure 4.
Figure 5.
D1
4
D
Q
C
CLOCK
D2
7
Q
D3
8
D
D4
13
D
D5
14
D
D6
17
D
D7
18
D
Q
C
11
OUTPUT 1
ENABLE
2
Q0
5
Q1
6
Q2
9
Q3
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229
12
Q4
15
Q5
16
Q6
19
Q7
MC74HC390A
Dual 4-Stage Binary Ripple
Counter with 2 and 5
Sections
HighPerformance SiliconGate CMOS
The MC74HC390A is identical in pinout to the LS390. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4bit counters, each
composed of a dividebytwo and a dividebyfive section. The
dividebytwo and dividebyfive counters have separate clock
inputs, and can be cascaded to implement various combinations of 2
and/or 5 up to a 100 counter.
Flipflops internal to the counters are triggered by hightolow
transitions of the clock input. A separate, asynchronous reset is
provided for each 4bit counter. State changes of the Q outputs do not
occur simultaneously because of internal ripple delays. Therefore,
decoded output signals are subject to decoding spikes and should not
be used as clocks or strobes except when gated with the Clock of the
HC390A.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No 7A
Chip Complexity: 244 FETs or 61 Equivalent Gates
LOGIC DIAGRAM
2
COUNTER
1, 15
CLOCK A
3, 13
QA
5, 11
5
COUNTER
4, 12
CLOCK B
QB
6, 10
QC
7, 9
QD
MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
MC74HC390AN
AWLYYWW
1
16
SO16
D SUFFIX
CASE 751B
16
HC390A
AWLYWW
1
16
HC
390A
ALYW
TSSOP16
DT SUFFIX
CASE 948F
16
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
CLOCK Aa
16
VCC
RESET a
15
CLOCK Ab
QAa
14
RESET b
CLOCK Ba
13
QAb
QBa
12
CLOCK Bb
QCa
11
QBb
QDa
10
QCb
GND
QDb
PIN 16 = VCC
PIN 8 = GND
2, 14
RESET
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FUNCTION TABLE
ORDERING INFORMATION
Clock
A
Reset
Action
Reset
2 and 5
Increment
2
Increment
5
Device
230
Package
Shipping
MC74HC390AN
PDIP16
2000 / Box
MC74HC390AD
SOIC16
48 / Rail
MC74HC390ADR2
SOIC16
2500 / Reel
MC74HC390ADT
TSSOP16
96 / Rail
MC74HC390ADTR2
TSSOP16
2500 / Reel
MC74HC390A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
0
1000
600
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
2.4 mA
4.0 mA
5.2 mA
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231
MC74HC390A
v
v
v
v
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
Iin
ICC
2.4 mA
4.0 mA
5.2 mA
VCC
V
55 to
25_C
2.0
4.5
6.0
85_C
125_C
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Unit
V
6.0
0.1
1.0
1.0
6.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
VCC
V
55 to
25_C
85_C
125_C
Unit
fmax
2.0
3.0
4.5
6.0
10
15
30
50
9
14
28
45
8
12
25
40
MHz
tPLH,
tPHL
2.0
3.0
4.5
6.0
70
40
24
20
80
45
30
26
90
50
36
31
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
200
160
58
49
250
185
65
62
300
210
70
68
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
70
40
26
22
80
45
33
28
90
50
39
33
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
90
56
37
31
105
70
46
39
180
100
56
48
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
70
40
26
22
80
45
33
28
90
50
39
33
ns
tPHL
2.0
3.0
4.5
6.0
80
48
30
26
95
65
38
33
110
75
44
39
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
Symbol
Parameter
Cin
Maximum Input Capacitance
10
10
10
pF
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
35
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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232
MC74HC390A
v
v
Guaranteed Limit
VCC
V
55 to
25_C
2.0
3.0
4.5
6.0
tw
tw
85_C
125_C
25
15
10
9
30
20
13
11
40
30
15
13
ns
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
2.0
3.0
4.5
6.0
75
27
20
18
95
32
24
22
110
36
30
28
ns
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
Symbol
Parameter
trec
tf, tf
Unit
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
Clock A (Pins 1, 15) and Clock B (Pins 4, 15)
OUTPUTS
QA (Pins 3, 13)
CONTROL INPUTS
Reset (Pins 2, 14)
SWITCHING WAVEFORMS
CLOCK
tf
90%
50%
10% 10%
tw
tr
tw
VCC
VCC
GND
GND
tPHL
1/fmax
tPLH
Q
50%
RESET
tPHL
90%
50%
10%
50%
trec
tTLH
VCC
50%
CLOCK
tTHL
GND
Figure 1.
Figure 2.
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233
MC74HC390A
TEST CIRCUIT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
Figure 3.
EXPANDED LOGIC DIAGRAM
1, 15
CLOCK A
C
D
4, 12
CLOCK B
5, 11
QB
C
D
QA
C
D
3, 13
6, 10 Q
C
7, 9 Q
D
C
D
2, 14
RESET
TIMING DIAGRAM
(QA Connected to Clock B)
0
CLOCK A
RESET
QA
QB
QC
QD
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234
MC74HC390A
APPLICATIONS INFORMATION
Each half of the MC54/74HC390A has independent 2
and 5 sections (except for the Reset function). The 2 and
5 counters can be connected to give BCD or biquinary
(25) count sequences. If Output QA is connected to the
Clock B input (Figure 4), a decade divider with BCD output
is obtained. The function table for the BCD count sequence
is given in Table 1.
Output
Output
Count
QD
QC
QB
QA
Count
QA
QD
QC
QB
0
1
2
3
4
5
6
7
8
9
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
0
1
2
3
4
8
9
10
11
12
L
L
L
L
L
H
H
H
H
H
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
L
H
H
L
L
H
L
H
L
L
H
L
H
L
CONNECTION DIAGRAMS
CLOCK A
CLOCK B
RESET
1, 15
4, 12
2
COUNTER
3, 13
5
COUNTER
6, 10
5, 11
7, 9
1, 15
QA
CLOCK A
QB
CLOCK B
4, 12
QC
QD
2
COUNTER
5
COUNTER
3, 13
QA
5, 11
QB
6, 10
7, 9
2, 14
2, 14
RESET
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235
QC
QD
MC74HC393A
Dual 4-Stage Binary Ripple
Counter
HighPerformance SiliconGate CMOS
The MC74HC393A is identical in pinout to the LS393. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of two independent 4bit binary ripple counters
with parallel outputs from each counter stage. A 256 counter can be
obtained by cascading the two binary counters.
Internal flipflops are triggered by hightolow transitions of the
clock input. Reset for the counters is asynchronous and activehigh.
State changes of the Q outputs do not occur simultaneously because of
internal ripple delays. Therefore, decoded output signals are subject to
decoding spikes and should not be used as clocks or as strobes except
when gated with the Clock of the HC393A.
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MARKING
DIAGRAMS
14
PDIP14
N SUFFIX
CASE 646
MC74HC393AN
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
HC393A
AWLYWW
1
14
HC
393A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
LOGIC DIAGRAM
PIN ASSIGNMENT
3, 11
CLOCK
4, 10
1, 13
BINARY
COUNTER
5, 9
6, 8
RESET
Q1
Q2
Q3
Q4
2, 12
PIN 14 = VCC
PIN 7 = GND
CLOCK a
14
VCC
RESET a
13
CLOCK b
Q1a
12
RESET b
Q2a
11
Q1b
Q3a
10
Q2b
Q4a
Q3b
GND
Q4b
FUNCTION TABLE
Inputs
Clock
Reset
Outputs
X
H
L
H
L
L
L
L
L
No Change
No Change
No Change
Advance to
Next State
ORDERING INFORMATION
Device
236
Package
Shipping
MC74HC393AN
PDIP14
2000 / Box
MC74HC393AD
SOIC14
55 / Rail
MC74HC393ADR2
SOIC14
2500 / Reel
MC74HC393ADT
TSSOP14
96 / Rail
MC74HC393ADTR2
TSSOP14
2500 / Reel
MC74HC393A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
0
1000
600
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
2.4 mA
4.0 mA
5.2 mA
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237
MC74HC393A
v
v
v
v
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
Iin
ICC
2.4 mA
4.0 mA
5.2 mA
VCC
V
55 to
25_C
2.0
4.5
6.0
85_C
125_C
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Unit
V
6.0
0.1
1.0
1.0
6.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
fmax
2.0
3.0
4.5
6.0
10
15
30
50
9
14
28
45
8
12
25
40
MHz
tPLH,
tPHL
2.0
3.0
4.5
6.0
70
40
24
20
80
45
30
26
90
50
36
31
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
100
56
34
20
105
70
45
38
180
100
55
48
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
130
80
44
37
150
105
55
47
180
130
70
58
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
160
110
52
44
250
185
65
55
300
210
82
65
ns
tPHL
2.0
3.0
4.5
6.0
80
48
30
26
95
65
38
33
110
75
50
43
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
Cin
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
35
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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238
MC74HC393A
v
v
Guaranteed Limit
VCC
V
55 to
25_C
2.0
3.0
4.5
6.0
tw
tw
Symbol
trec
tr, tf
85_C
125_C
25
15
10
9
30
20
13
11
40
30
15
13
ns
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
Parameter
Unit
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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239
MC74HC393A
PIN DESCRIPTIONS
INPUTS
Clock (Pins 1, 13)
OUTPUTS
Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)
CONTROL INPUTS
Reset (Pins 2, 12)
CLOCK
tf
90%
50%
10%
tr
tw
VCC
50%
GND
GND
tw
tPHL
1/fmax
tPLH
tPHL
VCC
RESET
50%
90%
50%
10%
trec
VCC
50%
CLOCK
tTLH
GND
tTHL
Figure 1.
Figure 2.
EXPANDED LOGIC DIAGRAM
TEST
POINT
CLOCK
OUTPUT
DEVICE
UNDER
TEST
1, 13
C
D
Q
Q
3, 11
Q1
CL*
C
D
Q
Q
4, 10
Q2
C
D
RESET
2, 12
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240
Q
5, 9
Q3
Q
Q
6, 8
Q4
MC74HC393A
TIMING DIAGRAM
10
11
12
CLOCK
RESET
Q1
Q2
Q3
Q4
COUNT SEQUENCE
Outputs
Count
Q4
Q3
Q2
Q1
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
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241
13
14
15
MC74HC540A
Octal 3-State Inverting
Buffer/Line Driver/Line
Receiver
HighPerformance SiliconGate CMOS
The MC74HC540A is identical in pinout to the LS540. The device
inputs are compatible with Standard CMOS outputs. External pullup
resistors make them compatible with LSTTL outputs.
The HC540A is an octal inverting buffer/line driver/line receiver
designed to be used with 3state memory address drivers, clock
drivers, and other busoriented systems. This device features inputs
and outputs on opposite sides of the package and two ANDed
activelow output enables.
The HC540A is similar in function to the HC541A, which has
noninverting outputs.
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
1
20
SOIC WIDE20
DW SUFFIX
CASE 751D
20
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
A2
A3
Data
Inputs
A4
A5
A6
A7
A8
Output
Enables
OE1
OE2
HC540A
AWLYYWW
1
A
WL
YY
WW
LOGIC DIAGRAM
A1
MC74HC540AN
AWLYYWW
18
17
16
15
14
13
12
11
Y1
MC74HC540AN
Y2
Package
Shipping
PDIP20
1440 / Box
MC74HC540ADW
SOICWIDE
38 / Rail
MC74HC540ADWR2
SOICWIDE
1000 / Reel
Y3
Y4
Inverting
Outputs
Y5
Y6
Y7
Y8
1
PIN 20 = VCC
PIN 10 = GND
19
FUNCTION TABLE
Inputs
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
20
19
18
17
16
15
14
13
12
11
10
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
Output Y
OE1
OE2
L
L
H
X
L
L
X
H
L
H
X
X
H
L
Z
Z
Z = High Impedance
X = Dont Care
Semiconductor Components Industries, LLC, 1999
VCC
242
MC74HC540A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
mW
Tstg
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
TA
tr, tf
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
Vout = 0.1V
|Iout| 20A
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
Vin = VIL
|Iout| 20A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
6.0
0.1
1.0
1.0
VOH
|Iout| 3.6mA
|Iout| 6.0mA
|Iout| 7.8mA
Vin = VIL
VOL
Vin = VIH
|Iout| 20A
|Iout| 3.6mA
|Iout| 6.0mA
|Iout| 7.8mA
Vin = VIH
Iin
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243
MC74HC540A
DC CHARACTERISTICS (Voltages Referenced to GND)
Parameter
Symbol
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
IOZ
6.0
0.5
5.0
10.0
ICC
6.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Parameter
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
20
120
55
28
25
ns
tPLZ,
tPHZ
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tPZL,
tPZH
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
10
10
10
pF
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V, VEE = 0 V
CPD
pF
35
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
VCC
tf
tr
OE1 or OE2
VCC
90%
INPUT A
50%
50%
GND
50%
tPZL tPLZ
10%
tPHL
OUTPUT Y
tPLH
50%
10%
90%
10%
OUTPUT Y
tTLH
tTHL
VOL
tPZH tPHZ
50%
OUTPUT Y
HIGH
IMPEDANCE
GND
90%
VOH
50%
HIGH
IMPEDANCE
Figure 1.
Figure 2.
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244
MC74HC540A
TEST CIRCUITS
TEST
POINT
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
1k
CL*
Figure 3.
Figure 4.
PIN DESCRIPTIONS
INPUTS
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) Device outputs. Depending upon the state of
the output enable pins, these outputs are either inverting
outputs or highimpedance outputs.
CONTROLS
LOGIC DETAIL
To 7 Other
Inverters
VCC
One of Eight
Inverters
INPUT A
OUTPUT Y
OE1
OE2
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245
MC74HC541A
Octal 3-State Non-Inverting
Buffer/Line Driver/
Line Receiver
HighPerformance SiliconGate CMOS
The MC74HC541A is identical in pinout to the LS541. The device
inputs are compatible with Standard CMOS outputs. External pullup
resistors make them compatible with LSTTL outputs.
The HC541A is an octal noninverting buffer/line driver/line
receiver designed to be used with 3state memory address drivers,
clock drivers, and other busoriented systems. This device features
inputs and outputs on opposite sides of the package and two ANDed
activelow output enables.
The HC541A is similar in function to the HC540A, which has
inverting outputs.
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
1
20
SOIC WIDE20
DW SUFFIX
CASE 751D
20
A
WL
YY
WW
A2
A3
Data
Inputs
A4
A5
A6
A7
A8
Output
Enables
OE1
OE2
18
17
16
15
14
13
12
11
Y1
Y2
Y3
Y4
NonInverting
Outputs
FUNCTION TABLE
Output Y
OE1
OE2
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
Z = High Impedance
X = Dont Care
Y5
Y6
ORDERING INFORMATION
Y7
Device
MC74HC541AN
Y8
PIN 20 = VCC
PIN 10 = GND
19
= Assembly Location
= Wafer Lot
= Year
= Work Week
Inputs
HC541A
AWLYYWW
1
LOGIC DIAGRAM
A1
MC74HC541AN
AWLYYWW
Package
Shipping
PDIP20
1440 / Box
MC74HC541ADW
SOICWIDE
38 / Rail
MC74HC541ADWR2
SOICWIDE
1000 / Reel
OE2
19
Y1
18
Y2
17
Y3
16
Y4
15
Y5
14
Y6
13
Y7
12
Y8
11
10
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
246
MC74HC541A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
mW
Tstg
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
TA
tr, tf
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
Vout = 0.1V
|Iout| 20A
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
Vin = VIL
|Iout| 20A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
6.0
0.1
1.0
1.0
VOH
|Iout| 3.6mA
|Iout| 6.0mA
|Iout| 7.8mA
Vin = VIL
VOL
Vin = VIH
|Iout| 20A
|Iout| 3.6mA
|Iout| 6.0mA
|Iout| 7.8mA
Vin = VIH
Iin
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247
MC74HC541A
DC CHARACTERISTICS (Voltages Referenced to GND)
Parameter
Symbol
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
IOZ
6.0
0.5
5.0
10.0
ICC
6.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Parameter
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
tPLH,
tPHL
2.0
3.0
4.5
6.0
80
30
18
15
100
40
23
20
120
55
28
25
ns
tPLZ,
tPHZ
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tPZL,
tPZH
2.0
3.0
4.5
6.0
110
45
25
21
140
60
31
26
165
75
38
31
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
60
22
12
10
75
28
15
13
90
34
18
15
ns
10
10
10
pF
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V, VEE = 0 V
CPD
pF
35
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
VCC
tf
tr
VCC
90%
INPUT A
OE1 or OE2
50%
50%
GND
50%
tPZL tPLZ
10%
tPLH
tPHL
OUTPUT Y
50%
90%
10%
VOL
90%
VOH
tPZH tPHZ
50%
OUTPUT Y
HIGH
IMPEDANCE
GND
10%
OUTPUT Y
tTHL
tTLH
50%
HIGH
IMPEDANCE
Figure 1.
Figure 2.
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248
MC74HC541A
TEST CIRCUITS
TEST
POINT
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
DEVICE
UNDER
TEST
CL*
1k
OUTPUT
CL*
Figure 3.
Figure 4.
PIN DESCRIPTIONS
INPUTS
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) Device outputs. Depending upon the state of
the output enable pins, these outputs are either
noninverting outputs or highimpedance outputs.
CONTROLS
LOGIC DETAIL
To 7 Other
Buffers
VCC
One of Eight
Buffers
INPUT A
OUTPUT Y
OE1
OE2
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249
MC74HCT541A
Octal 3-State Non-Inverting
Buffer/Line Driver/
Line Receiver With
LSTTL-Compatible Inputs
HighPerformance SiliconGate CMOS
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
1
20
SOIC WIDE20
DW SUFFIX
CASE 751D
20
MC74HCT541AN
AWLYYWW
HCT541A
AWLYYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
LOGIC DIAGRAM
A1
A2
A3
Data
Inputs
A4
A5
A6
A7
A8
Output
Enables
OE1
OE2
Device
18
17
16
15
14
13
12
11
MC74HCT541AN
Y1
MC74HCT541ADW
Shipping
1440 / Box
SOICWIDE
MC74HCT541ADWR2 SOICWIDE
Y2
38 / Rail
1000 / Reel
FUNCTION TABLE
Y3
Y4
Inputs
NonInverting
Outputs
Y5
Y6
Output Y
OE1
OE2
L
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
Z = High Impedance
X = Dont Care
Y7
1
19
Package
PDIP20
VCC
20
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
19
18
17
16
15
14
13
12
11
10
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
PIN 20 = VCC
PIN 10 = GND
250
MC74HCT541A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
mW
Tstg
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
TA
tr, tf
VCC
55
+ 125
_C
500
ns
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
4.5
3.98
3.84
3.70
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.40
VOH
|Iout| 6.0mA
Iin
5.5
0.1
1.0
1.0
IOZ
5.5
0.5
5.0
10.0
ICC
5.5
40
160
ICC
5.5
55C
25 to 125C
2.9
2.4
1. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Total Supply Current = ICC + ICC.
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251
mA
MC74HCT541A
AC CHARACTERISTICS (VCC = 5.0V, CL = 50 pF, Input tr = tf = 6 ns)
Guaranteed Limit
Symbol
Parameter
55 to 25C
85C
125C
Unit
tPLH,
tPHL
23
28
32
ns
tPLZ,
tPHZ
30
34
38
ns
tPZL,
tPZH
30
34
38
ns
tTLH,
tTHL
12
15
18
ns
Cin
10
10
10
pF
Cout
15
15
15
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
55
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
3.0V
tf
tr
OE1 or OE2
3.0V
90%
INPUT A
1.3V
1.3V
GND
1.3V
tPZL tPLZ
10%
HIGH
IMPEDANCE
GND
tPLH
OUTPUT Y
tPHL
1.3V
10%
90%
OUTPUT Y
VOL
tPZH tPHZ
1.3V
10%
90%
OUTPUT Y
tTHL
tTLH
VOH
1.3V
HIGH
IMPEDANCE
Figure 1.
Figure 2.
TEST CIRCUITS
TEST
POINT
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
CL*
DEVICE
UNDER
TEST
1k
CL*
Figure 3.
Figure 4.
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252
MC74HCT541A
PIN DESCRIPTIONS
INPUTS
OUTPUTS
Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 (PINS 18, 17, 16, 15, 14,
13, 12, 11) Device outputs. Depending upon the state of
the output enable pins, these outputs are either
noninverting outputs or highimpedance outputs.
CONTROLS
LOGIC DETAIL
To 7 Other
Buffers
VCC
One of Eight
Buffers
INPUT A
OUTPUT Y
OE1
OE2
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253
MC74HC573A
Octal 3-State Noninverting
Transparent Latch
HighPerformance SiliconGate CMOS
The MC74HC573A is identical in pinout to the LS573. The devices
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold time becomes latched.
The HC573A is identical in function to the HC373A but has the data
inputs on the opposite side of the package from the outputs to facilitate
PC board layout.
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
MC74HC573AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HC573A
AWLYYWW
1
20
HC
573A
ALYW
TSSOP20
DT SUFFIX
CASE 948G
20
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC74HC573AN
254
Package
Shipping
PDIP20
1440 / Box
MC74HC573ADW
SOICWIDE
38 / Rail
MC74HC573ADWR2
SOICWIDE
1000 / Reel
MC74HC573ADT
TSSOP20
75 / Rail
MC74HC573ADTR2
TSSOP20
2500 / Reel
MC74HC573A
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
LATCH ENABLE
OUTPUT ENABLE
19
18
17
16
15
14
13
12
PIN ASSIGNMENT
OUTPUT
ENABLE
D0
Q0
Q1
Q2
Latch
Enable
L
H
L
H
L
L
H
X
X = Dont Care
Z = High Impedance
Q0
D1
18
Q1
17
Q2
16
Q3
Q5
D4
15
Q4
Q6
D5
14
Q5
Q7
D6
13
Q6
D7
12
10
11
Q7
LATCH
ENABLE
Q4
H
L
X
X
H
L
No Change
Z
GND
Value
Units
54.5
ea.
1.5
ns
5.0
0.0075
pJ
19
Output
Design Criteria
PIN 20 = VCC
PIN 10 = GND
Inputs
VCC
D2
NONINVERTING
OUTPUTS
FUNCTION TABLE
Output
Enable
20
D3
Q3
11
1
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255
MC74HC573A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
18
0.5
0.9
1.35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
VOH
|Iout| 2.4mA
|Iout|
6.0 mA
|Iout|
7.8 mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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256
MC74HC573A
v
v
v
v
Guaranteed Limit
Symbol
VOL
Parameter
Test Conditions
|Iout| 2.4mA
|Iout|
6.0 mA
|Iout|
7.8 mA
VCC
V
55 to
25_C
2.0
4.5
6.0
85_C
125_C
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Unit
V
6.0
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
6.0
0.5
5.0
10
ICC
6.0
4.0
40
160
Iin
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
VCC
V
55 to
25_C
85_C
125_C
tPLH,
tPHL
2.0
3.0
4.5
6.0
150
100
30
26
190
140
38
33
225
180
45
38
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
160
105
32
27
200
145
40
34
240
190
48
41
ns
tPLZ,
tPHZ
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL,
tPZH
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
60
27
12
10
75
32
15
13
90
36
18
15
ns
10
10
10
pF
15
15
15
pF
Symbol
Cin
Cout
Parameter
Unit
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
23
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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257
MC74HC573A
v
v
Guaranteed Limit
Symbol
Parameter
Fig.
VCC
Volts
55 to 25_C
Min
Max
85_C
Min
Max
125_C
Min
Max
Unit
tsu
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
th
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
tw
2.0
3.0
4.5
6.0
75
60
15
13
95
80
19
16
110
90
22
19
ns
tr, tf
2.0
3.0
4.5
6.0
http://onsemi.com
258
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
MC74HC573A
SWITCHING WAVEFORMS
VCC
tr
LATCH
ENABLE
tf
VCC
90%
50%
10%
INPUT D
50%
GND
tw
GND
tPLH
tPHL
90%
50%
10%
tPLH
tTHL
tTLH
50%
Figure 1.
OUTPUT
ENABLE
Figure 2.
3.0 V
VALID
50%
GND
tPZL
10%
tPHZ
90%
Q
GND
HIGH
IMPEDANCE
50%
1.3 V
tSU
VOL
VOH
th
VCC
50%
LATCH
ENABLE
GND
HIGH
IMPEDANCE
Figure 3.
Figure 4.
TEST POINT
D0
OUTPUT
DEVICE
UNDER
TEST
D1
CL*
D2
*Includes all probe and jig capacitance
D3
D5
TEST POINT
OUTPUT
VCC
50%
INPUT D
tPLZ
tPZH
DEVICE
UNDER
TEST
tPHL
1 k
CL*
D6
D7
LATCH ENABLE
OUTPUT ENABLE
http://onsemi.com
259
11
D
Q
LE
19
D
Q
LE
18
D
Q
LE
17
D
Q
LE
16
D
Q
LE
15
D
Q
LE
14
D
Q
LE
13
D
Q
LE
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MC74HCT573A
Octal 3-State Noninverting
Transparent Latch with
LSTTL Compatible Inputs
HighPerformance SiliconGate CMOS
The MC74HCT573A is identical in pinout to the LS573. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to HighSpeed CMOS inputs.
These latches appear transparent to data (i.e., the outputs change
asynchronously) when Latch Enable is high. When Latch Enable goes
low, data meeting the setup and hold times becomes latched.
The Output Enable input does not affect the state of the latches, but
when Output Enable is high, all device outputs are forced to the
highimpedance state. Thus, data may be latched even when the
outputs are not enabled.
The HCT573A is identical in function to the HCT373A but has the
Data Inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
MC74HCT573AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HCT573A
AWLYYWW
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
MC74HCT573AN
MC74HCT573ADW
Package
Shipping
PDIP20
1440 / Box
SOICWIDE
38 / Rail
MC74HCT573ADWR2 SOICWIDE
260
HCT
573A
ALYW
TSSOP20
DT SUFFIX
CASE 948G
20
Device
20
1000 / Reel
MC74HCT573ADT
TSSOP20
75 / Rail
MC74HCT573ADTR2
TSSOP20
2500 / Reel
MC74HCT573A
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
19
18
17
16
15
14
13
12
PIN ASSIGNMENT
OUTPUT
ENABLE
D0
Q0
Q1
Q2
NONINVERTING
OUTPUTS
Q3
Q4
Q5
Q6
Q7
11
LATCH ENABLE
PIN 20 = VCC
PIN 10 = GND
OUTPUT ENABLE
Inputs
Output
Latch
Enable
L
L
L
H
H
H
L
X
H
L
X
X
H
L
No Change
Z
X = Dont Care
Z = High Impedance
Design Criteria
Value
Units
58.5
ea
1.5
ns
5.0
0.0075
pJ
20
VCC
19
Q0
D1
18
Q1
D2
17
Q2
D3
16
Q3
D4
15
Q4
D5
14
Q5
D6
13
Q6
D7
12
10
11
Q7
LATCH
ENABLE
GND
FUNCTION TABLE
Output
Enable
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261
MC74HCT573A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
TA
tr, tf
Min
Max
Unit
4.5
5.5
VCC
55
+ 125
_C
500
ns
Guaranteed Limit
VCC
V
55 to
25_C
85_C
125_C
VIH
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
4.5
3.98
3.84
3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.4
5.5
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage Current
5.5
0.5
5.0
10
ICC
5.5
4.0
40
160
ICC
Symbol
VOH
VOL
Iin
Parameter
Test Conditions
5.5
55_C
25_C to 125_C
2.9
2.4
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
http://onsemi.com
262
Unit
mA
MC74HCT573A
v
v
Guaranteed Limit
Symbol
55 to
25_C
Parameter
85_C
125_C
Unit
tPLH,
tPHL
30
38
45
ns
tPLH
tPHL
30
38
45
ns
TPLZ,
TPHZ
28
35
42
ns
tTZL,
tTZH
28
35
42
ns
tTLH,
tTHL
12
15
18
ns
10
10
10
pF
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
48
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Guaranteed Limit
55 to 25_C
Symbol
Parameter
Fig.
Min
Max
85_C
Min
Max
125_C
Min
Max
Unit
tsu
10
13
15
ns
th
5.0
5.0
5.0
ns
tw
15
19
22
ns
tr, tf
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263
500
500
500
ns
MC74HCT573A
SWITCHING WAVEFORMS
3.0 V
tr
LATCH
ENABLE
tf
3.0 V
2.7 V
1.3 V
0.3 V
INPUT D
1.3 V
GND
tw
GND
tPLH
tPHL
90%
1.3 V
10%
tPLH
tTHL
tTLH
1.3 V
Figure 1.
OUTPUT
ENABLE
Figure 2.
3.0 V
VALID
1.3 V
GND
tPZL
10%
tPHZ
90%
Q
GND
HIGH
IMPEDANCE
1.3 V
1.3 V
tSU
VOL
VOH
th
3.0 V
1.3 V
LATCH
ENABLE
GND
HIGH
IMPEDANCE
Figure 3.
Figure 4.
TEST POINT
D0
OUTPUT
DEVICE
UNDER
TEST
D1
CL*
D2
*Includes all probe and jig capacitance
D3
D5
TEST POINT
OUTPUT
3.0 V
1.3 V
INPUT D
tPLZ
tPZH
DEVICE
UNDER
TEST
tPHL
1 k
CL*
D6
D7
LATCH ENABLE
11
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264
D
Q
LE
19
D
Q
LE
18
D
Q
LE
17
D
Q
LE
16
D
Q
LE
15
D
Q
LE
14
D
Q
LE
13
D
Q
LE
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MC74HC574A
Octal 3-State Noninverting
D Flip-Flop
HighPerformance SiliconGate CMOS
The MC74HC574A is identical in pinout to the LS574. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The Output Enable input does not affect the states
of the flipflops, but when Output Enable is high, all device outputs
are forced to the highimpedance state. Thus, data may be stored even
when the outputs are not enabled.
The HC574A is identical in function to the HC374A but has the
flipflop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
MC74HC574AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HC574A
AWLYYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC74HC574AN
265
Package
Shipping
PDIP20
1440 / Box
MC74HC574ADW
SOICWIDE
38 / Rail
MC74HC574ADWR2
SOICWIDE
1000 / Reel
MC74HC574A
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
19
18
17
16
15
14
13
12
PIN ASSIGNMENT
OUTPUT
ENABLE
D0
20
VCC
19
Q0
D1
18
Q1
D2
17
Q2
D3
16
Q3
Q6
D4
15
Q4
Q7
D5
14
Q5
D6
13
Q6
D7
12
Q7
10
11
CLOCK
Q0
Q1
Q2
Q3
Q4
NON
INVERTING
OUTPUTS
Q5
11
PIN 20 = VCC
PIN 10 = GND
GND
FUNCTION TABLE
Inputs
OE
L
L
L
H
Output
Clock
L,H,
X
H
L
X
X
H
L
No Change
Z
X = Dont Care
Z = High Impedance
Design Criteria
Value
Units
66.5
ea
1.5
ns
5.0
0.0075
pJ
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266
MC74HC574A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
Vout = 0.1 V
|Iout|
20 A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
Vin = VIH
|Iout|
20 A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
6.0
0.1
1.0
1.0
VOH
Vin = VIH
VOL
2.4 mA
6.0 mA
7.8 mA
Vin = VIL
|Iout|
20 A
Vin = VIL
Iin
|Iout|
|Iout|
|Iout|
|Iout|
|Iout|
|Iout|
2.4 mA
6.0 mA
7.8 mA
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267
MC74HC574A
v
v
v
v
v
v
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
IOZ
Maximum ThreeState
Leakage Current
6.0
0.5
5.0
10
ICC
6.0
4.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
IOZ
Maximum ThreeState
Leakage Current
6.0
0.5
5.0
10
ICC
6.0
4.0
40
160
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
fmax
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
24
MHz
tPLH,
tPHL
2.0
3.0
4.5
6.0
160
105
32
27
200
145
40
34
240
190
48
41
ns
tPLZ,
tPHZ
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL,
tPZH
2.0
3.0
4.5
60
140
90
28
24
175
120
35
30
210
140
42
36
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
60
27
12
10
75
32
15
13
90
36
18
15
ns
10
10
10
pF
15
15
15
pF
Cin
Cout
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
24
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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268
MC74HC574A
v
v
Guaranteed Limit
Symbol
Parameter
Fig.
VCC
Volts
55 to 25_C
Min
Max
85_C
Min
Max
125_C
Min
Max
Unit
tsu
2.0
3.0
4.6
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
th
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
tw
2.0
3.0
4.5
6.0
75
60
15
13
95
80
19
16
110
90
22
19
ns
2.0
3.0
4.5
6.0
tr, tf
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269
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
MC74HC574A
SWITCHING WAVEFORMS
tr
tf
3.0 V
VCC
90%
50%
10%
tw
CLOCK
1.3 V
GND
GND
tPZL
1/fmax
tPLH
tPHL
HIGH
IMPEDANCE
1.3 V
tPZH
90%
50%
10%
tPLZ
tPHZ
10%
VOL
90%
VOH
Q
tTLH
HIGH
IMPEDANCE
tTHL
Figure 1.
Figure 2.
VALID
VCC
DATA
50%
GND
tsu
D0
th
C
Q
D
19
C
Q
D
18
C
Q
D
17
C
Q
D
16
C
Q
D
15
C
Q
D
14
C
Q
D
13
C
Q
D
12
Q0
VCC
CLOCK
50%
GND
D1
Figure 3.
D2
TEST POINT
D3
Q1
Q2
Q3
OUTPUT
DEVICE
UNDER
TEST
D4
CL*
D5
*Includes all probe and jig capacitance
D6
Figure 4.
D7
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
1 k
CL*
CLOCK
OUTPUT ENABLE
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270
11
1
Q4
Q5
Q6
Q7
MC74HCT574A
Octal 3-State Noninverting
D Flip-Flop with
LSTTL-Compatible Inputs
HighPerformance SiliconGate CMOS
The MC74HCT574A is identical in pinout to the LS574. This
device may be used as a level converter for interfacing TTL or NMOS
outputs to High Speed CMOS inputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the Clock. The Output Enable input does not affect the states
of the flipflops, but when Output Enable is high, all device outputs
are forced to the highimpedance state. Thus, data may be stored even
when the outputs are not enabled.
The HCT574A is identical in function to the HCT374A but has the
flipflop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
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MARKING
DIAGRAMS
20
PDIP20
P SUFFIX
CASE 738
20
MC74HCT574AN
AWLYYWW
1
20
20
1
SOIC WIDE20
DW SUFFIX
CASE 751D
HCT574A
AWLYYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Device
MC74HCT574AN
MC74HCT574ADW
Package
Shipping
PDIP20
1440 / Box
SOICWIDE
MC74HCT574ADWR2 SOICWIDE
271
38 / Rail
1000 / Reel
MC74HCT574A
LOGIC DIAGRAM
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
19
18
17
16
15
14
13
12
PIN ASSIGNMENT
Q0
Q1
Q2
Q3
Q4
NON
INVERTING
OUTPUTS
Q5
Q6
Q7
11
OUTPUT ENABLE
PIN 20 = VCC
PIN 10 = GND
Inputs
L
L
L
H
Output
Clock
L,H,
X
H
L
X
X
H
L
No Change
Z
X = dont care
Z = high impedance
Design Criteria
Value
Units
71.5
ea
1.5
ns
5.0
0.0075
pJ
20
VCC
19
Q0
D1
18
Q1
D2
17
Q2
D3
16
Q3
D4
15
Q4
D5
14
Q5
D6
13
Q6
D7
12
Q7
10
11
CLOCK
GND
FUNCTION TABLE
OE
OUTPUT
ENABLE
D0
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272
MC74HCT574A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
VCC
55
+ 125
_C
500
ns
TA
tr, tf
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
VIL
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
4.5
3.98
3.84
3.7
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.4
5.5
0.1
1.0
1.0
5.5
4.0
40
160
VOH
VOL
Iin
ICC
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273
MC74HCT574A
v
v
v
v
Guaranteed Limit
Symbol
IOZ
ICC
Parameter
Test Conditions
Maximum ThreeState
Leakage
Current
VCC
V
55 to
25_C
5.5
0.5
85_C
125_C
5.0
10
55_C
25_C to 125_C
2.9
2.4
5.5
Unit
A
mA
Guaranteed Limit
Symbol
55 to
25_C
Parameter
85_C
125_C
Unit
fMAX
30
24
20
MHz
tPLH,
tPHL
30
38
45
ns
tPLZ,
tPHZ
28
35
42
ns
tPZH,
tPZL
28
35
42
ns
tTLH,
12
15
18
ns
10
10
10
pF
tTHL
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
58
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Guaranteed Limit
55 to 25_C
Fig.
Min
10
13
15
ns
th
5.0
5.0
5.0
ns
tw
15
19
22
ns
tr, If
Parameter
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274
500
Min
Max
125_C
tsu
Symbol
Max
85_C
500
Min
Max
500
Unit
ns
MC74HCT574A
EXPANDED LOGIC DIAGRAM
D0
2
CLOCK
D1
3
D3
5
D4
6
D5
7
D6
8
D7
9
11
D
Q
ENABLE
OUTPUT
D2
4
19
Q0
18
17
Q1
16
Q2
15
Q3
14
Q4
13
Q5
12
Q6
Q7
SWITCHING WAVEFORMS
tr
CLOCK
tf
3.0 V
3.0 V
2.7 V
1.3 V
0.3 V
tw
OUTPUT
ENABLE
GND
1.3 V
GND
tPZL
1/fmax
tPLH
Q
tPZH
Q
tTLH
HIGH
IMPEDANCE
1.3 V
tPHL
90%
1.3 V
10%
tPLZ
tPHZ
10%
VOL
90%
VOH
1.3 V
HIGH
IMPEDANCE
tTHL
Figure 1.
Figure 2.
TEST POINT
VALID
OUTPUT
3.0 V
DEVICE
UNDER
TEST
1.3 V
DATA
GND
tsu
th
CL*
3.0 V
1.3 V
GND
CLOCK
Figure 3.
1 k
CL*
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275
MC74HC589A
8-Bit Serial or
Parallel-Input/Serial-Output
Shift Register with 3-State
Output
HighPerformance SiliconGate CMOS
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MARKING
DIAGRAMS
16
16
SA
MC74HC589AN
AWLYYWW
1
16
SO16
D SUFFIX
CASE 751B
16
HC589A
AWLYWW
1
16
HC
589A
ALYW
TSSOP16
DT SUFFIX
CASE 948F
16
1
1
A
WL
YY
WW
LOGIC DIAGRAM
SERIAL
DATA
INPUT
PDIP16
N SUFFIX
CASE 648
14
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
A
B
PARALLEL
DATA
INPUTS
C
D
E
F
G
H
LATCH CLOCK
SHIFT CLOCK
SERIAL SHIFT/
PARALLEL LOAD
OUTPUT ENABLE
15
16
15
14
13
12
SA
SERIAL SHIFT/
PARALLEL LOAD
LATCH CLOCK
11
SHIFT CLOCK
10
OUTPUT ENABLE
GND
1
2
VCC = PIN 16
GND = PIN 8
3
4
5
DATA
LATCH
SHIFT
REGISTER
6
7
12
SERIAL
DATA
QH
OUTPUT
VCC
A
QH
11
13
ORDERING INFORMATION
10
Device
276
Package
Shipping
MC74HC589AN
PDIP16
2000 / Box
MC74HC589AD
SOIC16
48 / Rail
MC74HC589ADR2
SOIC16
2500 / Reel
MC74HC589ADT
TSSOP16
96 / Rail
MC74HC589ADTR2
TSSOP16
2500 / Reel
MC74HC589A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
TBD
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
6.0
0.1
1.0
1.0
VOH
VOL
Vin = VIH
|Iout|
20 A
Iin
2.4 mA
6.0 mA
7.8 mA
2.4 mA
6.0 mA
7.8 mA
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277
MC74HC589A
v
v
v
v
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
IOZ
Maximum ThreeState
Leakage Current
6.0
0.5
5.0
10
ICC
6.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
fmax
2.0
3.0
4.5
6.0
6.0
TBD
30
35
4.8
TBD
24
28
4.0
TBD
20
24
MHz
tPLH,
tPHL
2.0
3.0
4.5
6.0
175
100
40
30
225
110
50
40
275
125
60
50
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
160
90
30
25
200
130
40
30
240
160
48
40
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
160
90
30
25
200
130
40
30
240
160
48
40
ns
tPLZ,
tPHZ
2.0
3.0
4.5
6.0
150
80
27
23
170
100
30
25
200
130
40
30
ns
tPZL,
tPZH
2.0
3.0
4.5
6.0
150
80
27
23
170
100
30
25
200
130
40
30
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
60
TBD
12
10
75
TBD
15
13
90
TBD
18
15
ns
Cin
Cout
10
10
10
pF
15
15
15
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
50
CPD
Power Dissipation Capacitance (Per Package)*
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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278
MC74HC589A
v
v
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tsu
2.0
3.0
4.5
6.0
100
TBD
20
17
125
TBD
25
21
150
TBD
30
26
ns
tsu
2.0
3.0
4.5
6.0
100
TBD
20
17
125
TBD
25
21
150
TBD
30
26
ns
tsu
2.0
3.0
4.5
6.0
100
TBD
20
17
125
TBD
25
21
150
TBD
30
26
ns
th
2.0
3.0
4.5
6.0
25
TBD
5
5
30
TBD
6
6
40
TBD
8
7
ns
th
2.0
3.0
4.5
6.0
5
5
5
5
5
5
5
5
5
5
5
5
ns
tw
2.0
3.0
4.5
6.0
75
TBD
15
13
95
TBD
19
16
110
TBD
23
19
ns
tw
2.0
3.0
4.5
6.0
80
TBD
16
14
100
TBD
20
17
120
TBD
24
20
ns
tw
2.0
3.0
4.5
6.0
80
TBD
16
14
100
TBD
20
17
120
TBD
24
20
ns
2.0
3.0
4.5
6.0
1000
TBD
500
400
1000
TBD
500
400
1000
TBD
500
400
ns
tr, tf
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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279
MC74HC589A
FUNCTION TABLE
Inputs
Resulting Function
Output
Enable
Serial Shift/
Parallel Load
Latch
Clock
Shift
Clock
Serial
Input
SA
Parallel
Inputs
AH
Data
Latch
Contents
Shift
Register
Contents
Output
QH
L, H,
ah
ah
L, H,
L, H,
L, H,
ah
ah
ah
SRA = D,
SRN
SRN+1
SRG
SRH
ah
ah
SRA = D,
SRN
SRN+1
SRG
SRH
Operation
U = remains unchanged
X = dont care
Z = high impedance
* = depends on Latch Clock input
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280
LRN
SRN
LRH
MC74HC589A
SWITCHING WAVEFORMS
tr
LATCH CLOCK
tf
1/fmax
VCC
90%
50%
10%
tw
tw
GND
SHIFT CLOCK
GND
tPLH
tPHL
tPLH
90%
50%
10%
QH
VCC
50%
QH
tTLH
tPHL
50%
tTHL
VCC
OUTPUT
ENABLE
50%
GND
tPZL
tPLZ
HIGH
IMPEDANCE
50%
QH
tPZH
QH
tw
tPHZ
50%
10%
VOL
90%
VOH
SERIAL SHIFT/
PARALLEL LOAD
QH
VCC
50%
50%
tPLH
tPHL
GND
50%
HIGH
IMPEDANCE
Figure 3.
Figure 4.
DATA VALID
AH
DATA VALID
VCC
SA
50%
VCC
50%
GND
tsu
LATCH CLOCK
GND
th
tsu
th
SHIFT CLOCK
50%
Figure 5.
50%
Figure 6.
TEST POINT
SERIAL SHIFT/
PARALLEL LOAD
OUTPUT
VCC
DEVICE
UNDER
TEST
50%
GND
tsu
SHIFT CLOCK
CL*
50%
*Includes all probe and jig capacitance
Figure 7.
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281
MC74HC589A
TEST CIRCUIT
TEST POINT
DEVICE
UNDER
TEST
1 k
OUTPUT
CL*
Figure 9.
PIN DESCRIPTIONS
DATA INPUTS
A, B, C, D, E, F, G, H (Pins 15, 1, 2, 3, 4, 5, 6, 7)
SA (Pin 14)
Serial data input. Data on this input is shifted into the shift
register on the rising edge of the Shift Clock input if Serial
Shift/Parallel Load is high. Data on this input is ignored
when Serial Shift/Parallel Load is low.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 13)
OUTPUT
QH (Pin 9)
Serial data output. This pin is the output from the last stage
of the shift register. This is a 3state output.
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282
MC74HC589A
TIMING DIAGRAM
SHIFT CLOCK
SERIAL DATA
INPUT, SA
OUTPUT ENABLE
SERIAL SHIFT/
PARALLEL LOAD
LATCH CLOCK
PARALLEL
DATA
INPUTS
QH
HIGH IMPEDANCE
SERIAL SHIFT
RESET LATCH
LOAD LATCH PARALLEL LOAD
AND SHIFT REGISTER
SHIFT REGISTER
SERIAL SHIFT
LOAD LATCH
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283
SERIAL SHIFT
PARALLEL LOAD
SHIFT REGISTER
H H
SERIAL
SHIFT
MC74HC589A
LOGIC DETAIL
OUTPUT ENABLE
SA
SHIFT CLOCK
10
14
11
SERIAL SHIFT/ 13
PARALLEL LOAD
LATCH CLOCK
A
12
15
STAGE A
D
Q
C
S
C Q
R
STAGE B
B
Q
C
S
C Q
R
PARALLEL
DATA
INPUTS
STAGE C*
STAGE D*
STAGE E*
STAGE F*
STAGE G*
STAGE H
VCC
Q
C
S
C Q
R
*NOTE: Stages C thru G (not shown in detail) are identical to stages A and B above.
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284
QH
MC74HC595A
8-Bit Serial-Input/Serial or
Parallel-Output Shift
Register with Latched
3-State Outputs
HighPerformance SiliconGate CMOS
The MC74HC595A consists of an 8bit shift register and an 8bit
Dtype latch with threestate parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register also
provides parallel data to the 8bit latch. The shift register and latch
have independent clock inputs. This device also has an asynchronous
reset for the shift register.
The HC595A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
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MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
MC74HC595AN
AWLYYWW
1
16
SO16
D SUFFIX
CASE 751B
16
1
HC595A
AWLYWW
1
16
HC
595A
ALYW
TSSOP16
DT SUFFIX
CASE 948F
16
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
LOGIC DIAGRAM
SERIAL
DATA
INPUT
15
14
1
2
3
SHIFT
REGISTER
SHIFT 11
CLOCK
10
RESET
LATCH 12
CLOCK
OUTPUT 13
ENABLE
4
LATCH
QA
QB
QC
QD
PARALLEL
DATA
OUTPUTS
QE
5
QF
6
QG
7
QH
SERIAL
DATA
OUTPUT
SQH
VCC = PIN 16
GND = PIN 8
285
QB
16
VCC
QC
15
QA
QD
14
QE
13
OUTPUT ENABLE
QF
12
LATCH CLOCK
QG
11
SHIFT CLOCK
QH
10
RESET
GND
SQH
ORDERING INFORMATION
Package
Shipping
MC74HC595AN
Device
PDIP16
2000 / Box
MC74HC595AD
SOIC16
48 / Rail
MC74HC595ADR2
SOIC16
2500 / Reel
MC74HC595ADT
TSSOP16
96 / Rail
MC74HC595ADTR2
TSSOP16
2500 / Reel
MC74HC595A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
Vout
20
mA
Iout
35
mA
ICC
75
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
v
v
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
VOH
VOL
2.4 mA
6.0 mA
7.8 mA
2.4 mA
6.0 mA
7.8 mA
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286
MC74HC595A
v
v
vv
v
vv
v
v
Guaranteed Limit
Symbol
VOH
Parameter
Test Conditions
VOL
2.4 mA
4.0 mA
5.2 mA
2.4 mA
4.0 mA
5.2 mA
VCC
V
55 to
25_C
2.0
4.5
6.0
85_C
125_C
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.98
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
Unit
V
6.0
0.1
1.0
1.0
IOZ
Maximum ThreeState
Leakage
Current, QA QH
6.0
0.5
5.0
10
ICC
6.0
4.0
40
160
Iin
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
fmax
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
24
MHz
tPLH,
tPHL
2.0
3.0
4.5
6.0
140
100
28
24
175
125
35
30
210
150
42
36
ns
tPHL
2.0
3.0
4.5
6.0
145
100
29
25
180
125
36
31
220
150
44
38
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
140
100
28
24
175
125
35
30
210
150
42
36
ns
tPLZ,
tPHZ
2.0
3.0
4.5
6.0
150
100
30
26
190
125
38
33
225
150
45
38
ns
tPZL,
tPZH
2.0
3.0
4.5
6.0
135
90
27
23
170
110
34
29
205
130
41
35
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
31
18
15
ns
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287
MC74HC595A
v
v
Guaranteed Limit
Symbol
tTLH,
tTHL
Cin
Cout
VCC
V
55 to
25_C
2.0
3.0
4.5
6.0
Parameter
85_C
125_C
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
15
15
15
pF
Unit
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
300
pF
2
* Used to determine the noload dynamic power consumption: P D = C PD V CC f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
CPD
v
v
Guaranteed Limit
Symbol
Parameter
VCC
V
25_C to
55_C
85_C
125_C
Unit
tsu
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
tsu
2.0
3.0
4.5
6.0
75
60
15
13
95
70
19
16
110
80
22
19
ns
th
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
ns
trec
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
tw
2.0
3.0
4.5
6.0
60
45
12
10
75
60
15
13
90
70
18
15
ns
tw
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
tw
2.0
3.0
4.5
6.0
50
40
10
9.0
65
50
13
11
75
60
15
13
ns
tr, tf
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
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288
MC74HC595A
FUNCTION TABLE
Inputs
Resulting Function
Reset
Serial
Input
A
L, H,
L, H,
L, H,
L, H,
L, H,
L, H,
Operation
Shift
Clock
Latch
Clock
Output
Enable
Shift
Register
Contents
Latch
Register
Contents
SRA;
SRN+1
D
SRN
Serial
Output
SQH
L
SRG
SRN
**
Enabled
**
= LowtoHigh
= HightoLow
SRH
Parallel
Outputs
QA QH
U
SRN
LRN
PIN DESCRIPTIONS
INPUTS
A (Pin 14)
Serial Data Input. The data on this pin is shifted into the
8bit serial shift register.
CONTROL INPUTS
Shift Clock (Pin 11)
OUTPUTS
QA QH (Pins 15, 1, 2, 3, 4, 5, 6, 7)
SQH (Pin 9)
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289
MC74HC595A
SWITCHING WAVEFORMS
tr
SHIFT
CLOCK
tw
tf
VCC
VCC
90%
50%
10%
tw
RESET
GND
GND
tPHL
1/fmax
tPLH
OUTPUT
SQH
50%
50%
OUTPUT
SQH
tPHL
90%
50%
10%
trec
VCC
SHIFT
CLOCK
tTLH
50%
GND
tTHL
Figure 1.
LATCH
CLOCK
Figure 2.
OUTPUT
ENABLE
VCC
50%
VCC
50%
GND
GND
tPLH
tPHL
OUTPUT Q
OUTPUT Q
tTLH
10%
VOL
90%
VOH
HIGH
IMPEDANCE
tTHL
Figure 4.
VCC
SHIFT
CLOCK
VALID
VCC
50%
GND
50%
tsu
GND
SWITCH
CLOCK
tPHZ
50%
Figure 3.
tsu
HIGH
IMPEDANCE
50%
tPZH
90%
QAQH 50%
OUTPUTS 10%
SERIAL
INPUT A
tPLZ
tPZL
LATCH
CLOCK
th
VCC
50%
VCC
50%
GND
tw
GND
Figure 6.
Figure 5.
TEST CIRCUITS
TEST POINT
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
OUTPUT
DEVICE
UNDER
TEST
CL*
1 k
CL*
Figure 7.
Figure 8.
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290
MC74HC595A
EXPANDED LOGIC DIAGRAM
OUTPUT
ENABLE
13
LATCH
CLOCK
12
SERIAL
DATA
INPUT A
14
SRA
15
QA
LRA
R
Q
SRB
QB
LRB
R
Q
SRC
QC
LRC
R
Q
SRD
QD
LRD
PARALLEL
DATA
OUTPUTS
R
Q
SRE
QE
LRE
R
Q
SRF
QF
LRF
R
Q
SRG
QG
LRG
SHIFT
CLOCK
D
11
SRH
QH
LRH
RESET
10
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291
SERIAL
DATA
OUTPUT SQH
MC74HC595A
TIMING DIAGRAM
SHIFT
CLOCK
SERIAL DATA
INPUT A
RESET
LATCH
CLOCK
OUTPUT
ENABLE
QA
QB
QC
QD
QE
QF
QG
QH
SERIAL DATA
OUTPUT SQH
NOTE:
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292
MC74HC4020A
14-Stage Binary Ripple
Counter
HighPerformance SiliconGate CMOS
The MC74C4020A is identical in pinout to the standard CMOS
MC14020B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 14 masterslave flipflops with 12 stages
brought out to pins. The output of each flipflop feeds the next and the
frequency at each output is half of that of the preceding one. Reset is
asynchronous and activehigh.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with the Clock of the
HC4020A for some designs.
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MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
1
1
16
SO16
D SUFFIX
CASE 751B
16
1
16
1
A
WL
YY
WW
Q4
5
6
13
10
Clock
Q9
Q10
Q11
15
1
2
Q10
Q8
Q9
15
14
13
12
Q14
ORDERING INFORMATION
Device
Reset Clock
11
10
Q1
9
Q12
Q13
Q14
Q6
Q5
Q7
Q4
No Charge
Advance to Next State
All Outputs Are Low
Q13
Pin 16 = VCC
Pin 8 = GND
Q11
L
L
H
Output State
Q12
VCC
16
Reset
Q8
14
11
Clock
Q7
12
Reset
= Assembly Location
= Wafer Lot
= Year
= Work Week
FUNCTION TABLE
Q5
Q6
HC40
20A
ALYW
TSSOP16
DT SUFFIX
CASE 948F
16
Q1
HC4020A
AWLYWW
LOGIC DIAGRAM
9
MC74HC4020AN
AWLYYWW
Package
Shipping
MC74HC4020AN
PDIP16
2000 / Box
MC74HC4020AD
SOIC16
48 / Rail
MC74HC4020ADR2
SOIC16
2500 / Reel
MC74HC4020ADT
TSSOP16
96 / Rail
MC74HC4020ADTR2
TSSOP16
2500 / Reel
8
GND
293
MC74HC4020A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
0
1000
600
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
VOH
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
VOL
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294
MC74HC4020A
DC CHARACTERISTICS (Voltages Referenced to GND)
55 to 25C
85C
125C
Unit
Symbol
Parameter
Iin
6.0
0.1
1.0
1.0
6.0
40
160
ICC
Condition
Guaranteed Limit
VCC
V
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Parameter
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
fmax
2.0
3.0
4.5
6.0
10
15
30
50
9.0
14
28
50
8.0
12
25
40
MHz
tPLH,
tPHL
2.0
3.0
4.5
6.0
96
63
31
25
106
71
36
30
115
88
40
35
ns
tPHL
2.0
3.0
4.5
6.0
45
30
30
26
52
36
35
32
65
40
40
35
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
69
40
17
14
80
45
21
15
90
50
28
22
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
* For TA = 25C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n1)] ns
VCC = 4.5 V: tP = [30.25 + 14.6 (n1)] ns
VCC = 3.0 V: tP = [61.5 + 34.4 (n1)] ns
VCC = 6.0 V: tP = [24.4 + 12 (n1)] ns
Typical @ 25C, VCC = 5.0 V
CPD
38
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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295
MC74HC4020A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
2.0
3.0
4.5
6.0
30
20
5
4
40
25
8
6
50
30
12
9
ns
tw
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
tw
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
Symbol
trec
tr, tf
Parameter
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
Clock (Pin 10)
OUTPUTS
Q1, Q4Q14 (Pins 9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3)
SWITCHING WAVEFORMS
tf
tr
VCC
90%
50%
10%
Clock
Clock
VCC
trec
tw
GND
tw
1/fMAX
Reset
tPHL
tPLH
Q1
50%
90%
50%
10%
Any Q
tTHL
Figure 1.
50%
Figure 2.
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296
VCC
50%
tPHL
tTLH
GND
GND
MC74HC4020A
SWITCHING WAVEFORMS (continued)
TEST
POINT
VCC
Qn
OUTPUT
50%
DEVICE
UNDER
TEST
GND
tPLH
Qn+1
tPHL
CL*
50%
Figure 3.
Q1
Q4
Clock
10
Q12
Q13
Q14
R
Reset
Q5
11
Q6 = Pin 4
Q7 = Pin 6
Q8 = Pin 13
Q9 = Pin 12
Q10 = Pin 14
Q11 = Pin 15
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297
VCC = Pin 16
GND = Pin 8
MC74HC4020A
1
16
32
64
128
256
512
1024
2048
4096
8192
16384
Clock
Reset
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q12
Q13
Q14
APPLICATIONS INFORMATION
TimeBase Generator
VCC
1/6 of HC14A
1.0M
HC4020A
Clock
120Vac
60Hz
13
Q5
12
20pF
Q10
10
Q11
1/2
HC20
9
Q12
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298
1
2
4
5
1/2
HC20
1.0 Pulse/Minute
Output
MC74HC4040A
12-Stage Binary Ripple
Counter
HighPerformance SiliconGate CMOS
The MC74C4040A is identical in pinout to the standard CMOS
MC14040. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 12 masterslave flipflops. The output of
each flipflop feeds the next and the frequency at each output is half of
that of the preceding one. The state counter advances on the
negativegoing edge of the Clock input. Reset is asynchronous and
activehigh.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with the Clock of the
HC4040A for some designs.
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MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
1
1
16
SO16
D SUFFIX
CASE 751B
16
7
6
5
Clock
10
2
4
13
12
14
15
1
Reset
VCC
16
11
Q10
Q8
Q9
15
14
13
12
HC40
40A
ALYW
TSSOP16
DT SUFFIX
CASE 948F
16
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
FUNCTION TABLE
Q2
Q3
Clock
Reset
Output State
L
L
H
No Charge
Advance to Next State
All Outputs Are Low
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
ORDERING INFORMATION
Q12
Reset Clock
11
1
16
Q1
Device
Pin 16 = VCC
Pin 8 = GND
Q11
HC4040A
AWLYWW
LOGIC DIAGRAM
9
MC74HC4040AN
AWLYYWW
10
Q1
9
Package
Shipping
MC74HC4040AN
PDIP16
2000 / Box
MC74HC4040AD
SOIC16
48 / Rail
MC74HC4040ADR2
SOIC16
2500 / Reel
MC74HC4040ADT
TSSOP16
96 / Rail
MC74HC4040ADTR2
TSSOP16
2500 / Reel
Q12
Q6
Q5
Q7
Q4
Q3
Q2
8
GND
299
MC74HC4040A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
Max
Unit
2.0
6.0
VCC
55
+ 125
_C
0
0
0
0
1000
600
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VOH
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
VOL
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MC74HC4040A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter
Condition
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
Iin
ICC
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Unit
6.0
0.1
1.0
1.0
6.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Parameter
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
fmax
2.0
3.0
4.5
6.0
10
15
30
50
9.0
14
28
45
8.0
12
25
40
MHz
tPLH,
tPHL
2.0
3.0
4.5
6.0
96
63
31
25
106
71
36
30
115
88
40
35
ns
tPHL
2.0
3.0
4.5
6.0
45
30
30
26
52
36
35
32
65
40
40
35
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
69
40
17
14
80
45
21
15
90
50
28
22
ns
tTLH,
tTHL
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
15
110
36
22
19
ns
10
10
10
pF
Cin
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
* For TA = 25C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n1)] ns
VCC = 4.5 V: tP = [30.25 + 14.6 (n1)] ns
VCC = 3.0 V: tP = [61.5 + 34.4 (n1)] ns
VCC = 6.0V: tP = [24.4 + 12 (n1)] ns
Typical @ 25C, VCC = 5.0 V
CPD
31
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
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301
MC74HC4040A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
2.0
3.0
4.5
6.0
30
20
5
4
40
25
8
6
50
30
12
9
ns
tw
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
tw
2.0
3.0
4.5
6.0
70
40
15
13
80
45
19
16
90
50
24
20
ns
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
Symbol
trec
tr, tf
Parameter
2.0
3.0
4.5
6.0
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
OUTPUTS
Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)
SWITCHING WAVEFORMS
tf
tr
VCC
VCC
90%
50%
10%
Clock
Clock
trec
tw
GND
tw
1/fMAX
Reset
tPHL
tPLH
Q1
50%
90%
50%
10%
Any Q
tTHL
Figure 1.
50%
Figure 2.
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302
VCC
50%
tPHL
tTLH
GND
GND
MC74HC4040A
SWITCHING WAVEFORMS (continued)
TEST
POINT
VCC
Qn
OUTPUT
50%
DEVICE
UNDER
TEST
GND
tPLH
Qn+1
tPHL
CL*
50%
Figure 3.
Q1
Q2
Clock
10
Q10
Q11
14
Q12
15
R
Reset
Q3
11
Q4 = Pin 5
Q5 = Pin 3
Q6 = Pin 2
Q7 = Pin 4
Q8 = Pin 13
Q9 = Pin 12
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303
VCC = Pin 16
GND = Pin 8
MC74HC4040A
1
16
32
64
128
256
512
1024
2048
4096
Clock
Reset
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
APPLICATIONS INFORMATION
TimeBase Generator
VCC
1/6 of HC14A
1.0M
HC4040A
13
Clock
120Vac
60Hz
20pF
Q5
12
Q10
10
Q11
1/2
HC20
9
Q12
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304
1
2
4
5
1/2
HC20
1.0 Pulse/Minute
Output
MC74HC4046A
Phase-Locked Loop
HighPerformance SiliconGate CMOS
The MC74HC4046A is similar in function to the MC14046 Metal
gate CMOS device. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC4046A phaselocked loop contains three phase
comparators, a voltagecontrolled oscillator (VCO) and unity gain
opamp DEMOUT. The comparators have two common signal inputs,
COMP IN, and SIG IN. Input SIG IN and COMP IN can be used directly
coupled to large voltage signals, or indirectly coupled (with a series
capacitor to small voltage signals). The selfbias circuit adjusts small
voltage signals in the linear region of the amplifier. Phase comparator
1 (an exclusive OR gate) provides a digital error signal PC1 OUT and
maintains 90 degrees phase shift at the center frequency between
SIG IN and COMP IN signals (both at 50% duty cycle). Phase
comparator 2 (with leadingedge sensing logic) provides digital error
signals PC2 OUT and PCP OUT and maintains a 0 degree phase shift
between SIG IN and COMP IN signals (duty cycle is immaterial). The
linear VCO produces an output signal VCOOUT whose frequency is
determined by the voltage of input VCO IN signal and the capacitor
and resistors connected to pins C1A, C1B, R1 and R2. The unity gain
opamp output DEMOUT with an external resistor is used where the
VCO IN signal is needed but no loading can be tolerated. The inhibit
input, when high, disables the VCO and all opamps to minimize
standby power consumption.
Applications include FM and FSK modulation and demodulation,
frequency synthesis and multiplication, frequency discrimination,
tone decoding, data synchronization and conditioning,
voltagetofrequency conversion and motor speed control.
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MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
1
MC74HC4046AN
AWLYYWW
1
16
SO16
D SUFFIX
CASE 751B
16
1
HC4046A
AWLYWW
1
16
HC40
46A
ALYW
TSSOP16
DT SUFFIX
CASE 948F
16
1
1
16
SOEIAJ16
F SUFFIX
CASE 966
16
1
74HC4046B
AWLYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
Package
Shipping
MC74HC4046AN
Device
PDIP16
2000 / Box
MC74HC4046AD
SOIC16
48 / Rail
MC74HC4046ADR2
SOIC16
2500 / Reel
MC74HC4046AF
SOICEIAJ
See Note 1.
MC74HC4046AFEL
SOICEIAJ
See Note 1.
305
MC74HC4046A
Pin No.
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PCPOUT
PC1OUT
COMPIN
VCOOUT
INH
C1A
C1B
GND
VCOIN
DEMOUT
R1
R2
PC2OUT
SIGIN
PC3OUT
VCC
PIN ASSIGNMENT
PCPout
16
VCC
PC1out
15
PC3out
COMPin
14
SIGin
VCOout
13
PC2out
INH
12
R2
C1A
11
R1
C1B
10
DEMout
GND
VCOin
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iin
Iout
25
mA
ICC
50
mA
PD
750
500
mW
Tstg
Storage Temperature
65 to + 150
_C
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Parameter
VCC
Vin, Vout
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
Max
Unit
3.0
6.0
2.0
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
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306
MC74HC4046A
[Phase Comparator Section]
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
Volts
55 to
25_C
85C
125C
Unit
VIH
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
VIL
2.0
4.5
6.0
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
Minimum HighLevel
Output Voltage
PCPOUT, PCnOUT
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
VOH
(continued)
VCC
Volts
55 to
25_C
85C
125C
Unit
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Parameter
Test Conditions
Maximum LowLevel
Output Voltage QaQh
PCPOUT, PCnOUT
2.0
3.0
4.5
6.0
3.0
7.0
18.0
30.0
4.0
9.0
23.0
38.0
5.0
11.0
27.0
45.0
IOZ
Maximum ThreeState
Leakage Current
PC2OUT
6.0
0.5
5.0
10
ICC
6.0
4.0
40
160
Iin
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Guaranteed Limit
Symbol
Parameter
55 to 25_C
85C
125C
Unit
tPLH,
tPHL
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH,
tPHL
2.0
4.5
6.0
340
68
58
425
85
72
510
102
87
ns
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307
MC74HC4046A
[Phase Comparator Section]
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
tPLH,
tPHL
2.0
4.5
6.0
270
54
46
340
68
58
405
81
69
ns
tPLZ,
tPHZ
2.0
4.5
6.0
200
40
34
250
50
43
300
60
51
ns
tPZH,
tPZL
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
ns
tTLH,
tTHL
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
[VCO Section]
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
Volts
55 to
25_C
85C
125C
Unit
VIH
Minimum HighLevel
Input Voltage
INH
3.0
4.5
6.0
2.1
3.15
4.2
2.1
3.15
4.2
2.1
3.15
4.2
VIL
Maximum LowLevel
Input Voltage
INH
3.0
4.5
6.0
0.90
1.35
1.8
0.9
1.35
1.8
0.9
1.35
1.8
VOH
Minimum HighLevel
Output Voltage
VCOOUT
3.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
3.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
6.0
0.1
1.0
1.0
VOL
Iin
Maximum LowLevel
Output Voltage
VCOOUT
Maximum Input
Leakage Current
INH, VCOIN
INH = VIL
Resistor Range
R2
C1
Capacitor Range
Min
Max
Min
Max
Min
Max
3.0
4.5
6.0
0.1
0.1
0.1
1.0
2.5
4.0
0.1
0.1
0.1
1.0
2.5
4.0
0.1
0.1
0.1
1.0
2.5
4.0
3.0
4.5
6.0
3.0
3.0
3.0
300
300
300
3.0
3.0
3.0
300
300
300
3.0
3.0
3.0
300
300
300
3.0
4.5
6.0
3.0
3.0
3.0
300
300
300
3.0
3.0
3.0
300
300
300
3.0
3.0
3.0
300
300
300
3.0
4.5
6.0
40
40
40
No
Limit
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308
pF
MC74HC4046A
[VCO Section]
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
VCC
Volts
Parameter
55 to 25_C
Min
Max
85C
Min
Max
125C
Min
Max
Unit
f/T
3.0
4.5
6.0
fo
3.0
4.5
6.0
fVCO
3.0
4.5
6.0
VCO
3.0
4.5
6.0
Typical 50%
%/K
3
11
13
MHz
[Demodulator Section]
DC ELECTRICAL CHARACTERISTICS
Guaranteed Limit
Symbol
RS
VOFF
RD
Parameter
VCC
Volts
Test Conditions
55 to 25_C
Min
Max
50
50
50
300
300
300
85C
Min
Max
125C
Min
Max
Unit
Resistor Range
3.0
4.5
6.0
Offset Voltage
VCOIN to VDEMOUT
3.0
4.5
6.0
See Figure 12
mV
Dynamic Output
Resistance at DEMOUT
3.0
4.5
6.0
Typical 25
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309
MC74HC4046A
SWITCHING WAVEFORMS
VCC
SIGIN, COMPIN
INPUTS
SIGIN
INPUT
VCC
50%
50%
GND
VCC
GND
tPHL
COMPIN
INPUT
tPLH
90%
50%
PCPOUT, PC1OUT
PC3OUT
OUTPUTS
50%
PC2OUT
OUTPUT
10%
tTHL
tTLH
GND
tPHZ
tPZH
VOH
90%
50%
Figure 1.
HIGH
IMPEDANCE
Figure 2.
VCC
SIGIN
INPUT
TEST POINT
50%
GND
OUTPUT
VCC
COMPIN
INPUT
50%
CL*
GND
tPLZ
tPZL
PC2OUT
OUTPUT
DEVICE
UNDER
TEST
HIGH
IMPEDANCE
50%
10%
Figure 3.
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310
MC74HC4046A
DETAILED CIRCUIT DESCRIPTION
I1
+
_
CURRENT
MIRROR
I1 + I2 = I3
R2
VCOIN
9
11
I2
+
_
VCOOUT
I3
R1
+
_
DEMODOUT 10
C1
(EXTERNAL)
7
INH
Vref
+
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311
MC74HC4046A
Phase Comparators
VCC
SIGIN
PC2OUT
14
13
VCC
COMPIN
3
PCPOUT
1
PC3OUT
15
PC1OUT
2
SIGIN
COMPIN
PC1OUT
VCOIN
VCC
GND
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312
MC74HC4046A
Phase Comparator 2
and will cause the output to go high until the VCO leading
edge is seen, potentially for an entire SIGIN period. This
would cause the VCO to speed up during that time. When
using PC1, the output of that phase detector would be
disturbed for only the short duration of the noise spike and
would cause less upset.
Phase Comparator 3
VCC
HIGH IMPEDANCE OFFSTATE
GND
VCOIN
PCPOUT
SIGIN
COMPIN
PC3OUT
VCOIN
VCC
GND
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313
MC74HC4046A
VCC=6.0 V
800
VCC=3.0 V
4.0
VCC=4.5 V
400
VCC=4.5 V
I I ( A)
R I = (k )
VCC=3.0 V
VCC=6.0 V
0
1/2 VCC1.0 V
1/2 VCC
1/2 VCC+1.0 V
4.0
1/2VCC 500 mV
VI (V)
1/2 VCC
VI (V)
DEMOD OUT
15
6.0
VDEM
OUT
VCC=6.0 V RS=300 k
VCC=6.0 V RS=50 k
VCC=4.5 V RS=300 k
VCC=4.5 V RS=50 k
R1=3.0 k
5.0
R1=300 k
R1=100 k
R1=300 k
5.0
R1=3.0 k
15
100
3.0
VCOIN (V)
10
R1=100 k
5.0
0
5.0
VCC = 4.5 V
C1 = 100 pF; R2 = ; VVCOIN = 1/2 VCC
10
15
100
50
0
50
100
AMBIENT TEMPERATURE (C)
0
50
100
AMBIENT TEMPERATURE (C)
10
FREQUENCY STABILITY (%)
R1=300 k
VCC = 3.0 V
C1 = 100 pF; R2 = ; VVCOIN=1/3 VCC
150
R1=3.0 k
15
50
6.0
R1=100 k
10
VCC=3.0 V RS=300 k
VCC=3.0 V RS=50 k
0
10
6.0
4.0
2.0
0
2.0
4.0
6.0
8.0
10
100
150
R1=3.0 k
R1=300 k
R1=100 k
8.0
VCC = 6.0 V
C1 = 100 pF; R2 = ; VVCOIN=1/2 VCC
50
50
100
150
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314
MC74HC4046A
23
70
21
60
19
VCC = 3.0 V
f VCO (KHz)
f VCO(MHz)
50
VCC = 4.5 V
17
15
13
R1 = 3.0 k
C1 = 39 pF
9
7.0
0.5
1.0
1.5
40
30
20
VCC = 3.0 V
11
2.0
2.5
3.0
3.5
R1 = 3.0 k
C1 = 0.1 F
10
0
4.0
0.5
1.0
1.5
VVCOIN (V)
2.0
2.5
VVCOIN (V)
3.0
3.5
4.0
2.0
VCC = 6.0 V
0.9
VCC = 4.5 V
VCC = 4.5 V
0.8
VCC = 6.0 V
0.7
f VCO (KHz)
VCC = 3.0 V
f VCO(MHz)
VCC = 6.0 V
VCC = 4.5 V
VCC = 6.0 V
1.0
VCC = 3.0 V
0.6
0.5
0.4
0.3
0.2
R1 = 300 k
C1 = 39 pF
0
0
0.5
1.0
1.5
2.0
2.5
VVCOIN (V)
3.0
3.5
4.5
4.0
0.5
1.0
1.5
2.0
2.5
3.0
VVCOIN (V)
3.5
4.0
4.5
C1 = 1.0 F
1.0
f VCO (%)
VCC=
4.5 V
6.0 V
f2
3.0 V
f0
f0
4.5 V
f1
6.0 V
1.0
3.0 V
2.0
R1 = 300 k
C1 = 0.1 F
0.1
100
R2 = ; V = 0.5 V
C1 = 39 pF
101
102
MIN
103
R1 (k)
1/2 VCC
MAX
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315
MC74HC4046A
106
106
105
PR2 ( W)
PR1 ( W)
105
VCC = 6.0 V, C1 = 40 pF
104
VCC = 6.0 V, C1 = 40 pF
VCC = 6.0 V, C1 = 1.0 F
104
VCC = 4.5 V, C1 = 40 pF
VCC = 4.5 V, C1 = 1.0 F
VCC = 4.5 V, C1 = 40 pF
VCC = 4.5 V, C1 = 1.0 F
VCC = 3.0 V, C1 = 40 pF
VCC = 3.0 V, C1 = 1.0 F
103
100
101
R1 (k)
102
103
100
103
101
102
103
R1 = R2 = ; Tamb = 25C
107
106
VCO
(Hz)
102
VCC=6.0 V
VCC =
6.0 V
4.5 V
3.0 V
6.0 V
4.5 V
3.0 V
6.0 V
4.5 V
3.0 V
105
R1=3.0 k
PDEM ( W)
R2 (k)
108
103
VCC = 3.0 V, C1 = 40 pF
VCC=4.5 V
101
104
VCC=3.0 V
R1=100 k
103
R1=300 k
100
101
102
RS (k)
102
103
101
off (Hz)
106
105
VVCOIN = 1/3 VCC FOR VCC = 3.0 V; INH = GND; Tamb = 25C
6.0 V
4.5 V
3.0 V
104
105
106
VCC = 4.5 V; R2 =
107
2 fL (Hz)
107
104
108
VCC =
6.0 V
4.5 V
3.0 V
6.0 V
4.5 V
3.0 V
103
C1 (pF)
108
102
106
105
R2=3.0 k
104
103
R2=100 k
102
101
103
R2=300 k
101
102
103
104
105
106
102
107
C1 (pF)
106
105
104
103
102
101
R1C1
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316
MC74HC4046A
20
14
R1=3.0 k
C1=39 pF
12
R1=10 k
10
FREQ. (MHz)
R1=20 k
R1=30 k
10
R1=40 k
8.0
R1=3 k
R1=10 k
R1=20 k
R1=30 k
R1=40 k
R1=50 k
R1=100 k
R1=300 k
6.0
4.0
R1=50 k
5.0
2.0
R1=100 k
C1=39 pF
R1=300 k
2.0
1.0
101
102
103
104
105
100
101
102
103
R2 ( k)
104
R2 ( k)
20
C1=39 pF
2f L (MHz)
FREQ. (MHz)
15
R1=10 k
R1=3.0 k
R1=20 k
10
R1=30 k
R1=40 k
R1=50 k
R1=100 k
R1=300 k
0
1.0
101
102
R2 ( k)
103
104
105
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317
105
106
MC74HC4046A
APPLICATION INFORMATION
The following information is a guide for approximate values of R1, R2, and C1. Figures 19, 20, and 21 should be used as
references as indicated below, also the values of R1, R2, and C1 should not violate the Maximum values indicated in the DC
ELECTRICAL CHARACTERISTICS tables.
Phase Comparator 1
R2 =
R2
0R
Given f0
Given f0 and fL
Use f0 with
Figure 19 to
determine R1 and
C1.
Calculate fmin
fmin = f0fL
Determine values
of C1 and R2 from
Figure 20.
Determine R1C1
from Figure 21.
Phase Comparator 2
R2 =
Given fmax and f0
Determine the
value of R1 and
C1 using Figure
19 and use Figure
21 to obtain 2fL
and then use this
to calculate fmin.
R2
0R
Given f0 and fL
Calculate fmin
fmin = f0fL
Determine values
of C1 and R2 from
Figure 20.
Determine R1C1
from Figure 21.
Phase Comparator 3
R2 =
Given fmax and f0
Determine the
value of R1 and
C1 using Figure
19 and Figure 21
to obtain 2fL and
then use this to
calculate fmin.
R2
0R
Given f0 and fL
Calculate fmin:
fmin = f0fL
Determine values
of C1 and R2 from
Figure 20.
Determine R1C1
from Figure 21.
Calculate value of
R1 from the value
of C1 and the
product of R1C1
from Figure 21.
Calculate value of
R1 from the value
of C1 and the
product of R1C1
from Figure 21.
Calculate value of
R1 from the value
of C1 and the
product of R1C1
from Figure 21.
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318
MC74HC4051A,
MC74HC4052A,
MC74HC4053A
Analog Multiplexers /
Demultiplexers
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MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
1
HC405xAN
AWLYYWW
1
16
SO16
D SUFFIX
CASE 751B
16
1
HC405xAD
AWLYYWW
1
16
SO16 WIDE
DW SUFFIX
CASE 751G
16
HC405xA
AWLYWW
1
16
HC40
5xA
ALYW
TSSOP16
DT SUFFIX
CASE 948F
16
1
1
16
SOEIAJ16
F SUFFIX
CASE 966
16
1
74HC405xB
AWLYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 331 of this data sheet.
319
Control Inputs
Enable
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
X
13
X0
14
X1
15
X2
ANALOG
12
MULTIPLEXER/
INPUTS/ X3
DEMULTIPLEXER
OUTPUTS X4 1
5
X5
2
X6
4
X7
11
A
CHANNEL
10
B
SELECT
9
INPUTS
C
6
ENABLE
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
COMMON
OUTPUT/
INPUT
Select
B
A
ON Channels
X0
X1
X2
X3
X4
X5
X6
X7
NONE
L
H
L
H
L
H
L
H
X
L
L
H
H
L
L
H
H
X
X = Dont Care
X2
X1
X0
X3
15
14
13
12
11
10
8
GND
X4
X6
X7
X5
Enable VEE
Control Inputs
Select
Enable
ON Channels
L
L
L
L
H
L
L
H
H
X
L
H
L
H
X
Y0
Y1
Y2
Y3
12
ANALOG
INPUTS/OUTPUTS
CHANNEL-SELECT
INPUTS
X0
14
X1
15
X2
11
X3
Y0
Y1
Y2
Y3
A
B
ENABLE
X SWITCH
13
X
COMMON
OUTPUTS/INPUTS
1
5
2
Y SWITCH
NONE
X = Dont Care
10
9
X0
X1
X2
X3
VCC
16
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
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320
X2
X1
X0
X3
15
14
13
12
11
10
8
GND
Y0
Y2
Y3
Y1
Enable VEE
LOGIC DIAGRAM
MC74HC4053A
Triple SinglePole, DoublePosition Plus Common Off
12
X0
13
X1
14
X SWITCH
ANALOG
INPUTS/OUTPUTS
Y0
1
Y1
15
Y SWITCH
Z0
3
Z1
Z SWITCH
Enable
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
X
COMMON
OUTPUTS/INPUTS
Select
B
A
L
L
H
H
L
L
H
H
X
ON Channels
Z0
Z0
Z0
Z0
Z1
Z1
Z1
Z1
L
H
L
H
L
H
L
H
X
Y0
Y0
Y1
Y1
Y0
Y0
Y1
Y1
NONE
X0
X1
X0
X1
X0
X1
X0
X1
X = Dont Care
11
A
10
B
9
C
6
ENABLE
PIN 16 = VCC
PIN 7 = VEE
PIN 8 = GND
CHANNEL-SELECT
INPUTS
X1
X0
15
14
13
12
11
10
8
GND
Y1
Y0
Z1
Z0
Enable VEE
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
0.5 to + 7.0
0.5 to + 14.0
7.0 to + 5.0
VIS
VEE 0.5 to
VCC + 0.5
Vin
25
mA
PD
750
500
450
mW
Tstg
65 to + 150
_C
VCC
VEE
TL
(Referenced to GND)
(Referenced to VEE)
Plastic DIP
EIAJ/SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
EIAJ/SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
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321
Parameter
Min
Max
Unit
2.0
2.0
6.0
12.0
6.0
GND
VIS
VEE
VCC
Vin
GND
VCC
VIO*
1.2
55
+ 125
_C
0
0
0
0
1000
600
500
400
ns
VCC
VEE
(Referenced to GND)
(Referenced to VEE)
TA
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
Symbol
Parameter
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
Iin
6.0
0.1
1.0
1.0
6.0
6.0
1
4
10
40
20
80
ICC
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
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322
Condition
VCC
VEE
55 to 25C
85C
125C
Unit
4.5
4.5
6.0
0.0
4.5
6.0
190
120
100
240
150
125
280
170
140
4.5
4.5
6.0
0.0
4.5
6.0
150
100
80
190
125
100
230
140
115
Parameter
Maximum ON Resistance
Ron
Maximum Difference in ON
Resistance Between Any Two
Channels in the Same Package
4.5
4.5
6.0
0.0
4.5
6.0
30
12
10
35
15
12
40
18
14
Ioff
6.0
6.0
0.1
0.5
1.0
6.0
6.0
6.0
6.0
6.0
6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
6.0
6.0
6.0
6.0
6.0
6.0
0.2
0.1
0.1
2.0
1.0
1.0
4.0
2.0
2.0
Ion
VCC
V
55 to 25C
85C
125C
Unit
Symbol
Parameter
tPLH,
tPHL
2.0
3.0
4.5
6.0
270
90
59
45
320
110
79
65
350
125
85
75
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
40
25
12
10
60
30
15
13
70
32
18
15
ns
tPLZ,
tPHZ
2.0
3.0
4.5
6.0
160
70
48
39
200
95
63
55
220
110
76
63
ns
tPZL,
tPZH
2.0
3.0
4.5
6.0
245
115
49
39
315
145
69
58
345
155
83
67
ns
Cin
10
10
10
pF
CI/O
Maximum Capacitance
Analog I/O
35
35
35
pF
130
80
50
130
80
50
130
80
50
Feedthrough
1.0
1.0
1.0
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor HighSpeed CMOS Data Book (DL129/D)
Typical @ 25C, VCC = 5.0 V, VEE = 0 V
CPD
HC4051A
HC4052A
HC4053A
45
80
45
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
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323
Symbol
BW
Parameter
2.25
4.50
6.00
2.25
4.50
6.00
2.25
4.50
6.00
2.25
4.50
6.00
50
50
50
2.25
4.50
6.00
2.25
4.50
6.00
40
40
40
2.25
4.50
6.00
2.25
4.50
6.00
25
105
135
RL = 10k, CL = 10pF
2.25
4.50
6.00
2.25
4.50
6.00
35
145
190
2.25
4.50
6.00
2.25
4.50
6.00
50
50
50
2.25
4.50
6.00
2.25
4.50
6.00
60
60
60
Unit
25C
THD
Limit*
VEE
V
Feedthrough Noise.
ChannelSelect Input to Common
I/O (Figure 8)
VCC
V
Condition
51
52
53
80
80
80
95
95
95
120
120
120
MHz
dB
mVPP
dB
%
2.25
4.50
6.00
2.25
4.50
6.00
0.10
0.08
0.05
250
200
125C
150
25C
55C
100
50
300
140
120
125C
100
80
25C
60
55C
40
20
0.25
0.5
0.75
1.0
1.25
1.5
1.75
2.0
2.25
0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75 3.0
VIS, INPUT VOLTAGE (VOLTS), REFERENCED TO VEE
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324
120
105
100
90
80
125C
60
25C
40
55C
20
0
75
125C
60
25C
45
55C
30
15
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
0.5
3.0 3.5
4.0
60
70
2.0 2.5
80
60
50
125C
40
30
25C
20
55C
10
0
4.5
1.0 1.5
3.5
2.5
1.5
0.5
0.5
1.5
2.5
3.5
50
125C
40
25C
30
55C
20
10
0
6.0 5.0 4.0 3.0 2.0 1.0
4.5
2.0
3.0 4.0
5.0
6.0
PLOTTER
1.0
PROGRAMMABLE
POWER
SUPPLY
MINI COMPUTER
DC ANALYZER
VCC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
VEE
GND
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325
VCC
VCC
16
VEE
ANALOG I/O
OFF
A
VCC
VIH
OFF
VIH
6
7
8
VEE
COMMON O/I
6
7
8
VEE
VCC
VCC
16
A
VEE
VCC
16
0.1F
fin
ON
VOS
dB
METER
ON
N/C
COMMON O/I
OFF
VCC
OFF
VCC
COMMON O/I
OFF
NC
VCC
16
VEE
RL
CL*
ANALOG I/O
VIL
6
7
8
6
7
8
VEE
VEE
VCC
16
VIS
0.1F
fin
VCC
16
VOS
dB
METER
OFF
RL
CL*
RL
ON/OFF
COMMON O/I
ANALOG I/O
RL
OFF/ON
RL
RL
6
7
8
VEE
VIL or VIH
Vin 1 MHz
tr = tf = 6 ns
VEE
VCC
GND
CHANNEL SELECT
*Includes all probe and jig capacitance
6
7
8
TEST
POINT
CL*
VCC
11
CHANNEL SELECT
*Includes all probe and jig capacitance
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326
VCC
VCC
CHANNEL
SELECT
ON/OFF
50%
COMMON O/I
ANALOG I/O
OFF/ON
GND
tPLH
TEST
POINT
CL*
tPHL
ANALOG
OUT
6
7
8
50%
CHANNEL SELECT
*Includes all probe and jig capacitance
VCC
16
ANALOG
IN
COMMON O/I
ANALOG I/O
VCC
ON
50%
TEST
POINT
CL*
GND
tPHL
tPLH
ANALOG
OUT
6
7
8
50%
tf
tr
90%
50%
10%
ENABLE
tPZL
ANALOG
OUT
tPLZ
VCC
2
GND
50%
TEST
POINT
ON/OFF
CL*
VOL
ENABLE
90%
1k
ANALOG I/O
tPZH tPHZ
ANALOG
OUT
VCC
16
VCC
HIGH
IMPEDANCE
10%
VOH
50%
6
7
8
HIGH
IMPEDANCE
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327
A
VCC
16
RL
fin
16
VOS
ON
COMMON O/I
ON/OFF
NC
ANALOG I/O
0.1F
OFF/ON
OFF
VEE
RL
RL
CL*
RL
CL*
6
7
8
VEE
VCC
6
7
8
11
CHANNEL SELECT
VIS
VCC
16
0.1F
fin
10
VOS
ON
CL*
TO
DISTORTION
METER
30
40
dB
RL
FUNDAMENTAL FREQUENCY
20
50
DEVICE
60
6
7
8
VEE
SOURCE
70
80
90
100
1.0
2.0
3.125
FREQUENCY (kHz)
APPLICATIONS INFORMATION
outputs to VCC or GND through a low value resistor helps
minimize crosstalk and feedthrough noise that may be
picked up by an unused switch.
Although used here, balanced supplies are not a
requirement. The only constraints on the power supplies are
that:
VCC GND = 2 to 6 volts
VEE GND = 0 to 6 volts
VCC VEE = 2 to 12 volts
and VEE GND
When voltage transients above VCC and/or below VEE are
anticipated on the analog channels, external Germanium or
Schottky diodes (Dx) are recommended as shown in Figure
16. These diodes should be able to absorb the maximum
anticipated current surges during clipping.
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328
+5V
16
+5V
ANALOG
SIGNAL
5V
ON
6
7
8
Dx
+5V
ANALOG
SIGNAL
VCC
16
Dx
Dx
VEE
VEE
7
8
5V
VEE
+5V
+5V
16
+5V
ANALOG
SIGNAL
VEE
ON/OFF
6
7
8
VEE
Dx
ON/OFF
5V
TO EXTERNAL CMOS
CIRCUITRY 0 to 5V
DIGITAL SIGNALS
11
10
9
VCC
ANALOG
SIGNAL
+5V
*
R
R
11
10
9
+5V
+5V
VEE
VEE
16
ANALOG
SIGNAL
ON/OFF
+5V
ANALOG
SIGNAL
VEE
+5V
6
7
8
LSTTL/NMOS
CIRCUITRY
VEE
* 2K R 10K
11
10
9
LSTTL/NMOS
CIRCUITRY
HCT
BUFFER
11
13
LEVEL
SHIFTER
14
10
15
LEVEL
SHIFTER
12
LEVEL
SHIFTER
ENABLE
LEVEL
SHIFTER
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329
X0
X1
X2
X3
X4
X5
X6
X7
10
12
LEVEL
SHIFTER
14
15
LEVEL
SHIFTER
11
13
ENABLE
LEVEL
SHIFTER
X0
X1
X2
X3
X
Y0
Y1
Y2
Y3
11
13
LEVEL
SHIFTER
12
14
B
10
LEVEL
SHIFTER
2
15
C
LEVEL
SHIFTER
5
4
ENABLE
LEVEL
SHIFTER
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330
X1
X0
X
Y1
Y0
Y
Z1
Z0
Z
Shipping
MC74HC4051AN
Device
PDIP16
MC74HC4051AD
SOIC16
48 Units / Rail
MC74HC4051ADR2
SOIC16
MC74HC4051ADT
TSSOP16
96 Units / Rail
MC74HC4051ADTR2
TSSOP16
MC74HC4051ADW
SOIC WIDE
48 Units / Rail
MC74HC4051ADWR2
SOIC WIDE
MC74HC4051AF
SOEIAJ16
See Note 1.
MC74HC4051AFEL
SOEIAJ16
See Note 1.
MC74HC4052AN
PDIP16
MC74HC4052AD
SOIC16
48 Units / Rail
MC74HC4052ADR2
SOIC16
MC74HC4052ADT
TSSOP16
96 Units / Rail
MC74HC4052ADTR2
TSSOP16
MC74HC4052ADW
SOIC WIDE
48 Units / Rail
MC74HC4052ADWR2
SOIC WIDE
MC74HC4052AF
SOEIAJ16
See Note 1.
MC74HC4052AFEL
SOEIAJ16
See Note 1.
MC74HC4053AN
PDIP16
MC74HC4053AD
SOIC16
48 Units / Rail
MC74HC4053ADR2
SOIC16
MC74HC4053ADT
TSSOP16
96 Units / Rail
MC74HC4053ADTR2
TSSOP16
MC74HC4053ADW
SOIC WIDE
48 Units / Rail
MC74HC4053ADWR2
SOIC WIDE
MC74HC4053AF
SOEIAJ16
See Note 1.
MC74HC4053AFEL
SOEIAJ16
See Note 1.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
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331
MC74HC4060A
14-Stage Binary Ripple
Counter With Oscillator
HighPerformance SiliconGate CMOS
The MC74C4060A is identical in pinout to the standard CMOS
MC14060B. The device inputs are compatible with standard CMOS
outputs; with pullup resistors, they are compatible with LSTTL
outputs.
This device consists of 14 masterslave flipflops and an oscillator
with a frequency that is controlled either by a crystal or by an RC
circuit connected externally. The output of each flipflop feeds the
next and the frequency at each output is half of that of the preceding
one. The state of the counter advances on the negativegoing edge of
the Osc In. The activehigh Reset is asynchronous and disables the
oscillator to allow very low power consumption during standby
operation.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with Osc Out 2 of the
HC4060A.
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MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
MC74HC4060AN
AWLYYWW
1
16
SO16
D SUFFIX
CASE 751B
16
HC4060A
AWLYWW
1
16
HC40
60A
ALYW
TSSOP16
DT SUFFIX
CASE 948F
16
1
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
LOGIC DIAGRAM
Osc Out 1 Osc Out 2
Q10
Q8
Q9
15
14
13
10
Osc Osc
Reset Osc In Out 1 Out 2
12
11
10
9
Osc In
Q12
Q13
Q14
Q6
Q5
Q7
Q4
GND
Reset
FUNCTION TABLE
Clock
Reset
Output State
L
L
H
No Charge
Advance to Next State
All Outputs Are Low
11
12
9
7
5
4
6
14
13
15
1
2
3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q12
Q13
Q14
Pin 16 = VCC
Pin 8 = GND
ORDERING INFORMATION
Device
332
Package
Shipping
MC74HC4060AN
PDIP16
2000 / Box
MC74HC4060AD
SOIC16
48 / Rail
MC74HC4060ADR2
SOIC16
2500 / Reel
MC74HC4060ADT
TSSOP16
96 / Rail
MC74HC4060ADTR2
TSSOP16
2500 / Reel
MC74HC4060A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
Vin
Vout
20
mA
Iout
25
mA
ICC
50
mA
PD
750
500
450
mW
Tstg
65 to + 150
_C
Iin
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
Min
Max
Unit
2.5*
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
*The oscillator is guaranteed to function at 2.5 V minimum. However, parametrics are tested
at 2.0 V by driving Pin 11 with an external clock source.
Parameter
Condition
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
VIH
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
VOH
|Iout| 2.4mA
|Iout| 4.0mA
|Iout| 5.2mA
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333
MC74HC4060A
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol
VOL
Parameter
Condition
VOH
VOL
Iin
ICC
|Iout| 0.7mA
|Iout| 1.0mA
|Iout| 1.3mA
|Iout| 0.7mA
|Iout| 1.0mA
|Iout| 1.3mA
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
6.0
0.1
1.0
1.0
6.0
40
160
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Parameter
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
fmax
2.0
3.0
4.5
6.0
6.0
10
30
50
9.0
14
28
45
8.0
12
25
40
MHz
tPLH,
tPHL
2.0
3.0
4.5
6.0
300
180
60
51
375
200
75
64
450
250
90
75
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
500
350
250
200
750
450
275
220
1000
600
300
250
ns
tPHL
2.0
3.0
4.5
6.0
195
75
39
33
245
100
49
42
300
125
61
53
ns
tPLH,
tPHL
2.0
3.0
4.5
6.0
75
60
15
13
95
75
19
16
125
95
24
20
ns
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334
MC74HC4060A
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) continued
Symbol
tTLH,
tTHL
Cin
Parameter
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
Guaranteed Limit
VCC
V
55 to 25C
85C
125C
Unit
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
10
10
10
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
* For TA = 25C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:
VCC = 2.0 V: tP = [93.7 + 59.3 (n1)] ns
VCC = 4.5 V: tP = [30.25 + 14.6 (n1)] ns
VCC = 3.0 V: tP = [61.5+ 34.4 (n1)] ns
VCC = 6.0 V: tP = [24.4 + 12 (n1)] ns
Typical @ 25C, VCC = 5.0 V
CPD
pF
35
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
VCC
V
55 to 25C
85C
125C
Unit
2.0
3.0
4.5
6.0
100
75
20
17
125
100
25
21
150
120
30
25
ns
tw
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
23
19
ns
tw
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
23
19
ns
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
Symbol
trec
tr, tf
Parameter
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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335
MC74HC4060A
PIN DESCRIPTIONS
INPUTS
Osc In (Pin 11)
SWITCHING WAVEFORMS
tf
tw
tr
90%
50%
10%
Osc In
Reset
VCC
GND
tPHL
GND
tw
1/fMAX
tPHL
tPLH
Q
VCC
50%
90%
50%
10%
50%
trec
tTLH
Osc In
tTHL
GND
Figure 1.
Figure 2.
TEST
POINT
VCC
Qn
OUTPUT
50%
DEVICE
UNDER
TEST
GND
tPLH
Qn+1
VCC
50%
tPHL
CL*
50%
Figure 3.
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336
MC74HC4060A
Q4
Q5
Osc Out 1
Osc In
Reset
Q13
Q14
R
Osc Out 2
Q12
9
Q6 = Pin 4
Q7 = Pin 6
Q8 = Pin 14
Q9 = Pin 13
10
Q10 = Pin 15
VCC = Pin 16
GND = Pin 8
11
12
Reset
12
Osc In
11
Osc Out 1
10
Osc Out 2
Rtc
RS
Ctc
Reset
12
Osc In
11
Osc Out 1
10
Rf
R1
C1
C2
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337
Osc Out 2
MC74HC4060A
TABLE 1. CRYSTAL OSCILLATOR AMPLIFIER SPECIFICATIONS (TA = 25C; Input = Pin 11, Output = Pin 10)
Type
60M Minimum
5pF Typical
7pF Typical
Series Capacitance, Ca
5pF Typical
3Vdc Supply
4Vdc Supply
5Vdc Supply
6Vdc Supply
LS
CS
Re
Xe
CO
RS
jXC2
Rload
Ca
jXCo
jXLs
Xload
Zload
jXCs
Cin
jXC
Cout
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338
MC74HC4060A
DESIGN PROCEDURES
The following procedure applies for oscillators operating below 2MHz where Z is a resistor R1. Above 2MHz, additional
impedance elements should be considered: Cout and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from
180C.
Step 1: Calculate the equivalent series circuit of the crystal at the frequency of oscillation.
Ze
Reactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency.
The maximum Rs for the crystal should be used in the equation.
Step 2: Determine , the attenuation, of the feedback network. For a closed-loop gain of 2,A = 2, = 2/A where A is
the gain of the HC4060A amplifier.
Step 3: Determine the manufacturers loading capacitance. For example: A manufacturer may specify an external load
capacitance of 32pF at the required frequency.
Step 4: Determine the required Q of the system, and calculate Rload, For example, a manufacturer specifies a crystal Q of
100,000. In-circuit Q is arbitrarily set at 20% below crystal Q or 80,000. Then Rload = (2foLS/Q) Rs where Ls and Rs are
crystal parameters.
Step 5: Simultaneously solve, using a computer,
b
@ XC2
+ R @ Re )XCXC2
(Xe * XC)
+ XC2 ) XC ) ReRXC2 + XCload (where the loading capacitor is an external load, not including Co)
RXCoXC2 [(XC ) XC2)(XC ) XCo) * XC(XC ) XCo ) XC2)]
Rload +
X2C2(XC ) XCo)2 ) R2(XC ) XCo ) XC2)2
Xe
( Eq 1 )
( Eq 2 )
( Eq 3 )
Here R = Rout + R1. Rout is amp output resistance, R1 is Z. The C corresponding to XC is given by C = C1 + Cin.
Alternately, pick a value for R1 (i.e, let R1 = RS). Solve Equations 1 and 2 for C1 and C2. Use Equation 3 and the fact that
Q = 2foLs/(Rs + Rload) to find in-circuit Q. If Q is not satisfactory pick another value for R1 and repeat the procedure.
CHOOSING R1
the first overtone. Rf must be large enough so as to not affect
Power is dissipated in the effective series resistance of the
the phase of the feedback network in an appreciable manner.
crystal. The drive level specified by the crystal manufacturer
ACKNOWLEDGEMENTS AND RECOMMENDED
is the maximum stress that a crystal can withstand without
REFERENCES
damage or excessive shift in frequency. R1 limits the drive
The following publications were used in preparing this
level.
data sheet and are hereby acknowledged and recommended
To verify that the maximum dc supply voltage does not
for reading:
overdrive the crystal, monitor the output frequency as a
Technical Note TN-24, Statek Corp.
function of voltage at Osc Out 2 (Pin 9). The frequency
Technical Note TN-7, Statek Corp.
should increase very slightly as the dc supply voltage is
D. Babin, Designing Crystal Oscillators, Machine
increased. An overdriven crystal will decrease in frequency
Design, March 7, 1985.
or become unstable with an increase in supply voltage. The
D. Babin, Guidelines for Crystal Oscillator Design,
operating supply voltage must be reduced or R1 must be
Machine Design, April 25, 1985.
increased in value if the overdriven condition exists. The
ALSO RECOMMENDED FOR READING:
user should note that the oscillator start-up time is
E. Hafner, The Piezoelectric Crystal Unit-Definitions
proportional to the value of R1.
and Method of Measurement, Proc. IEEE, Vol. 57, No. 2,
SELECTING Rf
Feb., 1969.
The feedback resistor, Rf, typically ranges up to 20M. Rf
D. Kemper, L. Rosine, Quartz Crystals for Frequency
determines the gain and bandwidth of the amplifier. Proper
Control, Electro-Technology, June, 1969.
bandwidth insures oscillation at the correct frequency plus
P. J. Ottowitz, A Guide to Crystal Selection, Electronic
roll-off to minimize gain at undesirable frequencies, such as
Design, May, 1966.
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339
MC74HC4060A
1
16
32
64
128
256
Clock
Reset
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q12
Q13
Q14
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340
512
1024
2048
4096
8192
16384
MC74HC4066A
Advance Information
Quad Analog Switch/
Multiplexer/Demultiplexer
4
5
XC
3 Y
B
9 Y
C
ANALOG
OUTPUTS/INPUTS
XD
11
D ON/OFF CONTROL
12
10 Y
D
14
PDIP14
N SUFFIX
CASE 646
HC4066AN
AWLYYWW
1
14
SOIC14
D SUFFIX
CASE 751A
HC4066AD
AWLYWW
1
14
HC40
66A
ALYW
TSSOP14
DT SUFFIX
CASE 948G
1
14
SOEIAJ14
F SUFFIX
CASE 965
74HC4066A
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
VCC
A ON/OFF
CONTROL
D ON/OFF
CONTROL
XD
YD
XA
YA
14
13
YB
XB
B ON/OFF
CONTROL
C ON/OFF
CONTROL
GND
12
11
10
YC
XC
ORDERING INFORMATION
ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
On/Off Control
Input
State of
Analog Switch
L
H
Off
On
Package
Shipping
MC74HC4066AN
Device
PDIP14
2000 / Box
MC74HC4066AD
SOIC14
55 / Rail
SOIC14
2500 / Reel
MC74HC4066ADR2
MARKING
DIAGRAMS
PIN ASSIGNMENT
13
B ON/OFF CONTROL
C ON/OFF CONTROL
2 Y
A
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341
MC74HC4066ADT
TSSOP14
96 / Rail
MC74HC4066ADTR2
TSSOP14
2500 / Reel
MC74HC4066AF
SOEIAJ14
See Note 1.
MC74HC4066A
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
0.5 to + 14.0
V
V
VCC
VIS
Vin
25
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
TL
Plastic DIP
EIAJ/SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
EIAJ/SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
v
v
Parameter
Min
Max
Unit
2.0
12.0
GND
VCC
Vin
GND
VCC
VIO*
1.2
55
+ 125
_C
0
0
0
0
0
1000
600
500
400
250
VCC
VIS
TA
tr, tf
ns
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input
components. The reliability of the device will be unaffected unless the Maximum Ratings are
exceeded.
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25_C
85_C
125_C
Unit
VIH
2.0
3.0
4.5
9.0
12.0
1.5
2.1
3.15
6.3
8.4
1.5
2.1
3.15
6.3
8.4
1.5
2.1
3.15
6.3
8.4
VIL
2.0
3.0
4.5
9.0
12.0
0.5
0.9
1.35
2.7
3.6
0.5
0.9
1.35
2.7
3.6
0.5
0.9
1.35
2.7
3.6
Iin
12.0
0.1
1.0
1.0
6.0
12.0
2
4
20
40
40
160
ICC
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book
(DL129/D).
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342
MC74HC4066A
v
v
Guaranteed Limit
Symbol
Ron
VCC
V
55 to
25_C
Vin = VIH
VIS = VCC to GND
IS
2.0 mA (Figures 1, 2)
2.0
3.0
4.5
9.0
12.0
Vin = VIH
VIS = VCC or GND (Endpoints)
IS
2.0 mA (Figures 1, 2)
Parameter
Test Conditions
Maximum ON Resistance
85_C
125_C
120
70
70
160
85
85
200
100
100
2.0
3.0
4.5
9.0
12.0
70
50
30
85
60
60
100
80
80
Unit
Ron
Maximum Difference in ON
Resistance Between Any Two
Channels in the Same Package
Vin = VIH
VIS = 1/2 (VCC GND)
IS
2.0 mA
2.0
4.5
9.0
12.0
20
15
15
25
20
20
30
25
25
Ioff
Vin = VIL
VIO = VCC or GND
Switch Off (Figure 3)
12.0
0.1
0.5
1.0
Ion
Vin = VIH
VIS = VCC or GND
(Figure 4)
12.0
0.1
0.5
1.0
At supply voltage (VCC) approaching 3 V the analog switchon resistance becomes extremely nonlinear. Therefore, for lowvoltage
operation, it is recommended that these devices only be used to control digital signals.
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book
(DL129/D).
v
v
Guaranteed Limit
Symbol
Parameter
VCC
V
55 to
25_C
85_C
125_C
Unit
tPLH,
tPHL
2.0
3.0
4.5
9.0
12.0
40
30
5
5
5
50
40
7
7
7
60
50
8
8
8
ns
tPLZ,
tPHZ
2.0
3.0
4.5
9.0
12.0
80
60
20
20
20
90
70
25
25
25
110
80
35
35
35
ns
tPZL,
tPZH
2.0
3.0
4.5
9.0
12.0
80
45
20
20
20
90
50
25
25
25
100
60
30
30
30
ns
10
10
10
pF
35
1.0
35
1.0
35
1.0
Maximum Capacitance
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
15
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
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343
MC74HC4066A
Symbol
Parameter
Test Conditions
VCC
V
Limit*
25_C
54/74HC
Unit
BW
4.5
9.0
12.0
150
160
160
MHz
fin
Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 , CL = 50 pF
4.5
9.0
12.0
50
50
50
dB
4.5
9.0
12.0
40
40
40
Vin
1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 , CL = 50 pF
4.5
9.0
12.0
60
130
200
RL = 10 k, CL = 10 pF
4.5
9.0
12.0
30
65
100
fin
Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 , CL = 50 pF
4.5
9.0
12.0
70
70
70
4.5
9.0
12.0
80
80
80
THD
fin = 1 kHz, RL = 10 k, CL = 50 pF
THD = THDMeasured THDSource
VIS = 4.0 VPP sine wave
VIS = 8.0 VPP sine wave
VIS = 11.0 VPP sine wave
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344
mVPP
dB
4.5
9.0
12.0
0.10
0.06
0.04
MC74HC4066A
TBD
TBD
TBD
TBD
PLOTTER
PROGRAMMABLE
POWER
SUPPLY
TBD
MINI COMPUTER
DC ANALYZER
VCC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
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345
MC74HC4066A
VCC
VCC
VCC
VCC
14
GND
14
A
VCC
OFF
SELECTED
CONTROL
INPUT
VIL
7
CL*
SELECTED
CONTROL
INPUT
VCC
14
VIS
ON
0.1F
SELECTED
CONTROL
INPUT
VIH
VOS
VCC
14
fin
N/C
ON
GND
fin
dB
METER
VOS
OFF
0.1F
CL*
RL
dB
METER
SELECTED
CONTROL
INPUT
VCC
VCC
VCC/2
VCC/2
14
RL
RL
OFF/ON
VOS
IS
VCC
CL*
VCC
GND
Vin 1 MHz
tr = tf = 6 ns
ANALOG IN
SELECTED
CONTROL
INPUT
50%
GND
tPHL
tPLH
CONTROL
50%
ANALOG OUT
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346
MC74HC4066A
VCC
tr
tf
14
ANALOG IN
ANALOG OUT
ON
TEST
POINT
VCC
90%
50%
10%
CONTROL
GND
CL*
SELECTED
CONTROL
INPUT
tPZL
tPLZ
HIGH
IMPEDANCE
50%
VCC
ANALOG
OUT
tPZH
10%
VOL
90%
VOH
tPHZ
50%
HIGH
IMPEDANCE
VCC
14
RL
fin
VCC
VCC
1
TEST
POINT
ON/OFF
0.1 F
1 k
14
VOS
ON
OFF
VCC OR GND
CL*
RL
RL
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
CL*
VCC/2
RL
CL*
VCC/2
7
VCC/2
*Includes all probe and jig capacitance.
VCC
A
VIS
VCC
14
N/C
OFF/ON
VOS
0.1 F
N/C
fin
ON
RL
CL*
TO
DISTORTION
METER
VCC/2
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
VCC
ON/OFF CONTROL
*Includes all probe and jig capacitance.
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347
MC74HC4066A
0
10
FUNDAMENTAL FREQUENCY
20
dBm
30
40
50
DEVICE
60
SOURCE
70
80
90
1.0
2.0
3.0
FREQUENCY (kHz)
APPLICATION INFORMATION
VCC
VCC = 12 V
+ 12 V
14
ANALOG I/O
ON
ANALOG O/I
Dx
+ 12 V
SELECTED
CONTROL
INPUT
7
16
Dx
ON
0V
0V
VCC
Dx
VCC
OTHER CONTROL
INPUTS
(VCC OR GND)
Dx
SELECTED
CONTROL
INPUT
7
OTHER CONTROL
INPUTS
(VCC OR GND)
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348
MC74HC4066A
+5 V
+5 V
14
ANALOG
SIGNALS
R*
R* R* R*
HC4066A
LSTTL/
NMOS
HCT
BUFFER
LSTTL/
NMOS
14
ANALOG
SIGNALS
HC4066A
5
6
CONTROL
INPUTS
15
14
ANALOG
SIGNALS
ANALOG
SIGNALS
14
CONTROL
INPUTS
15
R* = 2 TO 10 k
VDD = 5 V
13
VCC = 5 TO 12 V
16
14
ANALOG
SIGNALS
HC4066A
5
7
ANALOG
SIGNALS
MC14504
11
14
CONTROL
INPUTS
10
15
14
CHANNEL 4
1 OF 4
SWITCHES
CHANNEL 3
1 OF 4
SWITCHES
CHANNEL 2
1 OF 4
SWITCHES
CHANNEL 1
1 OF 4
SWITCHES
COMMON I/O
INPUT
1 OF 4
SWITCHES
OUTPUT
LF356 OR
EQUIVALENT
0.01 F
1
2
3 4
CONTROL INPUTS
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MC74HC4316A
Product Preview
Quad Analog Switch/
Multiplexer/Demultiplexer
with Separate Analog and
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MARKING
DIAGRAMS
16
YA
15
YB
14
XB
B ON/OFF
CONTROL
C ON/OFF
CONTROL
ENABLE
13
VCC
A ON/OFF
CONTROL
D ON/OFF
CONTROL
XD
12
YD
11
YC
10
XC
GND
VEE
FUNCTION TABLE
Inputs
On/Off
Enable
Control
L
L
H
H
L
X
State of
Analog
Switch
16
PDIP16
P SUFFIX
CASE 648
HC4316AN
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
HC4316AD
AWLYWW
1
16
HC43
16A
ALYW
TSSOP16
DT SUFFIX
CASE 948F
1
16
SOEIAJ16
F SUFFIX
CASE 966
74HC4316A
AWLYWW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Package
Shipping
MC74HC4316AN
Device
PDIP16
2000 / Box
MC74HC4316AD
SOIC16
48 / Rail
MC74HC4316ADR2
SOIC16
2500 / Reel
MC74HC4316ADT
TSSOP16
96 / Rail
MC74HC4316ADTR2
TSSOP16
2500 / Reel
MC74HC4316AF
SOEIAJ14
See Note 1.
On
Off
Off
X = dont care
350
MC74HC4316A
LOGIC DIAGRAM
XA
A ON/OFF CONTROL
XB
B ON/OFF CONTROL
XC
C ON/OFF CONTROL
XD
D ON/OFF CONTROL
ENABLE
1
15
YB
ANALOG
OUTPUTS/INPUTS
ANALOG
SWITCH
11
ANALOG
SWITCH
12
YC
LEVEL
TRANSLATOR
13
14
ANALOG
SWITCH
YA
LEVEL
TRANSLATOR
10
6
LEVEL
TRANSLATOR
4
5
ANALOG
SWITCH
PIN 16 = VCC
PIN 8 = GND
PIN 9 = VEE
GND VEE
YD
LEVEL
TRANSLATOR
ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
0.5 to + 7.0
0.5 to + 14.0
7.0 to + 0.5
VIS
VEE 0.5
to VCC + 0.5
Vin
VCC
VEE
(Ref. to GND)
(Ref. to VEE)
25
mA
PD
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_C
TL
Plastic DIP
EIAJ/SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
EIAJ/SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
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351
MC74HC4316A
Parameter
Min
Max
Unit
VCC
2.0
6.0
VEE
6.0
GND
VIS
VEE
VCC
Vin
GND
VCC
1.2
55
+ 125
_C
0
0
0
0
1000
600
500
400
ns
VIO*
TA
tr, tf
VCC = 2.0 V
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may
be drawn; i.e., the current out of the switch may contain both VCC and switch input
components. The reliability of the device will be unaffected unless the Maximum Ratings are
exceeded.
v
v
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted
Guaranteed Limit
55 to
25_C
85_C
125_C
Symbol
Parameter
VIH
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
VIL
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
Iin
6.0
0.1
1.0
1.0
6.0
6.0
2
4
20
40
40
160
ICC
Test Conditions
VCC
V
Unit
VEE = GND
VEE = 6.0
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
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352
MC74HC4316A
v
v
Guaranteed Limit
VCC
V
VEE
V
55 to
25_C
Vin = VIH
VIS = VCC to VEE
IS
2.0 mA (Figures 1, 2)
2.0*
45
4.5
6.0
0.0
0.0
4.5
6.0
Vin = VIH
VIS = VCC or VEE (Endpoints)
IS
2.0 mA (Figures 1, 2)
2.0
4.5
4.5
6.0
Maximum Difference in ON
Resistance Between Any Two
Channels in the Same Package
Vin = VIH
VIS = 1/2 (VCC VEE)
IS
2.0 mA
Ioff
Maximum OffChannel
Leakage Current, Any One
Channel
Ion
Maximum OnChannel
Leakage Current, Any One
Channel
Symbol
Ron
Ron
Parameter
85_C
125_C
160
90
90
200
110
110
240
130
130
0.0
0.0
4.5
6.0
90
70
70
115
90
90
140
105
105
2.0
4.5
4.5
6.0
0.0
0.0
4.5
6.0
20
15
15
25
20
20
30
25
25
Vin = VIL
VIO = VCC or VEE
Switch Off (Figure 3)
6.0
6.0
0.1
0.5
1.0
Vin = VIH
VIS = VCC or VEE
(Figure 4)
6.0
6.0
0.1
0.5
1.0
Test Conditions
Maximum ON Resistance
Unit
*At supply voltage (VCC VEE) approaching 2 V the analog switchon resistance becomes extremely nonlinear. Therefore, for lowvoltage
operation, it is recommended that these devices only be used to control digital signals.
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book
(DL129/D).
v
v
Guaranteed Limit
VCC
V
55 to
25_C
85_C
125_C
tPLH,
tPHL
2.0
4.5
6.0
40
6
5
50
8
7
60
9
8
ns
tPLZ,
tPHZ
2.0
4.5
6.0
130
40
30
160
50
40
200
60
50
ns
tPZL,
tPZH
2.0
4.5
6.0
140
40
30
175
50
40
250
60
50
ns
Maximum Capacitance
10
10
10
pF
35
1.0
35
1.0
35
1.0
Symbol
Parameter
ON/OFF Control
and Enable Inputs
Unit
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
15
pF
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
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353
MC74HC4316A
VCC
V
VEE
V
Limit*
25_C
2.25
4.50
6.00
2.25
4.50
6.00
150
160
160
MHz
fin
Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 , CL = 50 pF
2.25
4.50
6.00
2.25
4.50
6.00
50
50
50
dB
2.25
4.50
6.00
2.25
4.50
6.00
40
40
40
Vin
1 MHz Square Wave (tr = tf = 6 ns)
Adjust RL at Setup so that IS = 0 A
RL = 600 , CL = 50 pF
2.25
4.50
6.00
2.25
4.50
6.00
60
130
200
RL = 10 k, CL = 10 pF
2.25
4.50
6.00
2.25
4.50
6.00
30
65
100
fin
Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600 , CL = 50 pF
2.25
4.50
6.00
2.25
4.50
6.00
70
70
70
2.25
4.50
6.00
2.25
4.50
6.00
80
80
80
Symbol
Parameter
Test Conditions
BW
THD
fin = 1 kHz, RL = 10 k, CL = 50 pF
THD = THDMeasured THDSource
VIS = 4.0 VPP sine wave
VIS = 8.0 VPP sine wave
VIS = 11.0 VPP sine wave
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354
Unit
mVPP
dB
2.25
4.50
6.00
2.25
4.50
6.00
0.10
0.06
0.04
MC74HC4316A
TBD
TBD
TBD
TBD
PLOTTER
PROGRAMMABLE
POWER
SUPPLY
TBD
MINI COMPUTER
DC ANALYZER
VCC
DEVICE
UNDER TEST
ANALOG IN
COMMON OUT
GND
VEE
MC74HC4316A
VCC
VCC
16
VEE
VCC
16
A
VCC
OFF
VCC
N/C
ON
O/I
VEE
VIL
VIH
7
8
9
SELECTED
CONTROL
INPUT
7
8
9
SELECTED
CONTROL
INPUT
VEE
VEE
VIS
VCC
16
fin
VCC
RL
VCC
16
TO dB
METER
ON
0.1 F
TO dB
METER
OFF
0.1 F
CL*
RL
7
8
9
fin
VCC
RL
RL
7
8
9
SELECTED
CONTROL
INPUT
SELECTED
CONTROL
INPUT
VEE
VEE
CL*
VCC
16
TEST
POINT
ON/OFF
RL
7
8
9
VEE
RL
VCC
CL*
ANALOG IN
SELECTED
CONTROL
INPUT
50%
GND
tPHL
tPLH
CONTROL
ANALOG OUT
50%
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356
MC74HC4316A
VCC
16
ANALOG I/O
tr
ANALOG O/I
TEST
POINT
ON
tf
ENABLE
VCC
50%
CONTROL
50 pF*
GND
tPLZ
tPZL
7
8
9
SELECTED
CONTROL
INPUT
VCC
HIGH
IMPEDANCE
50%
ANALOG
OUT
tPZH
tPHZ
10%
VOL
90%
VOH
50%
HIGH
IMPEDANCE
VIS
1
2
fin
VCC
VCC
1
RL
ON
CL*
TEST
POINT
ON/OFF
16
0.1 F
1 k
16
VCC
RL
ANALOG I/O
50 pF*
TEST
POINT
OFF
CONTROL
OR
ENABLE
7
8
9
8
9
VEE
RL
CL*
VCC
SELECTED
CONTROL
INPUT
VCC
A
VIS
VCC
16
N/C
ON/OFF
10 F
N/C
VOS
16
fin
ON
RL
7
8
9
VEE
SELECTED
CONTROL
INPUT
7
8
9
VEE
CONTROL
SELECTED
CONTROL
INPUT
CL*
TO
DISTORTION
METER
VCC
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357
MC74HC4316A
APPLICATIONS INFORMATION
0
10
FUNDAMENTAL FREQUENCY
20
dBm
30
40
50
DEVICE
60
SOURCE
70
80
90
100
1.0
3.0
2.0
FREQUENCY (kHz)
VCC
VCC = 6 V
16
+6V
ANALOG I/O
ON
ANALOG O/I
+6V
SELECTED
CONTROL
INPUT
VEE
8
16
Dx
SELECTED
CONTROL
INPUT
Dx
Dx
+6V
ON
6 V
6 V
VCC
VCC
Dx
VEE
ENABLE CONTROL
INPUTS
(VCC OR GND)
VEE
VEE
ENABLE CONTROL
INPUTS
(VCC OR GND)
6 V
Figure 16.
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358
MC74HC4316A
VCC = 5 V
+5 V
16
ANALOG
SIGNALS
16
ANALOG
SIGNALS
ANALOG
SIGNALS
ANALOG
SIGNALS
R* R* R* R* R*
HC4316A
7
5
6
14
15
TTL
HCT
BUFFER
VEE = 0
TO 6 V
LSTTL/
NMOS
ENABLE
AND
CONTROL 9
INPUTS
8
HC4016A
6
14
VEE = 0
TO 6 V
CONTROL
INPUTS 9
15
R* = 2 TO 10 k
VCC = 12 V
R1
12 V
POWER
SUPPLY
GND = 6 V
R2
VEE = 0 V
R1 = R2
VCC
12 VPP
ANALOG
INPUT
SIGNAL
R3
C
1 OF 4
SWITCHES
ANALOG
OUTPUT
SIGNAL
12 V
0
R4
VEE
R1 = R2
R3 = R4
CHANNEL 4
1 OF 4
SWITCHES
CHANNEL 3
1 OF 4
SWITCHES
CHANNEL 2
1 OF 4
SWITCHES
CHANNEL 1
1 OF 4
SWITCHES
COMMON I/O
INPUT
1 OF 4
SWITCHES
OUTPUT
LF356 OR
EQUIVALENT
0.01 F
1
2
3 4
CONTROL INPUTS
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359
MC74HC4538A
Dual Precision
Monostable Multivibrator
(Retriggerable, Resettable)
The MC74HC4538A is identical in pinout to the MC14538B. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LSTTL outputs.
This dual monostable multivibrator may be triggered by either the
positive or the negative edge of an input pulse, and produces a
precision output pulse over a wide range of pulse widths. Because the
device has conditioned trigger inputs, there are no triggerinput rise
and fall time restrictions. The output pulse width is determined by the
external timing components, Rx and Cx. The device has a reset
function which forces the Q output low and the Q output high,
regardless of the state of the output pulse circuitry.
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MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
16
1
1
16
SO16
D SUFFIX
CASE 751B
16
HC4538A
AWLYWW
1
A
WL
YY
WW
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN ASSIGNMENT
GND
16
CX1/RX1
RESET 1
15
14
LOGIC DIAGRAM
CX1
MC74HC4538AN
AWLYYWW
RX1
VCC
GND
CX2/RX2
RESET 2
A1
13
B1
12
A2
Q1
11
B2
Q1
10
Q2
GND
Q2
VCC
1
FUNCTION TABLE
Inputs
6
TRIGGER A1
INPUTS B1 5
RESET 1
Reset
Q1
H
H
H
H
X
H
L
X
Not Triggered
Not Triggered
H
H
L,H,
L
H
L,H,
Not Triggered
Not Triggered
X
X
X
X
L
H
Not Triggered
3
CX2
RX2
VCC
15
TRIGGER
INPUTS
A2
B2
14
12
10
11
Outputs
Q1
Q2
Q2
ORDERING INFORMATION
PIN 16 = VCC
13
RESET 2
PIN 8 = GND
RX AND CX ARE EXTERNAL COMPONENTS
PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND
Device
360
Package
Shipping
MC74HC4538AN
PDIP16
2000 / Box
MC74HC4538AD
SOIC16
48 / Rail
MC74HC4538ADR2
SOIC16
2500 / Reel
MC74HC4538A
MAXIMUM RATINGS*
Symbol
VCC
Parameter
Value
Unit
0.5 to + 7.0
V
V
Vin
Vout
Iin
A, B, Reset
Cx, Rx
20
30
mA
Iout
25
mA
ICC
50
mA
PD
750
500
mW
Tstg
Storage Temperature
65 to + 150
_C
TL
Plastic DIP
SOIC Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
Vin, Vout
Parameter
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
A or B (Figure 5)
Rx
Cx
Min
Max
Unit
3.0**
6.0
VCC
55
+ 125
_C
0
0
0
1000
500
400
ns
No Limit
1.0
2.0
*
*
* The maximum allowable values of Rx and Cx are a function of the leakage of capacitor Cx, the leakage of the HC4538A, and leakage due
to board layout and surface resistance. For most applications, Cx/Rx should be limited to a maximum value of 10 F/1.0 M. Values of Cx
> 1.0 F may cause a problem during power down (see Power Down Considerations). Susceptibility to externally induced noise signals may
occur for Rx > 1.0 M.
** The HC4538A will function at 2.0 V but for optimum pulse width stability, VCC should be above 3.0 V.
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
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361
MC74HC4538A
v
v
v
v
Guaranteed Limits
Symbol
Parameter
Test Conditions
55 to
25_C
VCC
Volts
Min
1.5
3.15
4.2
Max
85_C
Min
Max
Min
Max
VIH
Minimum HighLevel
Input Voltage
2.0
4.5
6.0
VIL
Maximum LowLevel
Input Voltage
2.0
4.5
6.0
VOH
Minimum HighLevel
Output Voltage
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
VOL
Maximum LowLevel
Output Voltage
1.5
3.15
4.2
125_C
0.5
1.35
1.8
1.5
3.15
4.2
0.5
1.35
1.8
Unit
V
0.5
1.35
1.8
Iin
Maximum Input
Leakage Current
(A, B, Reset)
6.0
0.1
1.0
1.0
Iin
Maximum Input
Leakage Current
(Rx, Cx)
6.0
50
500
500
nA
ICC
Maximum Quiescent
Supply Current
(per package)
Standby State
6.0
130
220
350
ICC
Maximum Supply
Current
((per
er package)
ackage)
Active State
25_C
6.0
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362
400
45_C to
85_C
600
55_C to
125_C
800
MC74HC4538A
v
v
Guaranteed Limits
Symbol
VCC
Volts
85_C
125_C
Max
Unit
tPLH
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPHL
2.0
4.5
6.0
195
39
33
245
49
42
295
59
50
ns
tPHL
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tPLH
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tTLH
tTHL
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
10
25
10
25
10
25
pF
Cin
Parameter
55 to
25_C
(A. B, Reset)
(Cx, Rx)
Min
Max
Min
Max
Min
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola
HighSpeed CMOS Data Book (DL129/D).
Typical @ 25C, VCC = 5.0 V
CPD
pF
150
* Used to determine the noload dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
v
v
Guaranteed Limits
55 to
25_C
85_C
125_C
VCC
Volts
Min
2.0
4.5
6.0
0
0
0
0
0
0
0
0
0
ns
tw
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
tw
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
2.0
4.5
6.0
A or B
(Figure 7)
2.0
4.5
6.0
Symbol
trec
tr, tf
Parameter
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363
Max
1000
500
400
Min
Max
1000
500
400
No Limit
Min
Max
1000
500
400
Unit
ns
MC74HC4538A
v
v
Symbol
Parameter
Guaranteed Limits
55 to
25_C
85_C
125_C
Timing Components
VCC
Volts
Min
Max
Min
Max
Min
Max
Unit
Rx = 10 k, Cx = 0.1 F
5.0
0.63
0.77
0.6
0.8
0.59
0.81
ms
5.0
10
10 s
0.8
TA = 25C
1s
OUTPUT PULSE WIDTH ( )
0.7
0.6
0.5
0.4
0.3
3
4
5
6
VCC, POWER SUPPLY VOLTAGE (VOLTS)
VCC = 5 V, TA = 25C
100 ms
10 ms
1 ms
100 s
1 M
10 s 100 k
1 s
10 k
1 k
100 ns
0.00001 0.0001
0.001
0.01
0.1
CAPACITANCE (F)
1.1
TA = 25C
Rx = 100 k
Cx = 1000 pF
1
0.9
0.8
Rx = 1 M
Cx = 0.1 F
0.7
0.6
0.5
10
*For output pulse widths greater than 100 s, typically = kRxCx, where the value of k may be found in Figure 1.
3
4
5
6
VCC, POWER SUPPLY VOLTAGE (VOLTS)
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364
100
MC74HC4538A
1.1
1.05
1
VCC = 6 V
0.95
Rx = 10 k
Cx = 0.1 F
0.9
0.85
VCC = 3 V
0.8
75
50
25
25
50
75
100
125
150
125
150
1.03
Rx = 10 k
Cx = 0.1 F
1.02
1.01
1
VCC = 5.5 V
0.99
VCC = 5 V
0.98
VCC = 4.5 V
0.97
75
50
25
25
50
75
100
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365
MC74HC4538A
SWITCHING WAVEFORMS
tw(H)
VCC
50%
GND
A
tw(L)
VCC
B
50%
GND
tPLH
tPLH
50%
Q
tPHL
tPHL
Q
50%
tr
Figure 6.
tf
VCC
90%
10%
GND
trr
VCC
50%
GND
B
tf
tf
RESET
10%
tw(L)
tTLH
GND
trec
+ trr
tPHL
90%
50%
50%
10%
Q
tTHL
Q
VCC
90%
50%
tPLH
90%
10%
50%
Figure 7.
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
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366
(RETRIGGERED PULSE)
MC74HC4538A
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 4, 12)
OUTPUTS
Q1, Q2 (Pins 6, 10)
Q1, Q2 (Pins 7, 9)
LOGIC DETAIL
(1/2 THE DEVICE)
RxCx
UPPER
REFERENCE
CIRCUIT
+
Vre, UPPER
VCC
VCC
OUTPUT
LATCH
LOWER
REFERENCE
CIRCUIT
M1
2 k
M2
Vre, LOWER
M3
TRIGGER CONTROL
CIRCUIT
A
Q
TRIGGER CONTROL
RESET CIRCUIT
CB R
RESET
POWER
ON
RESET
RESET LATCH
Figure 9.
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367
MC74HC4538A
CIRCUIT OPERATION
TRIGGER OPERATION
QUIESCENT STATE
QUIESCENT
STATE
TRIGGER CYCLE
(A INPUT)
TRIGGER CYCLE
(B INPUT)
RESET
RETRIGGER
trr
TRIGGER INPUT A
(PIN 4 OR 12)
TRIGGER INPUT B
(PIN 5 OR 11)
8
24
TRIGGER-CONTROL
CIRCUIT OUTPUT
14
11
RX/CX INPUT
(PIN 2 OR 14)
15
21
17
23
12
Vref LOWER
5
UPPER REFERENCE
CIRCUIT
Vref UPPER
13
25
18
13
LOWER REFERENCE
CIRCUIT
16
RESET INPUT
(PIN 3 OR 13)
20
1
RESET LATCH
22
10
Q OUTPUT
(PIN 6 OR 10)
19
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368
+ trr
MC74HC4538A
occurs, the output of the reset latch goes low (#22), turning
on transistor M1. Thus Cx is allowed to quickly charge up to
VCC (#23) to await the next trigger signal.
On power up of the HC4538A the poweron reset circuit
will be high causing a reset condition. This will prevent the
triggercontrol circuit from accepting a trigger input during
this state. The HC4538As Q outputs are low and the Q not
outputs are high.
RETRIGGER OPERATION
DX
CX
VCC
RX
A
B
RESET
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369
MC74HC4538A
TYPICAL APPLICATIONS
CX
RX
RX
CX
RISINGEDGE
TRIGGER
RISINGEDGE
TRIGGER
VCC
Q
A
B
VCC
Q
A
Q
B = VCC
RESET = VCC
CX
RESET = VCC
RX
CX
VCC
A = GND
VCC
Q
Q
B
FALLINGEDGE
TRIGGER
RX
A
B
FALLINGEDGE
TRIGGER
RESET = VCC
RESET = VCC
GND
N/C
A = GND
VCC
RXCX
Q
N/C
B
Q
RESET
N/C
1 s
10 s 100 s 1 ms 10 ms 100 ms
1s
10 s
23 HR
5 MIN
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370
MC74HC4851A,
MC74HC4852A
Analog Multiplexers/
Demultiplexers with
Injection Current Effect
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Control
Automotive Customized
These devices are pin compatible to standard HC405x and
MC1405xB analog mux/demux devices, but feature injection current
effect control. This makes them especially suited for usage in
automotive applications where voltages in excess of normal logic
voltage are common.
The injection current effect control allows signals at disabled analog
input channels to exceed the supply voltage range without affecting
the signal of the enabled analog channel. This eliminates the need for
external diode/ resistor networks typically used to keep the analog
channel signals within the supply voltage range.
The devices utilize low power silicon gate CMOS technology. The
Channel Select and Enable inputs are compatible with standard CMOS
outputs.
Injection Current CrossCoupling Less than 1mV/mA (See Figure 9)
Pin Compatible to HC405X and MC1405XB Devices
Power Supply Range (VCC GND) = 2.0 to 6.0 V
In Compliance With the Requirements of JEDEC Standard No. 7A
Chip Complexity: 154 FETs or 36 Equivalent Gates
MARKING
DIAGRAMS
16
PDIP16
N SUFFIX
CASE 648
HC485xAN
AWLYYWW
1
16
SOIC16
D SUFFIX
CASE 751B
HC485xAD
AWLYWW
1
16
SOIC16 WIDE
DW SUFFIX
CASE 751G
HC485xADW
AWLYWW
1
16
TSSOP16
DT SUFFIX
CASE 948F
HC48
5xA
ALYW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 380 of this data sheet.
371
MC74HC4851A, MC74HC4852A
FUNCTION TABLE MC74HC4851A
Control Inputs
13
X0
14
X1
15
X2
ANALOG
12
MULTIPLEXER/
INPUTS/ X3
DEMULTIPLEXER
OUTPUTS X4 1
5
X5
2
X6
4
X7
11
A
CHANNEL
10
B
SELECT
9
INPUTS
C
6
ENABLE
PIN 16 = VCC
PIN 8 = GND
Select
B
A
ON Channels
Enable
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
X2
X1
X0
X3
15
14
13
12
11
10
COMMON
OUTPUT/
INPUT
VCC
16
L
H
L
H
L
H
L
H
X
X0
X1
X2
X3
X4
X5
X6
X7
NONE
X4
X6
X7
X5
Enable NC
8
GND
ON Channels
L
L
L
L
H
L
L
H
H
X
L
H
L
H
X
Y0
Y1
Y2
Y3
12
ANALOG
INPUTS/OUTPUTS
CHANNEL-SELECT
INPUTS
X0
14
X1
15
X2
11
X3
Y0
Y1
Y2
Y3
A
B
ENABLE
X SWITCH
13
X
COMMON
OUTPUTS/INPUTS
Y SWITCH
VCC
16
10
9
NONE
X = Dont Care
5
2
X0
X1
X2
X3
PIN 16 = VCC
PIN 8 = GND
X2
X1
X0
X3
15
14
13
12
11
10
8
GND
Y0
Y2
Y3
Y1
Enable NC
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372
MC74HC4851A, MC74HC4852A
MAXIMUM RATINGS*
Symbol
Value
Unit
VCC
(Referenced to GND)
0.5 to + 7.0
Vin
(Referenced to GND)
25
mA
750
500
450
mW
65 to + 150
_C
Parameter
PD
Tstg
TL
Plastic DIP
SOIC Package
TSSOP Package
_C
260
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating Plastic DIP: 10 mW/_C from 65_ to 125_C
SOIC Package: 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
Parameter
Min
Max
Unit
VCC
(Referenced to GND)
2.0
6.0
Vin
(Referenced to GND)
GND
VCC
0.0
1.2
55
+ 125
_C
0
0
0
1000
500
400
ns
VIO*
TA
tr, tf
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
*For voltage drops across switch greater than 1.2V (switch on), excessive VCC current may be
drawn; i.e., the current out of the switch may contain both VCC and switch input components.
The reliability of the device will be unaffected unless the Maximum Ratings are exceeded.
DC CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND, Except Where Noted
55 to 25C
85C
125C
Unit
Symbol
Parameter
VIH
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
VIL
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
Iin
6.0
0.1
1.0
1.0
6.0
20
40
ICC
Condition
Guaranteed Limit
VCC
V
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
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373
MC74HC4851A, MC74HC4852A
DC CHARACTERISTICS Analog Section
Guaranteed Limit
Condition
VCC
55 to 25C
85C
125C
Unit
Maximum ON Resistance
2.0
3.0
4.5
6.0
1700
1100
550
400
1750
1200
650
500
1800
1300
750
600
Delta ON Resistance
2.0
3.0
4.5
6.0
300
160
80
60
400
200
100
80
500
240
120
100
0.1
0.2
0.5
2.0
1.0
4.0
0.2
2.0
4.0
VCC
55 to 25C
85C
125C
Unit
2.0
3.0
4.5
6.0
160
80
40
30
180
90
45
35
200
100
50
40
ns
2.0
3.0
4.5
6.0
260
160
80
60
280
180
90
70
300
200
100
80
ns
10
35
130
10
35
130
10
35
130
pF
Symbol
Ron
Ron
Ioff
Ion
Parameter
Parameter
tPHL,
tPLH
tPHL, tPHZ,PZH
tPLH, tPLZ,PZL
Cin
CPD
Digital Pins
Any Single Analog Pin
Common Analog Pin
Typical
5.0
20
pF
Parameter
Maximum Shift of Output Voltage of Enabled Analog
Channel
Typ
Max
Unit
0.1
1.0
0.5
5.0
1.0
5.0
2.0
20
mV
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374
Condition
Iin* 1mA, RS 3,9k
Iin* 10mA, RS 3,9k
Iin* 1mA, RS 20k
Iin* 10mA, RS 20k
MC74HC4851A, MC74HC4852A
1100
1000
R on , ON RESISTANCE (OHMS)
900
55C
800
+25C
700
+125C
600
500
400
300
200
R on , ON RESISTANCE (OHMS)
1100
1000
100
800
700
600
500
55C
400
+25C
300
+125C
200
100
0
0.0
0.4
0.8
1.2
1.6
0
0.0
2.0
1.2
1.8
2.4
660
440
600
400
540
360
480
420
360
55C
300
+25C
240
+125C
180
55C
280
160
120
40
2.7
3.6
+125C
200
60
1.8
+25C
240
80
0.9
0
0.0
4.5
1.2
2.4
3.6
4.8
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375
3.0
320
120
0
0.0
0.6
R on , ON RESISTANCE (OHMS)
R on , ON RESISTANCE (OHMS)
900
6.0
MC74HC4851A, MC74HC4852A
VCC = 5V
Iin
Vin2 < VSS or VCC < Vin2
Any Disabled Channel
VSS < Vin1 < VCC
Enabled Channel
RS
5V
6V
5V
HC4051A
Sensor
VCC
VCC
Microcontroller
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
(8x Identical Circuitry)
Common Out
A/D Input
5V
VCC
HC4851A
Sensor
VCC
Microcontroller
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Channel 8
(8x Identical Circuitry)
Common Out
A/D Input
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376
MC74HC4851A, MC74HC4852A
PLOTTER
VCC
PROGRAMMABLE
POWER
SUPPLY
MINI COMPUTER
DC ANALYZER
16
VEE
VCC
OFF
VCC
VCC
COMMON O/I
OFF
NC
DEVICE
UNDER TEST
ANALOG IN
VIH
COMMON OUT
6
8
GND
VCC
16
VEE
ANALOG I/O
16
OFF
VCC
OFF
VIH
VCC
VCC
VCC
ON
VEE
COMMON O/I
VCC
N/C
ANALOG I/O
VIL
COMMON O/I
OFF
VCC
16
VCC
VCC
CHANNEL
SELECT
ON/OFF
50%
OFF/ON
GND
tPLH
ANALOG
OUT
COMMON O/I
ANALOG I/O
TEST
POINT
CL*
tPHL
6
50%
8
CHANNEL SELECT
*Includes all probe and jig capacitance
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377
MC74HC4851A, MC74HC4852A
VCC
16
ANALOG
IN
COMMON O/I
ANALOG I/O
VCC
ON
50%
TEST
POINT
CL*
GND
tPHL
tPLH
ANALOG
OUT
6
8
50%
tf
tr
tPZL
VCC
90%
50%
10%
ENABLE
ANALOG
OUT
2
GND
tPLZ
HIGH
IMPEDANCE
CL*
tPZH tPHZ
ANALOG
OUT
TEST
POINT
ON/OFF
VOL
ENABLE
VOH
90%
10k
ANALOG I/O
50%
10%
VCC
16
VCC
50%
6
8
HIGH
IMPEDANCE
VCC
A
VCC
16
COMMON O/I
ON/OFF
NC
ANALOG I/O
OFF/ON
VCC
6
8
11
CHANNEL SELECT
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378
MC74HC4851A, MC74HC4852A
Gate = VCC
(Disabled)
+
+
+
N Substrate (on VCC potential)
ENABLE
11
10
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379
INJECTION
CURRENT
CONTROL
13
INJECTION
CURRENT
CONTROL
14
INJECTION
CURRENT
CONTROL
15
INJECTION
CURRENT
CONTROL
12
INJECTION
CURRENT
CONTROL
INJECTION
CURRENT
CONTROL
INJECTION
CURRENT
CONTROL
INJECTION
CURRENT
CONTROL
INJECTION
CURRENT
CONTROL
X0
X1
X2
X3
X4
X5
X6
X7
MC74HC4851A, MC74HC4852A
ENABLE
10
INJECTION
CURRENT
CONTROL
13
INJECTION
CURRENT
CONTROL
14
INJECTION
CURRENT
CONTROL
15
INJECTION
CURRENT
CONTROL
12
INJECTION
CURRENT
CONTROL
13
INJECTION
CURRENT
CONTROL
INJECTION
CURRENT
CONTROL
INJECTION
CURRENT
CONTROL
INJECTION
CURRENT
CONTROL
INJECTION
CURRENT
CONTROL
Shipping
MC74HC4851AN
Device
PDIP16
MC74HC4851AD
SOIC16
48 Units / Rail
MC74HC4851ADR2
SOIC16
MC74HC4851ADW
SOIC16 WIDE
48 Units / Rail
MC74HC4851ADWR2
SOIC16 WIDE
MC74HC4851ADT
TSSOP16
96 Units / Rail
MC74HC4851ADTR2
TSSOP16
MC74HC4852AN
PDIP16
MC74HC4852AD
SOIC16
48 Units / Rail
MC74HC4852ADR2
SOIC16
MC74HC4852ADW
SOIC16 WIDE
48 Units / Rail
MC74HC4852ADWR2
SOIC16 WIDE
MC74HC4852ADT
TSSOP16
96 Units / Rail
MC74HC4852ADTR2
TSSOP16
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380
X0
X1
X2
X3
Y0
Y1
Y2
Y3
CHAPTER 4
Application Notes
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381
AN1410/D
Configuring and Applying
the MC74HC4046A
Phase-Locked Loop
A versatile device for 0.1 to 16MHz
frequency synchronization
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APPLICATION NOTE
Prepared by: Cleon Petty, Gary Tharalson & Marten Smith
Logic Application Engineers
Abstract
Phase Detector
Ref Osc
VCO
fo
Feedback
N
dt
(1)
or,
+ c dV
dt
Fo
and Fo
1
2CdV
+ 2dt1
I
+ 2CdV
(4)
(2)
+ dV CI
I1
in
+ VCO
R1
120
5
(5)
(3)
382
AN1410/D
I2 is set by R2 and adds a constant current to limit the Fo min
of the VCO and is a function of Vdd, R2, and an internal
current mirror of ratio 23/5, resulting in the equation:
I2
2Vdd
3R2
23
5
(6)
)
2Vdd
3R2
VCOin 120
5
R1
VCOin
(24)
R1
3VCOin
(24)
R1
2Cext
Vdd
3
2Vdd
3R2
23
5
(4.6)
Fo
2Vdd
(4.6)
R2
(7)
2Cext Vdd
Fo
+ 2C
&
ext (Vdd
3VCOin(Iconstant ratio)
R1
9.2(Vdd)
R2
(3)(1)(31)
300K
2Vdd
(4.6)
R2
) 3 * undershoot)
)
+ 2C (V
ext dd ) 3 * undershoot)
+ 235Hz
13.5
17.5
21.5
23.0
24.0
26.5
27.0
28.5
29.0
31.0
V
2Cext 3dd
Iconstant ratio
VCO gain
(8)
max * f min
+ VCO f max
* VCOin min
in
+ Dfreqvolt
(9)
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383
AN1410/D
Fo min
Fo max
(3)(0.25)(21.5)
9.1K
R1
(3)(2.5)(21.5)
9.1K
60.11 * 106
+ 1.3 * 102.50.25
+ 528.9KHzV
The design of low pass filters is well known and the intent
here is to simply show some typical examples. Reference
should be made to the HC4046A Data Sheet and to
Application Note AN535/D PhaseLocked Loop
Fundamentals (available through ON Semiconductor
Literature Distribution).
Some simple types of low pass filters are shown in
Figure 2 and Figure 3.
(Vdd)
+ 2C (R2) (V9.2
dd ) 3 * undershoot)
Cext (pF)
3.0K R1 9.0K
9.1K R1 50K
50K R1 900K
0 Cext 30
30 Cext 150
150 Cext
7.50/Fo
5.77/Fo
5.28/Fo
0 Cext 30
30 Cext 150
150 Cext
9.00/Fo
6.92/Fo
6.34/Fo
VCOin
C1
KKVCO
NC1R1
n
+ K0.5w
KVCO
R1
R2
(R1)(Cext)
5.40/Fo
4.15/Fo
3.80/Fo
VCOin
wn
0 Cext 30
30 Cext 150
150 Cext
R1
C1
2. (R1)(Cext) versus Fo
R1 ()
+ 15.28
+ 5.28 * 10-6
* 106
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384
KKVCO
NC1(R1 R2)
+ 0.5wn(R2C1 ) KKNVCO)
( 10 )
AN1410/D
Figure 4 shows an active filter using an op amp from
Application Note AN535/D.
R1
det
(K)
Ref Osc
Fref
LP Filter
wn
KVCO
fo
C1
Feedback
N
R1
det Charge
Pump Output
OP
AMP
VCOin
KKVCO
NC1R1
( 11 )
R2
+ K2wKVCO
nNR1
( 12 )
) R2 + KNCKVCO
w 2
( 13 )
R2
* N
+ C2d
1wn C1(KKVCO)
( 14 )
C1
+ Nw K2(RKVCO
)R
C1
* N
+ R2d
2wn R2(KKVCO)
1 n
(R1)(Cext)
+ 1.15.77
+ 5.245 * 10-6
* 106
, or alternatively,
2)
Cext
Cext
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385
AN1410/D
The final values used for the desired frequency range are
R1 = 42k, Cext = 175pF, R2 = , VCOin max = 2.75V, and
VCOin min = 0.25V.
The next step is to determine the loop filter. Choosing a
filter like the one in Figure 3, calculate the component as
follows:
Fo min
) R
+ (2)(125 * 10-12f) [5.0V
) 3(0.57V)]
(3)(0.25)(27)
42K
(9.2) (5.0)
20.25
+ 70.455
+ 287.4KHz
* 10-6
Fo max
(3)(2.75)(27)
42K
222.75
70.455 * 10-6
) 3(0.57V)]
Fo min
where
K = phase detector gain
Vdd = output swing
Fmax is > the required 2.0MHz, but the Fmin is not low
enough for required application. It is necessary to adjust
either Cext or R1 to achieve required specification of 0.2 to
2.0MHz Fo. Since R1 = 42k is a standard resistor value, try
adjusting Cext to a higher value, such as 175pF. Because Cext
is now > 150pF, the Vundershoot must be adjusted to 0.7V, as
per earlier explanation:
So,
wn
N = 2 to 20
+ 3.16MHz
R2
+ 2250.52514.4 + 1736W
(9.2) (5.0)
) 3(0.7V)]
222.75
+ 104.37
+ 2.13MHz
* 10-6
* f min
* VCOin min
KVCO
KVCO
f max
VCOin max
+ C2d
* N
1wn C1(KKVCO)
10
+ (0.01 (2)(0.707)
and
(3)(2.75)(27)
42K
1 n
0
(9.2) (5.0)
20.25
+ 104.37
+ 194.02KHz
* 10-6
Fo max
(0.4)(4.86 * 106)
) R2 + KNCKVCO
+
2
w
(10)(0.01 * 10-6)(62.83 * 103)2
* 106 + 4924.5W
+ 1.944
394.76
+ V4ddp + 5.0
+ 0.4Vrad
4p
(9.2) (5.0)
wn min
+
+
KKVCO
NC1(R1 R2)
(0.4)(4.86 * 106)
(20)(0.01 * 10-6)(3188.5
) 1736)
+ 44.43 * 103radsec, or
+ 44.43 * 103radsec [ 7KHz
or in radians
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386
AN1410/D
and
+ (0.5)(wn)
d min
R2C1
) KKNVCO
and
d max
(0.5)(44.43 * 103) *
(1736)(0.01 * 10-6)
20
) (0.4)(4.86
* 106)
(1736)(0.01 * 10-6)
wn max
2
) (0.4)(4.86
* 106)
+ 1.292
This shows the effect of changing n on loop performance and
for this application is adequate.
If the components are not what is desired, choosing a
different wn and/or d allows them to be modified.
Alternatively, picking different C, R1 or R2 and
recalculating the other parameters can be done. If the filter
does not provide adequate performance, making wn smaller
or d larger may improve stability.
+ 0.6144
For N = 2:
+ (0.5)(140.49 * 103) *
(0.4)(4.86 * 106)
(2)(0.01 * 10-6)(3188.5 1736)
+ 140.49 * 103radsec, or
+ 140.49 * 103radsec + 22.36KHz
2p
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387
AN1558/D
Characterization of
Retrigger Time in the
HC4538A Dual Precision
Monostable Multivibrator
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APPLICATION NOTE
Introduction
The MC74HC4538A is a monostable multivibrator
commonly used as a oneshot, or in applications that require
a pulse width of reliable dimensions. The pulse width and
the minimum retrigger time are usually well behaved over
the suggested pulsewidth range of 1s to 1 second.
However, some customers have found that in using shorter
than recommended pulse widths the retrigger time did not
behave as it had at longer pulse widths. ON Semiconductor
has done an overall characterization of the minimum
retrigger time in an investigation of this phenomenon.
The retrigger time is applicable when the device is
triggered a second time within the period of the output pulse.
When this happens, the output pulse remains high for a
period of + Trr. The earliest the part can be retriggered, or
the minimum retrigger time, is the focus of this
characterization. A trigger pulse on A or B inputs before this
minimum retrigger time would be ignored.
Ln 3
2
Ri
Cx
+ Rx
@ @ ) @@
Cx
Ln 1
Vundershoot
VCC
(Equation 2)
@ @
(Equation 1)
388
AN1558/D
CX
CX
RX
RISINGEDGE
TRIGGER
VCC
VCC
A = GND
A
B
RX
B = VCC
FALLINGEDGE
TRIGGER
RESET = VCC
RESET = VCC
LOGIC DETAIL
(1/2 THE DEVICE)
RxCx
UPPER
REFERENCE
CIRCUIT
+
Vref UPPER
VCC
VCC
OUTPUT
LATCH
LOWER
REFERENCE
CIRCUIT
M1
2 k
M2
Vref LOWER
M3
TRIGGER CONTROL
CIRCUIT
A
Q
TRIGGER CONTROL
RESET CIRCUIT
CB R
RESET
POWER
ON
RESET
RESET LATCH
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AN1558/D
QUIESCENT
STATE
TRIGGER CYCLE
(A INPUT)
TRIGGER CYCLE
(B INPUT)
RESET
RETRIGGER
trr
TRIGGER INPUT A
(PIN 4 OR 12)
TRIGGER INPUT B
(PIN 5 OR 11)
TRIGGER-CONTROL
CIRCUIT OUTPUT
RX/CX INPUT
(PIN 2 OR 14)
UPPER REFERENCE
CIRCUIT
LOWER REFERENCE
CIRCUIT
RESET INPUT
(PIN 3 OR 13)
RESET LATCH
Q OUTPUT
(PIN 6 OR 10)
+ trr
+ 1062.41 (0.1236764
@
@
@
(3.5256
10 *16
(7.9452
10 *11
(1.8339
10 *4
(Log Cx) 2
) (1.13509292
Rx) ) (5.9621
VCC)
Cx/Rx
10pF
100pF
220pF
1000pF
2K
4.5V
4.5V
4.5V
4.5V
10K
3.0V
4.5V
3.0V
4.5V
3.0V
4.5V
3.0V
4.5V
100K
3.0V
4.5V
3.0V
4.5V
3.0V
4.5V
3.0V
4.5V
1M
3.0V
4.5V
3.0V
4.5V
3.0V
4.5V
3.0V
4.5V
@
@
@
@ )
@
@
10 *12
(Log Cx)
10 17
Rx 2 )
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390
Rx 3 )
(4.03306325
Log Rx)
(Log Cx) 2 )
AN1558/D
1.0ms
T rr (sec)
100s
10s
1.0s
1M
100k
10K
0.1s
2K
Region 1
0.01s
1.0pF
10pF
100pF
Region 2
1000pF
Region 3
0.01F
0.1F
1.0F
10F
100F
Cx (Farad)
1.0ms
T rr (sec)
100s
10s
1.0s
1M
100k
10K
0.1s
1.0pF
Region 2
Region 1
10pF
100pF
1000pF
0.01F
Cx (Farad)
Region 3
0.1F
1.0F
10F
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391
AN1558/D
Trr = 10z,
where z
+ 315.29624(0.082881
@
@
(3.984
10 *7
(4.575
10 *10
(1.36599588
(Log Cx) 2
(Log Cx) 3 )
R x)
) (3.0657
* (1.124 10*
Cx) * (1.423 10 *
Rx 2 )
10 8
@ )
@
@ @ *
@ @ * @
@
VCC)(0.3146338
10 *12
(Log Cx)
(Log Cx)
10 16
4.3277
Rx )
Rx 2 )
(94.092747
Rx 3 )
(9.467093
Log Cx)
(Log Cx) 2 )
Rx )
+ 1.0059363(7.6336
(0.8635535
Log Cx)
10 3
VCC)
* (9.3203
@
@ @
) (0.87653815
10 *3
Log Rx
Log Rx)
Log Cx)
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392
AN1558/D
1.0E04
0.1F
T rr (sec)
1.0E05
0.01F
1.0E06
1000pF
200pF
100pF
1.0E07
10pF
1.0E08
1.0E+03
1.0E+04
1.0E+05
1.0E+06
RESISTANCE ()
1.0E03
T rr (sec)
1.0E04
0.1F
1.0E05
1000pF
200pF
0.01F
1.0E06
100pF
10pF
1.0E07
1.0E+04
1.0E+05
RESISTANCE ()
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393
1.0E+06
AN1558/D
1.0E02
1.0E03
1.0E04
1.0E05
1.0E06
1M
100k
10k
2k
1.0E07
1.0E11
1.0E09
1.0E10
1.0E08
1.0E07
Cx (Farads)
1.0E02
1.0E04
1.0E05
1.0E06
1M
100k
10k
1.0E07
1.0E11
1.0E09
1.0E10
1.0E08
Cx (Farads)
10s
1s
VCC = 5 V, TA = 25C
100ms
OUTPUT PULSE WIDTH ( )
1.0E03
10ms
1ms
100s
1 M
10s 100 k
1s
10 k
1 k
100ns
0.00001 0.0001
0.001
0.01
0.1
CAPACITANCE (F)
10
100
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394
1.0E07
AN1558/D
1.0E02
10pF
1.0E03
100pF
1.0E04
200pF
1000pF
1.0E05
0.01F
0.1F
1.0E06
1.0E07
1.0E+04
1.0E+05
1.0E+06
RESISTANCE ()
1.0E02
1.0E03
10pF
1.0E04
100pF
1.0E05
200pF
1.0E06
1000pF
0.01F
1.0E07
1.0E+03
0.1F
1.0E+05
1.0E+04
RESISTANCE ()
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395
1.0E+06
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396
CHAPTER 5
Case Outlines and Ordering Information
Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . .
Case Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ON Semiconductor Distributor and Worldwide
Sales Offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document Definitions . . . . . . . . . . . . . . . . . . . . . .
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397
398
398
405
406
VV
WWW
XXXX
Y
Package Type
D for 150 mil Plastic SOIC
DT for TSSOP
DW for 300 mil Plastic SOIC
F for 200 mil EIAJ SOIC
N for Plastic PDIP
ON Semiconductor
Circuit Identifier
Temperature Range
74 Series (55 to +125C)
Function Type
XX(X) Same Function and Pin Configuration
as LSTTL
4XXX Same Function and Pin Configuration
as CMOS 14000
7XX(X) Variation of LSTTL or CMOS 14000
Device
HighSpeed CMOS
Specification Identifier
HC = Buffered HighSpeed CMOS
HCU = Unbuffered HighSpeed CMOS*
HCT = HighSpeed CMOS TTL Compatible
*Not Available On All Devices
Case Outlines
14-Pin Packages
PDIP14
N SUFFIX
PLASTIC DIP PACKAGE
CASE 64606
ISSUE M
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
1
A
F
T
SEATING
PLANE
K
H
D 14 PL
0.13 (0.005)
M
M
http://onsemi.com
398
DIM
A
B
C
D
F
G
H
J
K
L
M
N
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.290
0.310
10_
0.015
0.039
MILLIMETERS
MIN
MAX
18.16
18.80
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.37
7.87
10_
0.38
1.01
SO14
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
A
14
P 7 PL
B
1
0.25 (0.010)
0.25 (0.010)
D 14 PL
R X 45
SEATING
PLANE
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7
0
6.20
5.80
0.50
0.25
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7
0
0.228 0.244
0.010 0.019
TSSOP14
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G01
ISSUE O
14X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE W.
N
2X
14
L/2
0.25 (0.010)
M
B
U
L
PIN 1
IDENT.
F
7
0.15 (0.006) T U
DETAIL E
K
A
V
K1
J J1
SECTION NN
W
C
0.10 (0.004)
T SEATING
PLANE
DETAIL E
http://onsemi.com
399
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
SO14 EIAJ
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96501
ISSUE O
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
Q1
M_
E HE
DETAIL P
Z
D
VIEW P
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
A1
b
0.13 (0.005)
0.10 (0.004)
MILLIMETERS
MIN
MAX
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
1.42
INCHES
MIN
MAX
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
0.056
16-Pin Packages
PDIP16
N SUFFIX
PLASTIC DIP PACKAGE
CASE 64808
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
16
S
T
SEATING
PLANE
H
G
16 PL
0.25 (0.010)
T A
http://onsemi.com
400
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SO16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B05
ISSUE J
A
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
B
1
P 8 PL
0.25 (0.010)
R X 45
C
SEATING
PLANE
D 16
PL
0.25 (0.010)
T B
MILLIMETERS
MIN
MAX
9.80 10.00
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7
0
6.20
5.80
0.50
0.25
DIM
A
B
C
D
F
G
J
K
M
P
R
INCHES
MIN
MAX
0.386 0.393
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7
0
0.229 0.244
0.010 0.019
SO16 WIDE
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G03
ISSUE B
A
D
9
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
h X 45 _
0.25
16X
M
14X
T A
0.25
A1
H
8X
16
SEATING
PLANE
DIM
A
A1
B
C
D
E
e
H
h
L
http://onsemi.com
401
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
10.15
10.45
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
TSSOP16
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948F01
ISSUE O
16X K REF
0.10 (0.004)
0.15 (0.006) T U
T U
K1
2X
L/2
16
J1
B
U
SECTION NN
J
PIN 1
IDENT.
8
N
0.25 (0.010)
0.15 (0.006) T U
A
V
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE W.
N
F
DETAIL E
C
0.10 (0.004)
T SEATING
PLANE
DETAIL E
H
D
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.18
0.28
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.007
0.011
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
SO16 EIAJ
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96601
ISSUE O
16
LE
Q1
M_
E HE
1
DETAIL P
Z
D
e
VIEW P
A1
b
0.13 (0.005)
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
0.10 (0.004)
http://onsemi.com
402
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
0.78
INCHES
MIN
MAX
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
0.031
20-Pin Packages
PDIP20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 73803
ISSUE E
-A20
11
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
C
-T-
SEATING
PLANE
M
E
G
N
F
J 20 PL
0.25 (0.010)
D 20 PL
0.25 (0.010)
T B
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010 1.070
0.240 0.260
0.150 0.180
0.015 0.022
0.050 BSC
0.050 0.070
0.100 BSC
0.008 0.015
0.110 0.140
0.300 BSC
0
15
0.020 0.040
MILLIMETERS
MIN
MAX
25.66 27.17
6.60
6.10
4.57
3.81
0.55
0.39
1.27 BSC
1.77
1.27
2.54 BSC
0.38
0.21
3.55
2.80
7.62 BSC
15
0
1.01
0.51
SO20 WIDE
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D05
ISSUE F
q
20
X 45 _
h
1
10
20X
B
0.25
T A
A
L
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
11
18X
A1
SEATING
PLANE
DIM
A
A1
B
C
D
E
e
H
h
L
http://onsemi.com
403
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
TSSOP20
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948E02
ISSUE A
K REF
20X
0.15 (0.006) T U
0.10 (0.004)
T U
K
K1
2X
L/2
20
11
J J1
B
U
L
PIN 1
IDENT
SECTION NN
10
0.25 (0.010)
N
0.15 (0.006) T U
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE W.
A
V
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
N
F
DETAIL E
W
C
G
DETAIL E
0.100 (0.004)
T SEATING
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
PLANE
SO20 EIAJ
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 96701
ISSUE O
20
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
11
Q1
E HE
M_
L
10
DETAIL P
Z
D
VIEW P
A
c
A1
b
0.13 (0.005)
0.10 (0.004)
http://onsemi.com
404
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
2.05
0.05
0.20
0.35
0.50
0.18
0.27
12.35
12.80
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
0.81
INCHES
MIN
MAX
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.486
0.504
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
0.032
CALIFORNIA
Irvine . . . . . . . . . . . . . . . . . . . . . . (949)7537360
San Jose . . . . . . . . . . . . . . . . . . (408)7490510
COLORADO
Littleton . . . . . . . . . . . . . . . . . . . . (303)2565884
FLORIDA
Tampa . . . . . . . . . . . . . . . . . . . . . (813)2866181
GEORGIA
Atlanta . . . . . . . . . . . . . . . . . . . . (770)3383810
ILLINOIS
Chicago . . . . . . . . . . . . . . . . . . . (847)4132500
MASSACHUSETTS
Boston . . . . . . . . . . . . . . . . . . . . (781)9329700
MICHIGAN
Detroit . . . . . . . . . . . . . . . . . . . . . (248)3476800
MINNESOTA
Plymouth . . . . . . . . . . . . . . . . . . (612)2492360
NORTH CAROLINA
Raleigh . . . . . . . . . . . . . . . . . . . . (919)8704355
PENNSYLVANIA
Philadelphia/Horsham . . . . . . . (215)9574100
TEXAS
Dallas . . . . . . . . . . . . . . . . . . . . . (972)5165100
CANADA
ONTARIO
Ottawa . . . . . . . . . . . . . . . . . . . . (613)2263491
QUEBEC
Montreal . . . . . . . . . . . . . . . . . . . (514)3333300
INTERNATIONAL (continued)
KOREA
Seoul . . . . . . . . . . . . . . . . . . . . 82234407200
MALAYSIA
Penang . . . . . . . . . . . . . . . . . . . . 60(4)2282514
MEXICO
INTERNATIONAL
BRAZIL
Guadalajara . . . . . . . . . . . . . . . . 52(36)780750
CHINA
Beijing . . . . . . . . . . . . . . . . . . . 861065642288
Guangzhou . . . . . . . . . . . . . . 862087537888
Shanghai . . . . . . . . . . . . . . . . 862163747668
FRANCE
Paris . . . . . . . . . . . . . . . . . . . . . . 33134 635900
GERMANY
Munich . . . . . . . . . . . . . . . . . . . . 49 89 921030
HONG KONG
Hong Kong . . . . . . . . . . . . . . . 85226106888
INDIA
Bangalore . . . . . . . . . . . . . . . . . 91805598615
ISRAEL
Tel Aviv . . . . . . . . . . . . . . . . . . . 97299522333
ITALY
Milan . . . . . . . . . . . . . . . . . . . . . . . . 39(02)82201
JAPAN
Tokyo . . . . . . . . . . . . . . . . . . . 81354878345
http://onsemi.com
405
PHILIPPINES
Manila . . . . . . . . . . . . . . . . . . . . (63)2 8078455
PUERTO RICO
San Juan . . . . . . . . . . . . . . . . . . (787)6414100
SINGAPORE
Singapore . . . . . . . . . . . . . . . . . . . . (65)4818188
SPAIN
Madrid . . . . . . . . . . . . . . . . . . . . . 34(1)4578204
or . . . . . . . . . . . . . . . . . . . . . . . . . 34(1)4578254
SWEDEN
Stockholm . . . . . . . . . . . . . . . . . 46(8)7348800
TAIWAN
Taipei . . . . . . . . . . . . . . . . . . . 886(2)27058000
THAILAND
Bangkok . . . . . . . . . . . . . . . . . . . 66(2)2544910
UNITED KINGDOM
Aylesbury . . . . . . . . . . . . . . . 44 1 (296)395252
http://onsemi.com
406
DL129/D
Rev. 7, Mar-2000
ON Semiconductor
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further
notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does
SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different
applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by
customers technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or
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application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC
products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of
the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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ON Semiconductor Website: http://onsemi.com
DL129/D
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DL129
REV 7
ON Semiconductor