AN2014 From ST

AN2014 Application note
How a designer can make the most of STMicroelectronics Serial EEPROMs

Electrically erasable and programmable memory (EEPROM) devices are standard products, used for the non-volatile storage of parameters and fine-granularity data. There is no single memory technology (SRAM, DRAM, EEPROM, Flash Memory, EPROM, ROM) that meets an applications needs perfectly. Consequently, the designer needs to know the particular strengths and weaknesses of each technology before selecting the best compromise for use in any given application. He can then design the application to keep within the specification, for the best performance, best reliability and lowest failure rates. Lately, this involves understanding at least the general principles of how the devices, in the given technology, are constructed, and how they work. This document has been designed to give precisely this level of background understanding for one of those technologies: EEPROM, from STMicroelectronics. It describes how STMicroelectronics EEPROM is constructed, how it works, and gives useful guidelines for achieving high reliability applications under some of the most stringent conditions, such as those that are experienced in the automotive market.
January 2007
Rev 4
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www.st.com
Contents
AN2014 - Application note
Contents
1 Construction of an EEPROM device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Floating gate operation within an EEPROM cell . . . . . . . . . . . . . . . . . . . . 7
1.1.1 1.1.2 1.1.3 Reading the value stored in a memory cell . . . . . . . . . . . . . . . . . . . . . . . 9 Writing a new value to the memory cell . . . . . . . . . . . . . . . . . . . . . . . . . 10 Cycling limit of EEPROM cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2
Electrical structure of ST serial EEPROM arrays . . . . . . . . . . . . . . . . . . . 14

1.2.1 1.2.2 1.2.3 Memory array architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Decoding architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Intrinsic electrical stress induced by programming . . . . . . . . . . . . . . . . 15
Choosing a suitable EEPROM for your application . . . . . . . . . . . . . . . 17

2.1 2.2 2.3 Choosing a memory type suited to the task to be performed . . . . . . . . . . 17 Choosing an appropriate memory interface . . . . . . . . . . . . . . . . . . . . . . . 17 Choosing an appropriate supply voltage and temperature range . . . . . . 18
Recommendations to improve EEPROM reliability . . . . . . . . . . . . . . . 19

3.1 ElectroStatic discharges (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.1.1 3.1.2 3.1.3 What is ESD? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 How to prevent ESD? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 ST EEPROM ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2
Electrical over-stress and latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2.1 3.2.2 3.2.3 What are EOS and latch-up? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 How to prevent EOS and latch-up events . . . . . . . . . . . . . . . . . . . . . . . 20 ST EEPROM latch-up protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3
Power supply considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.3.1 3.3.2 3.3.3 Stabilized power supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power-up and Power On Reset sequence . . . . . . . . . . . . . . . . . . . . . . . 23 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Hardware considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 IC family (M24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1.1 4.1.2 4.1.3 Chip enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Serial data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Serial clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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AN2014 - Application note 4.1.4 4.1.5
Contents Write control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Recommended I2C EEPROM connections . . . . . . . . . . . . . . . . . . . . . . 28
4.2
SPI family (M95) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Serial Data Input (D) and Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . 30 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Recommended SPI EEPROM connections . . . . . . . . . . . . . . . . . . . . . . 32
4.3
MICROWIRE family (M93C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3.1 4.3.2 4.3.3 4.3.4 4.3.5 4.3.6 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Serial Data (D) and Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Organization Select (ORG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Dont Use (DU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Recommended Microwire EEPROM connections . . . . . . . . . . . . . . . . . 36
4.4
PCB Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.4.1 4.4.2 4.4.3 Cross coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Noise and disturbances on power supply lines . . . . . . . . . . . . . . . . . . . 37 Communication lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Software considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.1 5.2 EEPROM electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Optimal EEPROM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.2.1 5.2.2 Page mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3
Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.3.1 5.3.2 Software write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Hardware write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5.4
Data integrity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.4.1 5.4.2 5.4.3 5.4.4 The checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Data redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Checksum and data redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Extra redundancy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.5
Cycling endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.5.1 Datasheet specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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Contents 5.5.2 5.5.3
AN2014 - Application note Temperature dependence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Defining the application cycling strategy . . . . . . . . . . . . . . . . . . . . . . . . 48
Power supply loss and application reset . . . . . . . . . . . . . . . . . . . . . . . 50

6.1 Application reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.1.1 6.1.2 6.1.3 I2C family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SPI family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Microwire family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.2
Power supply loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

6.2.1 6.2.2 6.2.3 Hardware recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Backup capacitor value for EEPROM supply . . . . . . . . . . . . . . . . . . . . . 54 Interruption of an EEPROM request . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.3
Robust software and Default Operating mode . . . . . . . . . . . . . . . . . . . . . 59
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.1 7.2 7.3 Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Humidity and chemical vapors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Mechanical stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
8 9 10
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Three serial bus protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ESD Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Typical POR threshold values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Connecting the Ei Inputs of IC Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Calculation rules for pull-up resistor on SDA(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Connecting WC inputs in IC products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Calculation for external pull-up and pull-down resistors in SPI products. . . . . . . . . . . . . . . 32 Calculating external pull-up and pull-down resistors in Microwire products . . . . . . . . . . . . 36 Column and page address bits according to page length. . . . . . . . . . . . . . . . . . . . . . . . . . 45 Application cycling profile evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Structure of an EEPROM floating gate transistor, and circuit symbol. . . . . . . . . . . . . . . . . . 7 MOSFET-like operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Floating gate reservoir full of electrons (Erased state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Floating gate reservoir empty of electrons (Written state) . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Using the voltage on the control gate to determine the charge on the floating gate. . . . . . . 9 During Erase, electrons go through the tunnel oxide into the floating gate . . . . . . . . . . . . 10 During Write, electrons go through the tunnel oxide out of the floating gate . . . . . . . . . . . 11 HiV is the output of the charge pump (VPP signal applied to EEPROM cells) . . . . . . . . . . 12 Accumulation of negative or positive charges in the tunnel oxide . . . . . . . . . . . . . . . . . . . 13 Architecture of the memory array (showing the grouping in Bytes) . . . . . . . . . . . . . . . . . . 14 Decoding block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Latch-up mechanism and protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Latch-up test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Local EEPROM supply filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Chip Enable Inputs E0, E1, E2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Serial Data input/output SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SDA Bus Conflict with Push-Pull Buffers (Not recommended) . . . . . . . . . . . . . . . . . . . . . . 26 Serial Clock input SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Write Control Input (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Recommended IC connections safe design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Recommended IC connections robust design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Chip Select, Clock, Data, Hold input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Write Protect input W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Output pin tri-state buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Recommended SPI connections - safe design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Recommended SPI connections - robust design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Chip Select, Clock, Data input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Organization input ORG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Recommended Microwire connections - safe design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Recommended Microwire connections - robust design . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PCB decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 IC data polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 SPI data polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Microwire data polling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 .Recommended use of the WC Pin in IC products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Recommended use of the W Pin in SPI products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Example of how to duplicate data safely . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Write/Erase cycles vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 .Application Reset I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Application Reset SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Application Reset MICROWIRE Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 EEPROM Power Backup Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Emergency sequence I2C products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Emergency sequence SPI products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Emergency Sequence MICROWIRE Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
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Construction of an EEPROM device
1
1.1

Floating gate operation within an EEPROM cell
From the users point of view, this EEPROM device is a circuit for storing digital information. To interface with the EEEPROM device a set of standard instructions are used. Behind this simple interface, however, there are a number of sensitive analog and physical processes. Figure 1. Structure of an EEPROM floating gate transistor, and circuit symbol
Control Gate Oxide Floating Gate Gate Oxide Tunnel Oxide Source Channel Region Drain Source Drain Control Gate Floating Gate
AI10227
Figure 1. shows the key component of a single EEPROM cell, the floating gate transistor (also known as a FLOTOX transistor). Figure 2. shows how it can be considered to be just like any other type of MOSFET device. As the voltage, Vg, is increased on the Control Gate electrode, so the current flowing through the drain, Id, increases in proportion. For the present, we can assume that this is a fairly linear relationship. Figure 2. MOSFET-like operation
Id
A
Id Vg Drain
Source
Vg
AI10230
Figure 3. shows what happens if the Floating Gate can be made more negatively charged, by filling it with extra electrons. This is used for the Erased state of the EEPROM cell. Figure 4. shows what happens if the Floating Gate can be made less negatively charged, by emptying it some of its normal electrons. This is used for the Written state of the EEPROM cell.
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Construction of an EEPROM device Figure 3.
Floating gate reservoir full of electrons (Erased state)

Vg Id
Control Gate Oxide - - - - - - - - - - - - - - - - - - - - Gate Oxide Tunnel Oxide Source Channel Region Drain Vth.erase Vg
AI10228
1. Control Gate threshold value (Vth.erase) is positive. 2. Id = f(Vg) characteristic shows Id=0 for Vg<Vth.erase.
The effect, as viewed from the channel region of the transistor, is that the Control Gate voltage, Vg, is offset by an extra negative or positive amount. Viewed from the outside, black-box electrical behavior of the device, the charge on the Floating Gate has the effect of moving the threshold MOSFET voltage, Vth, at which the linear conduction region begins. In other words, a FLOTOX transistor is a MOS transistor with a variable Control Gate threshold value, Vth. The Floating Gate acts as the storage element, and, being completely surrounded by insulating oxide, as shown in Figure 1., keeps its charge even when there is no power supply. Figure 4. Floating gate reservoir empty of electrons (Written state)
Vg Id
Control Gate Oxide + + + + + + + + + + + + + + + + + + Gate Oxide Tunnel Oxide Source Channel Region Drain Vth.write Vg
AI10229
1. Control Gate threshold value (Vth.write) is negative 2. Id=f(Vg) characteristic shows Id=0 for Vg<Vth.write.
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1.1.1
Reading the value stored in a memory cell

Figure 5. puts the three curves together, by way of comparison. It shows that for a given Control Gate voltage, Vg, the current that flows through the drain, Id, will be detectably higher or lower than that of the neutral device, depending on whether the reservoir of electrons on the Floating Gate has been filled up, or emptied. This, then, is the basis of how the memory cell can be read. Figure 5. Using the voltage on the control gate to determine the charge on the floating gate
Id
Id.ref
Vg.ref
Vg
AI10234
1. A written cell draws a current IA (where IA > Id.ref); an erased cell does not draw any current (0A).
In most of ST EEPROM products, a predetermined biasing condition on the Control Gate and the drain makes it possible to compare the current absorbed by the FLOTOX transistor with a reference. Basically, with the predetermined biasing condition an erased FLOTOX cell is not able to sink as much current as the reference (ideally the transistor is off). On the other hand, a written FLOTOX cell sinks a current that is superior to the reference (the transistor is on). By comparing to a reference current, the device is able to retrieve the stored information as a digital signal on the output pins of the memory device.
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1.1.2
Writing a new value to the memory cell

The next question, of course, is how the charge can be changed on the Floating Gate, given that it is so well insulated by oxide, and keeps its charge even when there is no power supply. The answer is that the Tunnel Oxide, shown in Figure 1., is very thin, and can be used to transfer charge, when much higher voltages are applied than those normally used during Read operations. Filling the Floating Gate reservoir with negative charges (electrons) is called Erase. After Erase, the FLOTOX transistor is in the Erased State (see Figure 3.). Pulling out negative charges from the Floating Gate is called Program. After Program, the FLOTOX transistor is in the Written State (see Figure 4.). One state is used to represent logic-0, and the other logic-1, but the exact choice is manufacturer and product-type dependent). Both operations use the Fowler-Nordheim tunneling effect. For this, a high electric field (10 MV/cm, or more) is needed to make electrons pass through the thin Tunnel Oxide. For a Tunnel Oxide thickness of 100, the high voltage needs to be at least 10V. In fact, higher voltages, in the range 15 to 18V, are normally used, to reduce the time taken for the operation. Voltages higher than this cannot be used, since they would damage the thin Tunnel Oxide. For Erase, the cell Control Gate is made positive, and the source-drain region is grounded (as shown in Figure 6.). The electric field makes electrons move from the substrate towards the Floating Gate, thereby filling the reservoir, and increasing the characteristic threshold voltage of the transistor (as shown in Figure 3.). Figure 6. During Erase, electrons go through the tunnel oxide into the floating gate
Vg=+18V
Control Gate Oxide Floating Gate Gate Oxide Tunneling Electrons Source Channel Region Drain Vd=0V
AI10232
Electric Field
e-
1. Characteristic threshold Vth increases and becomes positive as shown in Figure 3.
For Write, the Control Gate is grounded and the source-drain region is made positive (as shown in Figure 7.). The electric field is the opposite of that for Erase, and so electrons move out from the Floating Gate, thereby emptying the reservoir, and decreasing the characteristic threshold voltage of the transistor (as shown in Figure 4.).
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AN2014 - Application note Figure 7.
During Write, electrons go through the tunnel oxide out of the floating gate
Vg=0V
Control Gate Oxide Floating Gate Gate Oxide Tunneling Electrons Source Channel Region Drain Vd=+18V
AI10233
Electric Field
e-
1. Characteristic threshold decreases and becomes negative as shown in Figure 4.
Typically EEPROM Erase/Write cycles require a high voltage of about 15 to 18V for approximately 5ms. As EEPROM devices use a single supply voltage, the high voltage must be generated and managed internally. A set of analog circuits is needed to generate and control the high voltage from the single external power supply:

voltage and current references to control oscillators and timings a regulated charge pump that generates a stable 15 to 18V voltage, HiV, from the single external power supply a ramp generator that, from the stable 15 to 18V DC voltage, makes the specific waveform (shown in Figure 8.) that is to be applied to the cells
VPP is the high voltage that is directly applied to the FLOTOX cell, as described earlier. The precise shape of the VPP voltage waveform is critical, and has a direct effect on the reliability and endurance of the memory cells. The slope, plate time and maximum level are parameters that are very carefully controlled. Writing new data in an EEPROM array means doing an auto-erase of all the addressed Bytes, to reset them all to the Erased state, and then selectively programming those bits that should be set to the Written state.
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Construction of an EEPROM device Figure 8.
HiV is the output of the charge pump (VPP signal applied to EEPROM cells)
HiV 18V
VPP
Auto-Erase
Program
5ms Write Cycle = Auto-Erase + Program
t(ms)
AI10235
To Summarize: Binary information is coded by means of a FLOTOX transistor. The Floating Gate is a reservoir filled with negative electric charges that modify its electrical characteristics. The electric charges can be made to migrate into or out of the reservoir by applying a high voltage to a thin Tunnel Oxide. The binary information is read by comparing the cell (FLOTOX transistor) current to a reference.
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1.1.3
Cycling limit of EEPROM cells

When a cell is cycled (repeatedly erased and programmed) two common phenomena occur and are amplified during the memory cell lifetime. When tunneling, negative charges can either be trapped in some imperfection of the oxide or damage the Tunnel Oxide: 1. The accumulation of negative charges in the thin Tunnel Oxide creates an electric barrier in the Tunnel Oxide. The high voltage needed for the tunneling effect becomes even higher: programming high voltages are no longer able to move enough charges to program the cell properly. The Erased and Written states become undifferentiated. When the Tunnel Oxide deteriorates, a positive charge path may appear, that facilitates undesirable leakage through the Tunnel Oxide. The Floating Gate is no more 100% insulated, and loses its charges, and so the data retention time drops drastically. Accumulation of negative or positive charges in the tunnel oxide
2.
Figure 9.
Control Gate
Oxide
Floating Gate
Gate Oxide
+ - - + - - +
Horizontal electric barrier disturbing erase and write
Source
Channel Region Vertical electric path leading to leakage

AI10251
Charge trapping and oxide damage are accelerated at high temperatures. They are directly involved in cell cycling and endurance limitations. To store permanent digital information, we have to deal with physical phenomena and analog nonlinear behaviors that have natural limits and are sensitive to wear-out and improper use conditions.
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1.2
Electrical structure of ST serial EEPROM arrays

In the previous section, the EEPROM functionality was considered at the single bit level. We will now zoom out of the memory cell to the full EEPROM array, in order to give an overview of the architecture of an EEPROM device.
1.2.1
Memory array architecture

An EEPROM device is made of an array of memory cells whose organization allows Byte granularity, the automatic erasing of the addressed Bytes (Erased state), and the programming of only those bits that are to be changed to 1 (Written state). The array (as shown in Figure 10.) is organized as follows:
Each memory cell consists of one Select transistor in series with a FLOTOX transistor and each Byte is made up of eight memory cells and a Control Gate transistor with a drain that is common to the control gates of all eight FLOTOX transistors. Rows (in the horizontal direction) are made up of 16, 32, 64 or 128 Bytes (The number of Bytes within each row is a function of the array size.) All Select transistors that are in the same row and all Control Gate transistors have their control gates connected to the Row line. Each column consists of a group of lines, within the row, to implement a complete Byte of memory cells. This involves eight bit-lines and one Cg-line. This is then repeated as many times as the number of rows. A bit-line is common to all the drains of the Select transistors of each memory cell in the column. A Cg-line is common to all the sources of the Control Gate transistors of the column.
Figure 10. Architecture of the memory array (showing the grouping in Bytes)
Column 0 Cg-Line 0 Cg line b07 Bit line 8 Bit-Line Latches b06 b00 Bit line Bit line Column i Cg-Line i bi7 8 Bit-Line Latches bi6 bi0
RowLine 0
8 Select transistors
8 FLOTOX transistors Control Gate transistor Memory Cell Select transistor
Byte RowLine n
FLOTOX transistor
AI10224b
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1.2.2
Decoding architecture
To address a single Byte in a full array, decoding circuits are necessary. One logical address is associated with one byte location. The address bits are inserted serially into a Shift Register. Then, with parallel output, the decoding structures receive all of the bits at the same time, to perform the decoding and addressing. The row decoder decodes and brings correct biasing to a single row line. As one or more Bytes of the same row can be programmed at the same time, the column decoder decodes one or more column(s), and a RAM buffer memorizes the data to write, and enables the right path for Cg-line and Bit-line biasing. Figure 11. Decoding block diagram
Serial Input Address Shift Register
MSB Address Bits
LSB Address Bits

Column Decoder
Read/Write Analog Voltages
Bit-line and Cg-line Latches: RAM Buffer Cg-lines and Bit-lines
Row Decoder
Array
Row-lines
AI10225
1.2.3
Intrinsic electrical stress induced by programming

Whatever kind of data must be programmed and whether the request is made by Byte or page, all high-voltage circuits are stressed by HiV (a high voltage ranging between 15 and 18V). In particular, the internal nodes of the charge pump can see voltages equal to HiV + VCC (that is as much as 23 V). All circuits that receive and carry HiV (ramp generator, regulation, decoding, latches) are submitted to higher stress than active low voltage transistors. The overall time during which the high voltage circuits are active is relatively short compared to the product lifetime (10ms x 1Mcycles = 10000 seconds => less than 3 hours). A standard ST EEPROM device has a few hundred high voltage transistors, for low memory capacity products (1Kbit). This number can rise to a few thousand for high memory capacity products (1Mbit). Consider, by way of example, the stress induced on the array elements when programming one single Byte in a 1Kbit EEPROM, organized as 128 x8 bit. The memory array is composed of 8 pages (or rows) of 16 Bytes (or columns).
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Erase Cycle: the complete row (page) that contains the addressed Byte receives the VPP signal, on the selected Row-line, as does the complete column, on the selected Cg-line:

Control Gates of all the Select transistors in the given row: 1 row x 16 Bytes x 8 bits =128 Control Gates of all the Control Gate transistors in the given row: 1 row x 16 Bytes = 16 Drains of all the Control Gate transistors that are connected to the given Cg-line: 1 column x 8 rows = 8
The Bit-lines of the addressed Bytes are floating. Write Cycle: the complete row (page) that contains the addressed Byte receives the VPP signal, on the selected Row-line:

Control Gates of all the Select transistors in the given row: 1 row x 16 Bytes x 8 bits =128 Control Gates of all the Control Gate transistors in the given row: 1 row x 16 Bytes = 16 The Cg-line of the addressed Byte is held at ground voltage The Bit-lines are left floating or receive VPP depending on data to be written. The worst case is when FFh is to be written, and all Bit-lines receive the VPP signal Drains of all the Select transistors sharing the same 8 Bit-lines: 1 column x 8 rows x 8 bits = 64
This example shows how one single Byte, being erased or programmed, incurs a lot of High Voltage stress on elements that are on the same row, column and bit-line as the one addressed. For a 1Kbit EEPROM, programming one single Byte to FFh induces stress on 128 Select transistors and 24 Control Gate transistors during auto-erase, and 192 Select transistors and 16 Control Gate transistors during the write cycle, even though only 17 transistors (8 Select transistors, 8 FLOTOX transistors, 1 MOS transistor) were really being addressed for the data change. The bigger the memory array, the larger the number of additional transistors that are involved. This is why when high cycling performance is required, it is recommended to gather cycled data in contiguous blocks and use the write page mode as much as possible.
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Choosing a suitable EEPROM for your application

ST "Automotive Grade" EEPROM products are made to meet automotives stringent requirements. They are produced by a longstanding process and benefit from being tested continuously for quality as well as specific test strategies like Statistical Bin Limits, Parametric Average Testing and qualification following the AEC Q100, specific product buffer stocks, etc. Nevertheless, the reliability on EEPROM products are also closely linked to the way they are designed in Applications.The aim of this part of the document is to provide our automotive customers with a set of practical recommendations for achieving immediate improvements in application reliability and robustness. In the case of automotive applications, ST strongly recommends the use of products that are classified as automotive grade. These devices are designed to satisfy the most stringent requirements of automotive, sensitive and safety applications. "Grade 3" and Automotive Grade EEPROMs are tested with STmicroelectronics High Reliability Certified Flow (described in Quality Note, QNEE9801) insuring a very high level of quality.
2.1
Choosing a memory type suited to the task to be performed

EEPROM devices are particularly suited to the tasks of code traceability and parameter storage. The Serial protocol offers the best compromise of performance versus cost where the access time is not critical.
2.2
Choosing an appropriate memory interface

ST is specialized in Serial Access EEPROMs, which are based on three main protocols: IC, SPI and Microwire (see Table 1.). Fundamental requirements such as noise immunity, ESD, Latch-up and cycling Endurance are basic features of each ST Serial EEPROM device (independent from the protocol used). The choice of the most appropriate Serial EEPROM (as described in AN1001) depends mainly on the hardware resources of the master and on the architecture built around it. See the following:
The I2C bus offers a 2-wire protocol working at a maximum clock rate of 400KHz and so, is preferred when the hardware resources are limited and the data rate is not a constraint at all. The multiple slave configuration requires no extra hardware and is managed by software. The SPI bus and Microwire bus are 4-wire protocols allowing higher communication speed (speed is determined by each manufacturer design and technology). The number of slaves is unlimited but each slave requires an additional master resource for the chip select line. Both SPI and Microwire can be used with only 3 wires providing that the D and Q pins are tied together to a bidirectional I/O.
Data Write protection is different for each protocol family and is also a key factor when selecting the memory interface. I2C products offer only hardware Write protection while SPI and Microwire products provide both hardware and software protection. Refer to 5.3, Write protection.
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If none of the standard products exactly meets all the requirements to produce an Application Specific Memory (as described in AN1292), customizing is also possible. Table 1. Three serial bus protocols
IC SPI M95xxx, 1Kb to 1Mb Serial Flash M25 & M45xxx 512Kb to 64Mb 4 wires: data in, data out, clock & CS Up to 20Mb/s Byte Page: 16 Bytes to 128 Bytes Hold mode (input pin) Write control for 4 blocks SO8, TSSOP8, MSOP8, MLP8, PDIP8 MICROWIRE M93Cxx, 256b to 16Kb M93Sxx, 1Kb to 4Kb 4 wires: data in, data out, clock & CS 1Mb/s Byte or Word Page: 4 Words Block write protection defined by software for M93Sxxx family SO8, TSSOP8, MSOP8, MLP8, PDIP8
ST Families
M24Cxx, 1Kb to 1Mb
Interface Clock Rate (max) Data Management Specific Features Package
2 wires: Single I/O line, clock 400Kb/s Byte Page: 16 Bytes to 128 Bytes Global write control Up to 8 devices cascadable on the same bus SO8, TSSOP8, MSOP8, MLP8, PDIP8
2.3
Choosing an appropriate supply voltage and temperature range

These are essential parameters that will determine the devices reliability to operate. The VCC values and the temperatures of the final application must always stay within the ST EEPROM guaranteed range (given in the datasheets) since correct operation outside the specified ranges can never be guaranteed. This means that not only average values, but effective maxima and minima or forecast extreme values, must be taken into account when deciding on a power supply and temperature range. The robustness of an application is very often really measured under these critical conditions. Moreover biasing an EEPROM device above the authorized operating values accelerates the ageing process. For instance, using a 7V power supply on the technology currently used (CMOSF6 0.6m-0.5m power supply) accelerates the ageing process by a factor of 1000 with respect to an authorized 5V power supply.
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Recommendations to improve EEPROM reliability
3
3.1

ElectroStatic discharges (ESD)
ESD damage can happen any time during the product lifetime, from the moment it is delivered to the final field service operation. ESD damage can be destructive or latent. In the first case, a simple functional test can screen faulty devices; in the second case, the part is partially damaged and may be able to operate correctly, but its operating life may be drastically reduced, causing the device to fail prematurely in field service.
3.1.1
What is ESD?
Static Electricity results from the contact and separation of two bodies, which creates an unbalance in the number of electrons at the surface of the bodies. Practically, the bodies become charged to a specific electrical potential that depends on the material from which they are made (see Table 2.). An Electro-Static Discharge is defined as the transfer of charges between two bodies at different electrical potentials. It is instantaneous (a few nanoseconds) and thus induces high energy transfers very difficult to control and predict.
3.1.2
How to prevent ESD?

From customer goods-in to the final customer production line, ESD-protected areas are mandatory. Therefore, human and machine ESDs must be treated with care. The discharging of accumulated charges through a known and controlled path avoids hazardous ESD stress. An ESD occurs only if a conductive path with a potential difference is found by a charged object. Specific design rules and techniques can be used by designers to better protect against ESDs, such as Faraday shields, perimeter ground lines or ground planes.
3.1.3
ST EEPROM ESD protection

ST EEPROM devices offer a specific protection circuit against Human Body Model ESDs of up to at least 4000V in non-operating mode (in accordance with AEC-Q100-002). During write operations, the EEPROM is much more sensitive to ESDs because of the architecture of its internal high voltage generator. Applications exposed to ESD should avoid writing data in the EEPROM when an ESD is more likely to occur. Table 2. ESD Generation(1)
ESD generation means Walking across a carpet Worker on a bench Chair with Urethane Foam Static voltage levels 1 500 V to 35 000 V 100 V to 6 000 V 1 500 V to 18 000 V
1. The charge unbalance depends on many factors such as the contact area, separation speed and relative humidity.
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3.2
Electrical over-stress and latch-up

Electrical Over-Stress (EOS) and Latch-up are also damaging stresses that are either immediately destructive, or may create latent defects leading to premature failure.
3.2.1
What are EOS and latch-up?

In comparison with ESDs, EOS and Latch-up are lower-intensity events that last much longer (sometimes more than a few seconds). EOS and Latch-up give rise to current injections or overvoltage stress on external package pins. Latch-up occurs when a charge injection causes parasitic thyristors (or SCRs Switching Current Rectifiers) to switch on and discharge a very high current between the VDD and VSS of the device until the power is turned off.
3.2.2
How to prevent EOS and latch-up events

Typically power supply cycling leads to EOS situations. During the power-up and powerdown phases, the EEPROM signals interfaced with other ICs may temporary see voltages greater than VCC or lower than VSS. When outside Absolute Maximum Ratings, these biasing conditions may lead to positive and negative current injections, respectively. This kind of stress cannot always be completely prevented but it can be minimized. The switching sequence of the different interfaced ICs must be carefully determined, and if necessary protection resistor (<1K) can be placed on critical pins or sometimes directly on VCC pin (<50) to limit eventual latch-up current. Please refer to the 4, Hardware considerations section for more details. Overshoots and undershoots may occur on external device pins when the application is running. They are generated by radiations, power supply disturbances or even some ICs. The very first protection is provided by the semiconductor manufacturer (ST) which offers the best possible robustness against EOS and Latch-up. If extra protection is needed, the application designer can add small value resistors (<1k) in series on all interfaced lines and (<50Ohm) in series on VCC line so that it can be compatible with the communication speed constraints and power supply range. Please refer to the Hardware considerations section for more details. Manufacturing, handling devices and probe testing are also sources of EOS: all voltage levels applied to the device must be checked accurately and regularly. In addition all equipment should be constantly calibrated. During Write operations, EEPROM devices are more sensitive to overvoltages on their power supplies because of their internal high voltage generators.
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Figure 12. Latch-up mechanism and protection

5V 5V
High current(often destructive) EEPROM VCC

SRC
RP<50
VCC I/O I or V stress

SRC
RP<1K I/O
VSS
VSS
SCR is switched on by an external stress coming from an I/O pin.
Latch up risk minimized

Ai11084b
1. Protection is only recommended if Latch-up risk is identified.
3.2.3
ST EEPROM latch-up protection

During the qualification process samples from three different lots are tested for voltage overshoots and positive and negative injections. Figure 13. shows the levels of stress applied to the tested devices. Figure 13. Latch-up test conditions
Current Injection
Good = Class A 100mA Fail 0.5 x VCCmax 1.5 x VCCmax Fail Good = Class A 100mA
ai10858
Overvoltage
1. The device does not latch up within the gray areas.
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3.3
Power supply considerations

The power supply also has a major impact on the operating reliability of the EEPROM device.
3.3.1
Stabilized power supply voltage

The value of the stabilized power supply voltage, including potential variations, must always stay within the operating VCC range specified in the datasheet, where device operation is reliable and guaranteed. Application designers deal mostly with transient peak currents and voltages. Transient peak current generated by EEPROM during read, write and output buffer transitions induces transient voltage disturb on power supply lines. Therefore, the use of high-frequency, low-inductance capacitors located as close as possible to the device VCC and VSS pins are also recommended. Some applications with a limited power supply driving capability (e.g. battery) may require a small value resistor (<50), which is connected to the EEPROM VCC pin, to optimize local filtering. See Figure 14. Figure 14. Local EEPROM supply filtering
5V
50
Vcc EEPROM Device Vss 10nF < C < 100nF
Ai11064
1. Capacitor should be placed as close as possible to VCCand VSS pins to avoid parasitic inductive effects. 2. Resistor must never be placed between the decoupling capacitor and the VCC pin of the EEPROM.
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3.3.2
Power-up and Power On Reset sequence

During Power-up, the application designer has to make sure that the VCC supply voltage waveform rises monotonously, with a maximum slew rate of 1V/s, from VSS to the final stabilized value in order for EEPROM internal reset to be performed correctly. In ST EEPROM devices the POR circuit is activated first. It locks the part before the internal logic is able to activate any function. Therefore while the device is in the undefined area where VCC is close to ground level there is no risk of data corruption. The POR circuit then ensures the global reset and re-initialization of the device. The internal reset mechanism is released once the VCC supply voltage has reached a value where the stability of the device in the standby mode is ensured. Then, normal device operation is guaranteed only above the VCC min. operating value. The application designer should therefore make sure that no instruction is issued to the EEPROM before VCC min. is reached and the power supply is stabilized as illustrated in Figure 15. After a power loss condition, it is recommended to carry out a safe power-down by pulling VCC to ground, and a safe power-up to secure the device re-initialization. Figure 15. Power-Up
Voltage Monotonous rising slope slower than 1V/s VCCmax VCCmin
POR
time Part locked by POR Standby mode Operation allowed

ai10859
1. Power-up is safe with a monotonous rising slope slower than 1V/s.
Table 3.
Typical POR threshold values

IC All 5V SPI Other Device Ranges 1.5V0.2V 5V 3 V 0.5 V Microwire Other Device Ranges 1.5 V 0.2 V
Bus protocol Device voltage range
POR threshold values at 1.5 V 0.2 V 3 V 0.5 V ambient temperature
3.3.3
Absolute maximum ratings

Absolute maximum ratings are not operating values for the device. They provide an additional security margin for temporary operating deviations. Temporary operation within this margin will not cause the device to be damaged. However, the normal operation of the EEPROM is neither guaranteed nor reliable under absolute maximum rating conditions that are above or below normal operating conditions.
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Hardware considerations
EEPROM connections are essential for an applications robustness. At Power up, Power down and Application Reset input signals must be fully controlled to avoid hazardous behavior or random operation. For each product family a good hard-wiring design can protect the parts from uncontrolled behavior.
4.1
4.1.1
IC family (M24)
Chip enable (E0, E1, E2)
The Chip Enable (E0, E1, E2) inputs have an internal pull-down resistor. It is thus possible to have the three Chip Enable inputs at 0 (Chip Enable address is 000) if, by mistake, the application designer has left them floating, but it is a configuration that should be avoided since inputs are still prone to antenna-like pick-up or other cross coupling effects. In a robust design, the Chip Enable inputs should be directly tied to VCC or VSS. Driving these inputs dynamically is not recommended either since a Chip Enable address that is not also changed in the Device code will lead to communications problems. The input pin leakage on Ei pins depends on the input voltage value. See Table 4. Figure 16. Chip Enable Inputs E0, E1, E2
Ei pin
RPD
T ESD/EOS Protection
ai10914c
Table 4.
Connecting the Ei Inputs of IC Products

IC products 1 Kbits to 16 Kbits 30 K 32 Kbits to 128 Kbits 100 K Ili = 0 for VEi > VIH Ili = VEi/RPD for 0 < VEi < VIH Direct connection to VCC or VSS, or connection through a small (< 1 k) resistor for a better protection against external stress 256 Kbits to 512 Kbits 50 K
Typical internal E0, E1, E2 Pulldown Resistance (RPD) Input leakage Ili of Ei pins Recommended Connection of Ei pins
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4.1.2
Serial data (SDA)

The Serial Data (SDA) input/output is a bidirectional signal. The SDA pin is internally connected to a CMOS Schmitt trigger input buffer and an open drain output transistor (see Figure 17.). The SDA line must be pulled to the VCC of the device with a pull-up resistor (RPU). Pull-up value depends on capacitive load of SDA line, Master and EEPROM I/O buffer characteristics. See Table 5. for calculation rules. On the Master side, the SDA line should be connected to an open drain output and not to a push-pull buffer as connecting to a push-pull buffer could lead to the generation of a high current between the power supply of the Master and the ground of the EEPROM slave device. This event becomes very likely when the IC device acknowledges an instruction from the Master. In this configuration a resistor (RS) on an SDA line will limit the short-circuit current (See Figure 18.). The input pin leakage is negligible (typically a few nA). The input schematic (including protection circuit) does not offer any open path to the VSS or VCC therefore the SDA level can be set before the EEPROM power up and remain high even after Power Down with no risk of leakage or EOS. Figure 17. Serial Data input/output SDA
INPUT SDA pad RC Filter Schmitt trigger
OUTPUT
Open-drain Resistor
ESD/EOS Protection
Ai11088
Table 5.
Calculation rules for pull-up resistor on SDA(1)

RPU x Cload < SDA rise time (I2C specification is 300ns) (2) V CC V IL EEPROM V CC V IL Master Maximum values of: ---------------------------------------------- ;------------------------------------------ I OL Master I OL EEPROM
Maximum RPU
Minimum RPU
1. The smaller RPU, the faster the clock frequency. The higher RPU, the lower the operating current, the slower the transitions and the lower the electromagnetic interference. 2. Refer to the "Maximum RL value Vs. Bus capacitance" figure in I2C datasheet
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Figure 18. SDA Bus Conflict with Push-Pull Buffers (Not recommended)
VCC
RPU SDA Line
EEPROM Device Low impedance path Rpu does not limit the current
(1)
Push-pull output buffers
RS
T2
Ai11065
1. RS > VCC/IO with IO = min(Master IOH, EE IOL). Without the RS resistor the current is limited by the Master buffer and transistor T2 producing overstress at both Master and EEPROM side.
4.1.3
Serial clock (SCL)

The Serial Clock (SCL) input is connected to a CMOS Schmitt trigger input buffer. In applications with a multiple master configuration, the master must have an open drain output with an external pull-up resistor. In applications using a single master configuration, SCL line can be connected to a push-pull buffer. For a safe design, the SCL line must never be left floating (Hi-Z) and must be driven low when SDA transitions are not under control to avoid undesired START and STOP conditions. Power up, Power down phases as well as Reset states, can be secured using a pull-down resistor on the SCL line. This will minimize the chances of a parasitic STOP/START condition, when the controller releases the I2C bus. The input pin leakage is negligible (typically a few nA). Input schematic (including a protection circuit) does not offer any open path to VSS or VCC. Therefore SCL level can be set before the EEPROM power up and can remain high even after power down with no risk of high leakage or EOS. Figure 19. Serial Clock input SCL
SCL pad Glitch Filter Schmitt trigger 100ns
ESD/EOS Protection
Ai11725
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4.1.4
Write control (WC)

The Write Control (WC) input has an internal pull-down resistor, in case the application designer leaves it floating (See Figure 20.). If no write protection is necessary, it should be directly tied to the VSS. The best write protection is obtained by connecting the Write Control input to a Master output and a pull-up resistor, to VCC, thus allowing a default write protection also during the critical Power-up, Power Down and Application Reset phase. Prior to issuing any Write instruction the WC pin should be driven Low and it should be maintained Low during the whole operation. Input pin leakage current depends on input pin voltage. See Table 6. Figure 20. Write Control Input (WC)
WC pin
VCC
I typ = 2.5A at VCC = 5V
RPD
T1 T2 ESD/EOS Protection
ai10916b
Table 6.
Connecting WC inputs in IC products

IC 1 Kbits to 16 Kbits 20 k 32 Kbits to 128 Kbits 70 k 256 Kbits to 512 Kbits 35 k
WC Pull-down Resistance (RPD)(1)
External Pull-up (RPU)
R PD -------------------------------- 0.7 R PU + R PD
Not used Input leakage Ili
Direct connection to VSS Ili = 0 for Vi = 0V Ili = Vi/RPD for 0<Vi<VIH lli < 5A for Vi > VIH
1. These pull-down values can change within the range authorized in the datasheet without previous notice.
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4.1.5
Recommended I2C EEPROM connections

Recommended IC EEPROM connections are shown in Figure 21 and Figure 22. Note that for both circuits: 1. 2. 3. 4. The decoupling capacitor (10 nF min) must be placed as close as possible to the package pins VCC and VSS. A 50 Ohm resistor can be connected to VCC, if extra filtering on VCC is needed, or if an identified latch up risk must be minimized. A pull-up resistor should be used only when the WC pin is driven by a Master I/O. If unused, the WC pin must be connected to ground. The I2C specification recommends to connect 220-Ohm resistors on SCL and SDA. They are not useful unless identified overstress is liable to occur on these pins or electromagnetic disturbances must be reduced.
Figure 21. Recommended IC connections safe design

VCC 4.7K (1) VCC
10nF
IC EEPROM VCC E0 E1 E2 WC SCL SDA (4) (4) VSS
(3) RL RL
VSS
GND
ai10917b
Figure 22. Recommended IC connections robust design

VCC
Reos < 1k
(1)
(2)
E0
10nF
4.7k
VCC
IC EEPROM VCC WC SCL (4) SDA (4) GND
(3) RL
E1 VSS E2 VSS
R<RL
ai10918c
Note:
I2C devices can operate correctly with an (E0, E1, E2, SDA, SCL, WC) input voltage higher than their own supply voltage. However input voltages must remain within the normal device operating range. The use of external pull-up and pull-down resistors is strongly recommended even if the Master I/Os reserved for the I2C bus are already providing them. This is because during power-supply transitions, the Master is in the reset sate and may not offer the correct configuration.
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4.2
4.2.1
SPI family (M95)

Chip Select (S)
Chip Select (S) is connected to a CMOS Schmitt trigger input buffer, which is both active Low and edge sensitive (a falling edge is required to select the device). For safe design, Chip Select (S) must never be left floating, it must be constantly held at VCC outside communications slots. It is strongly recommended to add a pull-up resistor to ensure a high level on the Chip Select pin at any time and in particular during power-up, power-down and the reset phase of the master. The pull-up resistance should be calculated as a function of the bus capacitive load so that the voltage on the S pin always remains above VIH = 0.7VCC during power-up. The input pin leakage is negligible, typically a few nA. The input schematic, including the protection circuit, does not offer any open path to the VSS or VCC. Figure 23. Chip Select, Clock, Data, Hold input pins
Hold, S, C, D
Schmitt Trigger
ESD/EOS Protection
Ai11065
4.2.2
Write Protect (W)

The Write Protect (W) signal is a CMOS input used to enable or disable Write Protection. To ensure write protection at Power-up and Power-down, its default state should be low. It is therefore recommended to add a pull-down resistor, stronger than the pull-up for the S signal, to optimize write protection in cases where the controller releases the SPI bus (power-up, power-down and Master reset phases). In this case the Write Protect (W) line goes low before the Chip select (S) line goes high, preventing the potential execution of an ongoing write command (write to memory for 1 Kbit to 4 Kbit densities and Write Status Register for 8 Kbit densities and above). The input pin leakage is negligible, typically a few nA. The input schematic, including the protection circuit, does not offer any open path to VSS or VCC.
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Hardware considerations Figure 24. Write Protect input W

W pin
ESD/EOS Protection
Ai11066
4.2.3
Serial Data Input (D) and Serial Clock (C)

The Serial Data Input (D) and Serial Clock (C) signals are connected to a CMOS Schmitt trigger input buffer and should be controlled by push-pull buffers. An external pull-down resistor on Serial Clock (C) signal will prevent out-of-specification configurations like simultaneous rising edges on S and C when the Master releases the SPI bus (violation of the tSHCH and tCHSH timings). An external pull-down resistor on the Serial Data Input (D) (see Figure 23., Chip Select, Clock, Data, Hold input pins) will optimize the signal control and standby current. Pull-down resistor values are optimized if they are at least 3 times bigger than the pull-up value on the Chip Select (S) line. In this case, if the SPI bus is released, the Chip Select (S) line goes high faster than the Clock (C) line goes low and so deselects the device before the Clock signal crosses the input buffer trigger point (around VCC/2). If the Clock (C) line cannot be pulled down and must be pulled up due to other system constraints, it is recommended to choose a weaker pull-up value (at least 3 times weaker) than the one on the Chip Select (S) line. Moreover, the "out-of-specification" configuration can be also minimized by connecting the Hold (HOLD) pin to the reset signal (active low) of the Master. As soon as the Master resets, the Hold (HOLD) line goes low, locking the Clock to a low level (if already low), thus preventing the occurrence of a rising edge on both the Clock and Chip Select lines (violation of the tCHSH and tSHCH timings). The input pin leakage is negligible, typically a few nA. The input schematic, including the protection circuit, does not offer any open path to the VSS or VCC.
4.2.4
Hold (HOLD)
The Hold (HOLD) signal is connected to a CMOS Schmitt trigger input buffer used to pause communication. It should be driven by a push-pull buffer for a better timing control, or tied directly to VCC if unused. The hold pin cannot be left floating. The Hold input will not sink current even if a voltage higher than VCC is applied to it. The Hold input can be set before the EEPROM power up and can remain high after power down. The input pin leakage is negligible, typically a few nA. The input schematic, including the protection circuit, does not offer any open path to the VSS or VCC (see Figure 23., Chip Select, Clock, Data, Hold input pins).
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4.2.5
Serial Data Output (Q)

The Serial Data Output (Q) is a push-pull tri-state output buffer. The Serial Data Output being often in the high impedance state and connected to a master input pin, it may be useful to connect it to a pull-up (or pull-down) resistor to set a default value on the bus and thus prevent the master input from toggling. Application designers must be aware that connecting several devices on the Serial Data Output (Q) increases capacitive load of the line. The access time of the ST EEPROM is tested with a 100 pF load until 10 MHz, or a 30 pF load for frequencies from 20 MHz. Figure 25. Output pin tri-state buffer
Q pin
ESD/EOS Protection
Ai11067
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4.2.6
Recommended SPI EEPROM connections

Recommended SPI EEPROM connections are shown in Figure 26 and Figure 27. Note that for both circuits: 1. 2. 3. The decoupling capacitor (10 nF min) must be placed as close as possible to the package pins VCC and VSS. A 50 Ohm resistor can be connected to VCC if extra filtering on VCC is needed or if an identified latch-up risk is to be minimized. If unused, the Hold and W pins must be directly connected to VCC.
Figure 26. Recommended SPI connections - safe design

VCC Rpu (10K) (1) VCC
10nF
SPI EEPROM VCC S (3) Q HOLD C D (3)
VSS Rpd(4.7k)
W VSS
GND
ai10919c
Figure 27. Recommended SPI connections - robust design

VCC Rpu (1) Rpu10 k SPI EEPROM S VCC Q (3) VSS Rpd Rpd (4.7 k) W VSS C D Rpd 100 k Rpd100 k HOLD (3)
(2)
VCC 10 nF
GND
ai10860c
Table 7.
Calculation for external pull-up and pull-down resistors in SPI products.

EEPROM output pin Q RPD > VIH master / IOH EEPROM
Recommended EEPROM input pins (S, W, HOLD, C, D) connection RPD RPU RPD > VIH EEPROM / IOH master
RPU > (VCC VIL EEPROM) / IOL master RPU > (VCC VIL master) / IOL EEPROM
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4.3
MICROWIRE family (M93C)

Only devices designed for 4.5 V/5.5 V range offer both TTL and CMOS input/output level compatibility. 2.5 V/5.5 V range products are only CMOS compatible.
4.3.1
Chip Select (S)

The Chip Select (S) input pin is connected to a CMOS Schmitt trigger input buffer (see Figure 28., Chip Select, Clock, Data input pins). It is recommended to control it with a pushpull buffer. Chip select (S) must stay low outside communication time slots and never be left floating. It is therefore strongly recommended to add a pull-down resistor to ensure a low level on the Chip Select pin at any time and in particular during power-up, power-down and the reset phase of the Master. The input pin leakage is negligible, typically a few nA. The input schematic, including the protection circuit, does not offer any open path to the VSS or VCC.
4.3.2
Serial Data (D) and Serial Clock (C)

Serial Data (D) and Serial Clock (C) input pins are connected to a CMOS Schmitt trigger input buffer (see Figure 28.).It is recommended to control them with a push-pull buffer. An external pull-down resistor (Rpd) on a Serial Clock (C) signal will prevent from an out-ofspecification configuration such as a clock rising edge while Chip Select goes low when the Master releases the bus (Hi-Z state, violation of the tSLCH timing)). An external pull-down resistor on Serial Data Input (D) will optimize signal control and standby current. Pull-down resistor values on Serial Clock (C) and Serial Data (D) are optimized if they are at least three times bigger than the pull-down value on the Chip Select (S) line. In this case, if the SPI bus is released, the Chip Select (S) line goes Low faster than the Clock (C) line goes low, and so, deselects the device before the Clock signal crosses the input buffer trigger point (area around VCC/2 is always sensitive). If the Clock (C) line cannot be pulled down and must be pulled up due to other system constraints, it is recommended to choose a weaker pull-up value (at least three times weaker) than the pull-down value on Chip Select (S). The input pin leakage is typically a few nA. The input schematic, including the protection circuit, does not offer any open path to the VSS or VCC.
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Hardware considerations Figure 28. Chip Select, Clock, Data input pins
S, C, D
Glitch Filter Schmitt trigger Typical 50ns
ESD/EOS Protection
Ai11727
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4.3.3
Organization Select (ORG)

It is not a CMOS input. If left floating, it is interpreted internally as being High. It is strongly recommended to connect it directly to the VCC or VSS pin of the device. Driving it dynamically implies that application software can handle specific MICROWIRE dual organization and switch from Single data byte management to Word data management. The input pin leakage is negligible, in standby mode, typically a few nA. The input schematic, including the protection circuit, does not offer any open path to the VSS or VCC. (See Figure 29.) Figure 29. Organization input ORG
(1)
ORG pin
ESD/EOS Protection
Ai11089
1. The Pull up is switched off in standby mode. Pull up is only active for a short time at chip select to ensure 1 level is latched when ORG is floating.
4.3.4
Serial Data Output (Q)

It is a push-pull tri-state output buffer. As the Serial Data Output is often in the Highimpedance state and connected to a Master input pin, it may be useful to connect a pull-up resistor to set a default value (corresponding to the Ready state) on the bus and thus prevent the Master input from toggling. Application designers must be aware that connecting several devices on Serial Data Output (Q) increases the capacitive load of the line. Access time of M93C ST EEPROM is tested with 100pF load (see Figure 25.: Output pin tri-state buffer)
4.3.5
Dont Use (DU)

Pin does not contribute to the normal operation of the device. It is reserved for use by STMicroelectronics during test sequences. The pin may be left unconnected or may be connected to VCC or VSS. No other connection is allowed. Direct connection of DU to VSS is recommended for the lowest standby power consumption mode.
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4.3.6
Recommended Microwire EEPROM connections

Recommended Microwire EEPROM connections are shown in Figure 30 and Figure 31. Note that for both circuits: 1. 2. A decoupling capacitor (10 nF min) must be placed as close as possible to the package pins VCC and VSS. A 50 Ohm resistor can be connected to VCC if extra filtering on VCC is needed or if an identified latch-up risk is to be minimized.
Figure 30. Recommended Microwire connections - safe design

VCC
(1)
10nF
VCC
Rpd(10K)
Microwire EEPROM S VCC C DU ORG VSS
VSS
Rpd(10K)
D Q
GND
ai10920c
Figure 31. Recommended Microwire connections - robust design

VCC Rpu(10 k) VCC
10nF
(1)
(2) Microwire EEPROM S VCC
Rpd(10 k) Rpd 100 k VSS
C D Q
DU ORG VSS
Rpd 100 k GND

ai10861d
Table 8.
Calculating external pull-up and pull-down resistors in Microwire products

EEPROM input pins (S, C, D, W/ORG,) RPD > VIH EE / IOH master RPU > (VCC VIL EE) / IOL master EEPROM output pin Q RPD > VIH master / IOH EE RPU > (VCC VIL master) / IOL EE
Recommended connection RPD RPU
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4.4
PCB Layout considerations

The full system layout becomes ever more critical because of space constraints, high communication speed, noise due to interference and all EMC constraints.
4.4.1
Cross coupling
The cross coupling effect increases with the frequency and fine PCB technology. All floating signals or pins, weak pull-up or pull-down connections are very sensitive to cross coupling and antenna-like pick-up. All unused pins should be tied correctly (in general to VCC or VSS).
4.4.2
Noise and disturbances on power supply lines

Noise and disturbances on power supply lines may be source of unreliable EEPROM behavior. For a robust design it is recommended to place local decoupling capacitors. Low inductance capacitors in the range of 10nF to 100nF are usually preferred. Electrolytic capacitors in the range of 1F to 100F should also be placed close to the power supply source of the system.Avoid Ground and VCC loops on the PCB as it increases the sensitivity to electromagnetic fields. (See Figure 32., PCB decoupling.)
4.4.3
Communication lines
In cases of interference, EMC, disturbance or interfacing issues in ICs, it is possible to insert resistors on:

communication lines between 2 devices (< 1k) in a way that it is compatible with the communication speed.
power-supply lines with limited driving capability to filter the noise and interference generated by connected devices (< 50)
These solutions are described in Section 4: Hardware considerations. Figure 32. PCB decoupling
VCC
+
1 F < C2 < 100 F
VCC EEPROM VSS 10 nF < C1 < 100 nF Other ICs
GND
Ai11079b
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Software considerations
The purpose of the suggestions discussed below is to help the application designers make the most of STs EEPROM products, and to help them improve the system robustness and compatibility in the view of future shrinks and evolution.
5.1
EEPROM electrical parameters

Low-level drivers (hardware dependent) must follow the EEPROM electrical parameters for correct communication. EEPROM samples are not absolute references for software validation as they are not representative of production variations. EEPROM timings are tested to be compliant with the values given in the datasheets and a small change in typical values over the production is normal. The values quoted in the datasheets are the unique and definitive references, they correspond to minimum and maximum values to be taken into account for hardware and software calibration. Typical errors to be avoided in applications are:

Input voltage levels not compatible with the specifications, VIL<0.3VCC and VIH > 0.7VCC. Excessive current requested from EEPROM data output buffer (output CMOS levels are no more guaranteed). Programming time not observed (tW is 10ms on old products and 5ms on new products) before issuing a new command. Data setup time in applications using high clock rate or very smooth waveforms with slow transitions. As a general recommendation rise and fall times of bus signals should be less than 10% of the clock period. Out of specification (too short) pulses on the Clock signal, Chip select signal or on Start/Stop conditions.
The behavior of EEPROM devices operating out of specification can never be guaranteed and is not always predictable. Moreover, major compatibility issues may arise when switching to a shrink device or using a compatible device from another supplier. When using a double source supplier for EEPROMs, the worst value of each single timing should be used as a reference for direct compatibility.
5.2
Optimal EEPROM Control

EEPROM devices are simple products with few operating modes and instructions. It is nevertheless worth focusing on the features that can be used to improve performance and application robustness.
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5.2.1
Page mode
The memory array is divided into pages. The size of a page is given on the first page of the product datasheet (it can be 8, 16, 32, 64, 128 or 256 Bytes). The Write Page mode is used to write a block of data bytes in a single shot. The Write Page mode sequence consists of a write instruction with the start address and one or more data Bytes directly followed by the internal execution of the operation (tW).

The maximum block size for page programming is limited by the page length of the product. A data block can be programmed starting at any offset inside the page. The address of the first data Byte to program is given in the instruction, other data Bytes are programmed in consecutive addresses. If the last page address is reached when shifting in the data Bytes, the internal address pointer rolls over to the first page address. It is therefore not possible to store data in two different pages with a single Write Page instruction. If more data Bytes than the page length (for instance 32) are shifted in, only the last data Bytes (last 32 Bytes) are programmed in the page (The 33rd data Byte shifted in will replace the 1st data Byte shifted in and so on).
To write to the EEPROM, it is recommended to use the Page mode instead of the Byte mode whenever possible. The programming time (tW) is independent of the number of Bytes to program and the Page mode has two main advantages: 1. 2. It speeds up the application when storing or updating data. It minimizes the high-voltage programming stress and naturally extends the cycling endurance.
5.2.2
Data polling
Data Polling is a very safe way of managing the EEPROM programming time (tW). The aim is to check the EEPROM status before sending the next instruction, so as to prevent bad master-slave communications. Data polling is a smart algorithm used to optimize the write wait time and control the correct operation of the device. Moreover, software which has data polling will be able to adapt to different devices regardless of the specified write time. This algorithm must be coupled to a timeout counter to limit the data polling time and avoid endless process.The timeout limit should be higher than the maximum write time of all devices used
(typically 15ms should be enough).
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IC products
In IC products, the device does not respond (NoAck) when a programming operation is in progress. Data polling thus consists in sending a Device Code in a loop mode and tracking the EEPROM acknowledgement. It is recommended to poll the device with a WRITE instruction. Figure 33. IC data polling algorithm
Write in Progress
START
Device Code (R/W = 0) (1)
No
ACK?
Yes
(Re)START
STOP
Ready for new command
Ai11083
1. Using the READ Device code (R/W = 1) is hazardous due to I2C protocol constraints.
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SPI products
In SPI products, a specific instruction (Read Status Register - RDSR) is used to check the status of the WIP (Write In Progress) bit in the Status Register. A loop on the RDSR instruction checks the WIP bit status. As soon as it returns to "0", the device is ready to accept new commands. For compatibility reasons, it is recommended to send the full RDSR command each time instead of continuously reading the status register. Figure 34. SPI data polling algorithm
Write in Progress
Select (S=0)
Deselect (S=1) (1)
RDSR command
Ready Busy (8 bits)
=1
WIP bit
=0
Deselect (S=1)

Ai11082
1. Although ST EEPROM allow continuous read of the status register it is, for compatibility reasons, recommended to send each time the full RDSR command
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Microwire products
In Microwire products, the Data Output pin (Q) indicates the Ready/Busy status when the Chip Select pin (S) is driven High. Once the device is ready, the Q output goes highimpedance (Hi-Z) after a Start Condition. It is strongly recommended to not operate the Clock during the data polling sequence because as soon as the chip is ready, the logic will start to decode incoming bits. Figure 35. Microwire data polling algorithm
Write in Progress
(1)
Deselect (S=0)
Select (S=1)
Ready/Busy on Q pin
High
Q level
Low
(2) Deselect (S=0)

Ai11081
1. There is no difference in the data polling process if chip is deselected between 2 ready/busy checks. 2. It is strongly recommended not to operate the Clock during the data polling sequence because as soon as the chip is ready, the logic will start to decode incoming bits.
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5.3
5.3.1
Write protection
Software write protection
Use the software write protection features to protect sensitive data items:

IC products do not have a software write protection. In SPI products, 2 non-volatile Status Register bits (BP0, BP1) are dedicated to the software write protection. The upper quarter, the upper half or the whole memory array can be set as Read-Only. In 1 Kbit to 4 Kbit M93Sxxx Microwire products the amount of data to protect is directly set by a user instruction. The selected area becomes a Read-Only memory.
Data items like trace codes, identification codes, manufacturing configurations, default parameters and all sensitive data in general, can be software protected against corruption during field service. Software protection bits and registers are limited in terms of cycling and data retention in the same way as memory array bits.
5.3.2
Hardware write protection

By default the hardware write protection feature should be set and the time during which the device is left unprotected should be limited to the time required to issue and execute Write instructions. The hardware write protection is very effective against parasitic or hazardous instructions transiting on the interface bus. Also use the hardware write protection features during Power-up, Power-down and normal operation (Refer to the Hardware considerations).

The WC pin in IC products protects the entire array. The W pin protects the entire array by resetting the Write Enable Latch (WEL) bit in 1 Kbit to 4 Kbit SPI products whereas it protects the non-volatile bits of the Status Register in 8 Kbit to 512 Kbit SPI products.
It is recommended to change the state of the Write Protect pin only if no data transfer or program cycle is in progress. The Write Protect and Write Control pins should be controlled with very conservative timings:

1 clock cycle time clearance with no data transfer before the state transition 1 clock cycle time clearance with no data transfer after the state transition wait for the Write operation to complete (tW) to set up the protection again
This conservative sequence will not affect the communication speed but will ensure the safe operation of the products (see Figures 36 and 37). The Write Protect (W) signal for SPI, or Write Control (WC) signal for IC are glitch sensitive and a short (parasitic) pulse could cause a write request to be aborted. This feature can also be of great help in emergency situations like power loss or Master reset. See the Power supply loss and application reset section for details.
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Figure 36. .Recommended use of the WC Pin in IC products

WC
SDA
START + WRITE +ADDRESS + DATA + STOP
tW < 5ms
Clearance 1 Clock Period
ai10921
Figure 37. Recommended use of the W Pin in SPI products

W
Polling
SDA
WREN
WRITE +ADDRESS + DATA
tW < 5ms
ai10922
5.4
Data integrity
In automotive applications, the implementation of a data integrity strategy is mandatory. Several strategies are possible, but whatever the solution used, extra memory capacity is required to hold the extra data.
5.4.1
The checksum
It is perhaps the more commonly used method to prevent data loss, data corruption and poor communication. It consists in computing a checksum of the data to write and in storing it into the memory array as an additional data Byte. Checksums are particularly suitable for the secure communication of parameters that are often read and updated. To give applications more robustness, more elaborated checksum routines like Error Code Correction can also be used to correct detected errors.
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5.4.2
Data redundancy
It is also a good way of preventing data loss and data corruption. Data redundancy is more particularly adapted to the read-only data stored in the EEPROM. Typically, this kind of data is programmed once during module manufacturing and then only read during the whole application lifetime. As the data is never refreshed, there is a higher probability of facing a retention problem due to device defectivity or external disturbing factors. With redundancy, there is a backup on each read-only byte. The efficiency of Redundancy depends strongly on the physical structure of the memory. As described previously, the memory array is organized as rows (or pages) and columns where each Byte location (address) is the intersection of a row and a column. Two redundant data items should not share the same row (or page) and column but should be located at physically independent addresses (see Figure 38.). The following rules should be kept in mind by the designer:

The redundant data should not be in the same page or column as the page or column of reference. The address of the duplicated data should differ from original address by at least 1 bit in the column address and 1 bit in the page address (see Table 9., Column and page address bits according to page length).
Note:
More detailed information on memory array, data scrambling and address decoding are available on request. Table 9. Column and page address bits according to page length
Page Length Page of 16 Bytes Page of 32 Bytes Page of 64 Bytes Page of 128 Bytes Column Address Bits 4 LSB bits 5 LSB bits 6 LSB bits 7 LSB bits Page Address Bits All other MSB bits All other MSB bits All other MSB bits All other MSB bits
Figure 38. Example of how to duplicate data safely

D0 D1 Dn 1 Dn
Reference Data
Rows or Pages
Duplicated Data
Dn
Dn 1
D1
D0
Columns
ai10923b
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5.4.3
Checksum and data redundancy

Combining checksums and data redundancy is the best strategy. Applying the redundancy and checksum strategy to read-only data (2 or 3 copies with a checksum byte for each data block) improves the EEPROM robustness and, with it, data integrity. For cycled data, the checksum strategy is better suited than redundancy (data redundancy is not recommended as it increases the number of bytes cycled and so, it statistically increases the probability of fail by cycling stress).
5.4.4
Extra redundancy
Default backup parameters can also be stored in another non-volatile external or embedded Flash memory. The micro should then have the ability to copy back the data in the EEPROM when necessary.
5.5
Cycling endurance and data retention

Sometimes applications may overstress the EEPROM in terms of cycling. This must be considered as a serious issue. Even if EEPROM devices are able to withstand a very high number of write cycles they should not be used in replacement for a Non-volatile RAM buffer.
5.5.1
Datasheet specifications
The rated values in the datasheets are as follows:

more than 40 years data retention at 55 C more than 1 million Write cycles (a memory Byte can be cycled at least 1 million times) at 25 C 1 Write cycle is equivalent to 1 Write instruction independently of the number of Bytes written
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5.5.2
Temperature dependence
Write cycling and retention endurance are independent of the value of VCC (on ST products) but directly depend on the operating temperature. The higher the temperature, the lower the cycling performance. Refer to Section 1.1.3: Cycling limit of EEPROM cells. In Figure 39, the red line represents the maximum Write / Erase cycling limit at 1 Cell per Million failure rate. When performing cycling trials for EEPROM product qualifications, the failure rate is 0 until the intrinsic capability of the cells is reached. At this point the cells reach the end of their lives and the intrinsic failure rate becomes exponential as a function of the write cycles. ST has chosen 1 cell fail per Million cells cycled as the criterion to determine the intrinsic cycling performance of the product. This failure rate criteria of 1 Cell per Million is not a quality indicator but only a criteria to determine the intrinsic capability of the product. Therefore the cycling limit shown here is to be considered by system designers as a maximum to respect for each byte of the memory. Being above this limit is dangerous as the intrinsic capability of the cells is exceeded, very quickly inducing high failure rates. When an EEPROM mounted on a system fails after a few cycles it is due to extrinsic factors like manufacturing defects or specific application stress that are not considered here and cannot be measured during ST qualification tests. Extrinsic factors are the main contributors to the EEPROM quality failure rate observed by our customers. Figure 39. Write/Erase cycles vs. temperature
Write / Erase cycles versus tem perature w earout lim it 10000
10 cycles
1000
Safe application (below line)
Risky application (above line)
100 25 50 75 100 125 150 cycling tem perature (C)
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5.5.3
Defining the application cycling strategy

Regarding the cycling endurance, EEPROM users should be aware that the memory cells are the limiting factor. ST EEPROM products have no build-in function to limit cycling and therefore application designers are responsible for checking the number of write cycles executed on the EEPROM device. To ensure the safest conditions, it is strongly recommended to define a temperature profile of cycled data in the EEPROM.

Define the main temperature stages at which the EEPROM is operating in the end application. For each temperature, estimate the number of write cycles executed for each data block. For each data block (with different cycling profiles), calculate the cumulated cycling effect using Table 10. Application cycling profile evaluation(1)
Number of cycles(2) w x y z w+x+y+z % of specification max (w/1M) 100 = a% (x/600K) 100 = b% (y/300K) 100 = c% (z/150K) 100 = d% a + b + c + d%
Table 10.
Temperature 25 C 55 C 85 C 125 C Total
1. The table can be adapted according to the temperature profile by taking care of putting down the maximum cycling for each temperature (using Figure 39). 2. w, x, y and z are the forecast number of cycles for a specific data block.
If the Total percentage of cumulated cycles is below 100%, the data block can be cycled with no particular cycling strategy. If the Total percentage of cumulated cycles is above 100%, the intrinsic safe margin for cycling is exceeded and a data relocation strategy must be defined. Cycling on each EEPROM cell is limited as shown in Figure 39 but the number of cycles is not limited at device level. On this basis it is possible to define a data relocation strategy by distributing the total number of cycles over several memory locations as follows:

Define a cycling limit for each data block according to the application needs and product performance (see Table 10). Count the numbers of cycles executed on each data block (counter value can be stored in the EEPROM). When the counter exceeds the defined limit, the cycled data block must be relocated to another physically independent memory address. The software developer should not move it to a location in the same page (when possible, not in the same column either) as the reference column/page. This means that the 2 addresses should differ by at least 1 bit in the page address and, if possible, by 1 bit in the column address. See Table 9. for page and column address bits. The counter is then reset and must also change address.
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In addition, to optimize the number of cycles in the EEPROM and preserve the other data blocks in the memory array:
define data groups or classes (located in the same page) where data with similar update rates are gathered together. This will optimize the use of the Page mode instead of the Byte mode. the area containing the read-only parameters and the cycled items should be separated and made independent as much as possible. Two types of data should not share the same pages and, where possible, not the same columns.
Following the above rules, in laboratory environment, ST EEPROM devices have demonstrated to reach tens of millions of cycles, safely.
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Power supply loss and application reset
6
6.1

Application reset
In a running application the Master may happen to be reset (external reset condition, watchdog timer, ESD) while the power supply stays stable at its nominal value. When this occurs the challenge is to allow for the completion of the on-going write process or to stop correctly the on-going communication with the EEPROM. As Master reset is very often asynchronous, there is no way of predicting the current state of the EEPROM:
deselected in standby mode. This is the best and safest case. The EEPROM is in an idle state and will remain so if the hardware connections are correct. It will be ready to accept any new command when the Master is restarted. deselected performing an internal write cycle. It is not a problem as at the end of the self-timed internal write process, the device returns to the standby state. As the Master may restart while the EEPROM is still programming, at restart the Master must check that the EEPROM is ready by issuing a data polling sequence. selected receiving a command or answering to a Read command. This case is managed differently depending on the EEPROM protocol family.
The solutions discussed below regard an EEPROM that is selected and will not affect an EEPROM device that is already in standby or that has started a write operation. The aim of these recommendations is to stop the communication by deselecting the part to avoid disturbing an on-going write process or triggering an undesired write process.
6.1.1
I2C family
The basic principle for I2C products is to NOT issue a STOP condition when a reset occurs. Although a STOP condition terminates a communication, it can also give the start for an undesired write process if sent at the end of a data byte of write command request. On the contrary, the START condition is, on ST EEPROM, understood at any moment and will immediately reset the internal state machine.
Smart connections of EEPROM pins help to avoid a default STOP condition and allow a default write protection when the Master releases the I2C bus. Indeed, commonly used connections with pull-up on SCL and SDA pins increase the probability to issue a STOP condition when a bus is released (see Figure 40., .Application Reset I2C Bus). Refer to 4, Hardware considerations section for safe recommendations.
When the I2C bus has been released without a STOP condition, the EEPROM remains like paused in its communication and write protected by the WC pin until the Master is able to restart. Before accessing the EEPROM, the Master must follow the sequence below:
Master must first send a re-synchronization sequence to the EEPROM. It consists of 9 START conditions + 1 STOP condition to re-initialize the internal state machine and deselect the device safely. Refer to AN1471 for any help to implement this sequence. Master must check that EEPROM is ready (no write cycle in progress) by sending a data polling sequence. Refer to 5.2.2, Data polling. For the first read access to the EEPROM, it is recommended to set the address pointer with a Random Read instruction.
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These recommendations will maximize the control on the EEPROM in case of inadvertent Master reset. Recommendations for Master restart can also be the default sequence each time Master comes out of the reset state like after Power up. Figure 40. .Application Reset I2C Bus
RL SCL RL SDA SCL

SCL SDA
STOP condition possible
STOP condition
R<RL
RL
SCL SDA
Safe
Safe
SDA
Ai11090
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6.1.2
SPI family
Main recommendation for SPI products is to deselect the device in a safe way. The chip must be deselected taking care of the timings of Chip Select respect to the Clock rising edge.
Smart connections of EEPROM pins help to avoid deselect timing violation (tCHSL and tCHSH) when Master releases SPI bus. Refer to 4, Hardware considerations section for safe recommendations. At deselect, EEPROM will go into the standby state (see Figure 41., Application Reset SPI Bus). However, a write cycle may be triggered if the EEPROM is deselected between two data Bytes of a write instruction. On 4-Kbit or lower-density SPI device, setting the W pin to Low before deselecting the memory will prevent the write cycle execution. When Master restarts, it must run a data polling sequence to check that EEPROM is ready (no write cycle in progress). Refer to 5.2, Optimal EEPROM Control. As soon as the SPI device is ready, a WRDI instruction must be issued if the WEL bit in the Status Register is still set to 1. In so doing, the device is protected against any parasitic write instruction.
These recommendations will maximize the control on the EEPROM in case of inadvertent Master reset. Recommendations for Master restart can also be the default sequence each time Master comes out of the reset state like after Power up. Figure 41. Application Reset SPI Bus
SPI bus connections Controlled bus configuration at application reset
R S C R
S
C
Safe Safe
tSHCH timing violation with pull-up on C and S pins
(1)
Ai11091b
1. Pull-down on Clock pin will prevent tSHCH timing violation, if the SPI bus is released during a communication.
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6.1.3
Microwire family
Main recommendation for Microwire products is to deselect the device in a safe way. The chip must be deselected taking care of the timings of Chip Select respect to the Clock rising edge.
Smart connections of EEPROM pins help to avoid deselect critical configurations when Master releases Microwire bus. Refer to 4, Hardware considerations section for safe connections. At deselect, EEPROM will go into the standby state (see Figure 42., Application Reset MICROWIRE Bus). However when deselecting the EEPROM, a write cycle may be triggered if the EEPROM is deselected between two data Bytes of a write instruction. When Master restarts, it must run a data polling sequence to check that EEPROM is ready (no write cycle in progress). As soon as device is ready, an Erase/Write Disable (EWDS) instruction must be issued to disable any WRITE instruction. In this way, the device is protected against any parasitic WRITE instruction.
These recommendations will maximize the control on the EEPROM in case of inadvertent Master reset. Recommendations for Master restart can also be the default sequence each time Master comes out of the reset state like after Power up. Figure 42. Application Reset MICROWIRE Bus
SPI bus connections S C R R
Safe Safe
Controlled bus configuration at application reset
(1) The tSHCH timing violation
Ai11092b
1. Pull-down on the Clock and S pins will prevent tSHCH timing violation, if the MICROWIRE bus is released during a communication
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6.2
Power supply loss

Data integrity of Non-volatile memory is very often critical as applications rely on it for system start up and configuration. Power loss is critical for an EEPROM device when a Write instruction is being issued or executed. In this event, the on-going Write request or the internal write process in the EEPROM may not have completed, leading to data corruption and data inconsistency.
6.2.1
Hardware recommendations
Application designer will find below some guidelines and recommendations to handle in the best conditions power supply loss on systems designed with STMicroelectronics EEPROM memories. The power supply must de designed in such a way that power loss is detected and backup supply is supplied for a time allowing safe emergency ending of the system operations. The list below gives some useful elements to build a robust power management system:

use voltage regulators including an output voltage sensor. It gives power loss information to the Master before the supply is too low for system operation. use available MCU features such as the Auxiliary Voltage Detector and External Voltage Detector pin to create a delay between the detection of the low voltage and the system reset. use diodes, bipolar transistors or analog switches to create specific areas with backup power capacitors.
The extra delay time gained should be used either to allow for the EEPROM to complete any on-going write process or to allow for the Master to finish or interrupt safely the current communication with the EEPROM. In a running application it is not possible to distinguish these two possibilities, therefore the below recommendations must be considered all together.
6.2.2
Backup capacitor value for EEPROM supply

In case of inadvertent power loss, applications are very often faced with the situation where the EEPROM is operating while power supply is falling down. It is not recommended to operate the device and in particular to initiate write operations when the device is undergoing steady VCC transitions. ST EEPROM devices can however handle write cycles during smooth power supply transitions. A power supply transition is considered smooth when it allows a complete write cycle to be completed while VCC is continuously falling or rising within the authorized VCC range. Taking advantage of this possibility, a power backup capacitor can be designed to allow for the EEPROM to complete its on-going self-timed write operation in case of inadvertent power loss. The capacitor value is calculated so as to allow for the full write cycle to be executed:

l is the EEPROM supply current (ICC max) t is the EEPROM Write time (tW) U is the voltage drop from the nominal value to VCC min of the EEPROM Q = C U = I t => C = (l t) / U
For instance: C = (3 mA 5 ms) / 2 V = 7.5 F
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Figure 43. EEPROM Power Backup Capacitor

5V on
+ C
Vcc EEPROM Vss
Ai11753
1. Sometimes filtering capacitors placed after voltage regulators, are big enough to allow the EEPROM device to finish the Write operation. In this case, backup capacitors are no longer necessary.
For a complete and detailed calculation, the discharge current through the MCU protection diodes must be taken into account. The EEPROM inputs/outputs do not draw any current during write operations and only the pull-up resistors connected to the EEPROM VCC pin will discharge the backup capacitor through the MCU connection. Optimum robustness is obtained by adding a discharge path to ground. At power-down, the EEPROM is usually in the standby mode, where it draws little current (no more than a few A) and the backup capacitor takes a long time to discharge. The system designer must either:

take into consideration the long discharge time to allow the EEPROM VCC supply to reach ground level before switching the system on again or add a discharge path to ground to accelerate the discharge if the system may or must be re-started after a short time
When applying this recommendation, please read also Section 3.3.2: Power-up and Power On Reset sequence.
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6.2.3
Interruption of an EEPROM request

When the Power loss occurs while Master is still sending a command, it is recommended to have an emergency software procedure able to interrupt safely the request being sent to the EEPROM. The set of below recommendations is adapted to each product family.
IC Products
Emergency procedure to interrupt an I2C request:

Drive the WC pin High. One clock period pulse will inhibit the current write request. Send a START condition followed by a STOP condition. The re-synchronization sequence described in AN1471 can also be used. See Figure 44., Emergency sequence I2C products.
Figure 44. Emergency sequence I2C products
WC 1 Clock Period
START (1) + ..... + START (9)
STOP
~110s, at Fc=100kHz
Tw = 5ms
Obtaining power loss information
Effective power loss
Ai11093b
After the emergency sequence, the power supply of the EEPROM (through keep alive systems or a backup capacitor at the EEPROM level) should remain high enough to allow an eventual write cycle to end correctly.
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SPI Products (1Kbit to 4Kbit)

Emergency procedure to interrupt an SPI request:

Drive the W pin Low while the device is selected. One clock period pulse will reset the WEL bit in the Status Register (current write request will be ignored). Deselect the EEPROM by driving the S pin High.
Warning:
If the chip is deselected between two data Bytes of a write request and W has not been driven Low, a write cycle may be triggered.
SPI Products (8Kbit and larger)

Emergency procedure to interrupt a SPI request:

if possible drive W pin low while device is selected. Only the WRSR instruction will be ignored, write to memory are not affected by W pin for 8Kbit products and larger. Deselect the EEPROM driving S pin High.
Warning:
If the chip is deselected between two data Bytes of a write request, a write cycle may be triggered.
Figure 45. Emergency sequence SPI products

W
1 Clock Period
S ~2s, at Fc=1MHz Tw = 5ms

Ai11094b
Note:
If the emergency software sequence can be executed so that the EEPROM is not deselected at a data Byte boundary (multiple of 8 bits), there is no risk of triggering a write cycle.
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After the emergency sequence, the power supply of the EEPROM (through keep alive systems or a backup capacitor at the EEPROM level) must remain high enough to allow an eventual write cycle to complete correctly.
MICROWIRE products
Emergency procedure to interrupt a MICROWIRE request:

if possible drive W pin low for M93S devices. One clock period pulse will inhibit the current write request. deselect the EEPROM by driving the S pin Low.
Warning:
If the chip is deselected between two data Bytes of a write request and W has not been driven Low, a write cycle may be triggered (see Figure 46., Emergency Sequence MICROWIRE Products)
Figure 46. Emergency Sequence MICROWIRE Products

W
1 Clock Period S
~2s, at Fc=1MHz
Tw = 5ms

Ai11095b
1. W pin is only available on M93S products
Note:
If the emergency software sequence can be executed so that the EEPROM is not deselected at a data Byte boundary (multiple of 8 bits), there is no risk of triggering a write cycle. After the emergency sequence, the power supply of the EEPROM (through keep alive systems or a backup capacitor at the EEPROM level) must remain high enough to allow an eventual write cycle to complete correctly.
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6.3
Robust software and Default Operating mode

In sensitive applications such as automotive, safety or medical applications, it is not acceptable for a system to enter a lock state or an endless loop, because of bad EEPROM communications. In many cases, simple software rules can help to secure operation of the application.

It is recommended to use the data polling feature and a timeout counter to prevent the system from being locked by an endless EEPROM Write process. After each Write cycle, the software should always verify that data has been correctly programmed by reading back the data. Of course several attempts can be made in order to get the correct result. When reading data from the EEPROM, the applicative software should check whether the data is within an acceptable range or not and when required, switch to a default value allowing continuity in the application operation. As already recommended, data in the EEPROM can be duplicated and associated with a checksum and an Error Code Correction mechanism. In particular default parameters can be stored in a protected part of the memory array (Read-Only software configuration) or in another available non-volatile memory (like a Flash memory). The MCU should then be able to access flash memory in order to copy the missing parameters back to the EEPROM. Moreover, it is safer to have a default application operating mode that can run with a reduced set of default parameters.
Refer to the Optimized Use of the Device Features and Data integrity, Data redundancy and Checksum sections.
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Operating Conditions
Operating Conditions
There are many other operating conditions, imposed by the final application environment, that may also have an adverse affect on the EEPROM device (shortened lifetime or unreliable operation). They should be studied, and solutions must be found to minimize them.
7.1
Temperature
The temperature should be kept as low as possible, since high temperatures accelerate wear-out. At high temperatures, cycling endurance and data retention are reduced because of charge trapping in the thin oxide of the memory cells. When applications are designed to run in hot environments with high cycling requirements, it is strongly recommended to establish a temperature profile and discuss it with the ST EEPROM quality support (refer to Section 5.5: Cycling endurance and data retention).
7.2
Humidity and chemical vapors

Boards should always operate in a clean and dry environment. Humidity and dirt of any kind can cause corrosion and short circuits between package pins and tracks.
7.3
Mechanical stress
EEPROM packages cannot withstand excessive weight, local pressure or strong shocks.
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Conclusions
Conclusions
To meet the very stringent requirements of the automotive market, STMicroelectronics and its customers need to collaborate, to combine STs know-how in EEPROM devices with the customer's application needs. The result will be the design of more robust EEPROM products and applications destined for high-end systems with a very high operating reliability. ST EEPROM are designed to fit automotive requirements. Target specifications are updated in response to issues, which are reported directly from the field. ST EEPROM products do not only offer a high level of performance but are increasingly offering a better level of operating robustness and reliability. This robustness is directly measured by our customer in their applications where although not all conditions are predictable, ST EEPROMs have demonstrated to be able to increase operating stability being more tolerant and flexible for out of specification signals. This Application Note gives the EEPROM user a basic knowledge of ST EEPROM products and can also be considered as a kind of reference point. Descriptions on the storage mechanism, product architecture and interface circuit are useful to gain better understanding of the devices operation and its limitations. Hardware connections, software and data management recommendations are essential guidelines to improve the reliability of the EEPROMs operation. Using this document, designers can understand, which recommendations are most relevant to their own applications. Indeed, storing non-volatile and binary information in a flexible and safe manner, is not simply a matter of correctly managing the flow of digital information.
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References
References

AN1001, Choice of Serial EEPROMs Requires Understanding of Bus Differences. AN1292, How to Make An Application Specific Memory AN1471, What Happens to the M24xxx IC EEPROM If the IC Bus Communication is Stopped?
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Revision history
10
Revision history
Table 11.
Date 28-Oct-2005
Document revision history

Revision 1 Initial release. Section 1.1.3: Cycling limit of EEPROM cells, Section 5.2.1: Page mode, Section 5.4.1: The checksum, Section 5.5: Cycling endurance and data retention, Section 6.1: Application reset, Section 6.2: Power supply loss modified. Small text changes. Small text changes. Figure 15: Power-Up and Figure 39 modified (paragraph added to explain Figure 39). Table 5: Calculation rules for pull-up resistor on SDA(1) and Note 1 modified. Note modified below Figure 22. Section 5.4: Data integrity modified. Section 6.2.2: Backup capacitor value for EEPROM supply modified. General recommendation applying to all EEPROM products paragraph removed and content transferred to Section 3.3.2 on page 23. Small text changes. In the SPI family the S pin must remain above VIH = 0.7VCC during power-up (see Section 4.2.1: Chip Select (S)) and Write Protect (W) behavior specified. Pull-up and pull-down resistances discussed in Section 4.2.3: Serial Data Input (D) and Serial Clock (C) (SPI) and Section 4.3.2: Serial Data (D) and Serial Clock (C) (MICROWIRE). Pull-down resistor value on C modified and pull-down resistor added to D line in Figure 27: Recommended SPI connections - robust design and Figure 31: Recommended Microwire connections robust design. Maximum C2 value modified in Figure 32: PCB decoupling. Changes
15-May-2006
26-Oct-2006
15-Jan-2007
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AN2014 Application note

How a designer can make the most of STMicroelectronics Serial EEPROMs

AN2014 - Application note

Electrical structure of ST serial EEPROM arrays . . . . . . . . . . . . . . . . . . . 14

Choosing a suitable EEPROM for your application . . . . . . . . . . . . . . . 17

Recommendations to improve EEPROM reliability . . . . . . . . . . . . . . . 19

Electrical over-stress and latch-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Power supply considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

AN2014 - Application note 4.1.4 4.1.5

Contents Write control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Recommended I2C EEPROM connections . . . . . . . . . . . . . . . . . . . . . . 28

SPI family (M95) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

MICROWIRE family (M93C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PCB Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Cycling endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Contents 5.5.2 5.5.3

Power supply loss and application reset . . . . . . . . . . . . . . . . . . . . . . . 50

Power supply loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Robust software and Default Operating mode . . . . . . . . . . . . . . . . . . . . . 59

AN2014 - Application note

AN2014 - Application note

AN2014 - Application note

Construction of an EEPROM device

Construction of an EEPROM device

Construction of an EEPROM device Figure 3.

AN2014 - Application note

Floating gate reservoir full of electrons (Erased state)

AN2014 - Application note

Construction of an EEPROM device

Reading the value stored in a memory cell

Construction of an EEPROM device

AN2014 - Application note

Writing a new value to the memory cell

1. Characteristic threshold Vth increases and becomes positive as shown in Figure 3.

AN2014 - Application note Figure 7.

Construction of an EEPROM device

1. Characteristic threshold decreases and becomes negative as shown in Figure 4.

Construction of an EEPROM device Figure 8.

AN2014 - Application note

5ms Write Cycle = Auto-Erase + Program

AN2014 - Application note

Construction of an EEPROM device

Cycling limit of EEPROM cells

Horizontal electric barrier disturbing erase and write

Channel Region Vertical electric path leading to leakage

Construction of an EEPROM device

AN2014 - Application note

Electrical structure of ST serial EEPROM arrays

Memory array architecture

8 FLOTOX transistors Control Gate transistor Memory Cell Select transistor

AN2014 - Application note

Construction of an EEPROM device

MSB Address Bits

LSB Address Bits

Read/Write Analog Voltages

Bit-line and Cg-line Latches: RAM Buffer Cg-lines and Bit-lines

Intrinsic electrical stress induced by programming

Construction of an EEPROM device

AN2014 - Application note

AN2014 - Application note

Choosing a suitable EEPROM for your application

Choosing a suitable EEPROM for your application

Choosing a memory type suited to the task to be performed

Choosing an appropriate memory interface