IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 52, NO.

2, FEBRUARY 2005

379

Enhanced Phase Noise Modeling of Fractional-N Frequency Synthesizers

Himanshu Arora, Student Member, IEEE, Nikolaus Klemmer, Senior Member, IEEE, James C. Morizio, Member, IEEE, and Patrick D. Wolf

AbstractMathematical models for the behavior of fractional-N phase-locked-loop frequency synthesizers (Frac-N) are presented. The models are intended for calculating rms phase error and determining spurs in the output of Frac-N. The models describe noise contributions due to the charge pump (CP), the phase frequency detector (PFD), the loop lter, the voltage control osicllator, and the deltasigma modulator. Models are presented for the effects of static CP gain mismatch, CP dynamic mismatch and PFD reset delay mismatch. A simple analytic expression shows the level of sequence noise caused by static CP current mismatch. We further show that un-equal rise time and fall time constants of the CP result in dynamic mismatch noise. Reset delay mismatch in PFD is shown to also contribute signicantly to close-in phase noise. The model takes into account the reduction in CP thermal and icker noise due to the changing duty cycle of Frac-N CP. Our model is therefore useful in characterizing the noise performance of Frac-N at the system-level, simplifying the design of fractional-N synthesizers and transmitters. Analytical and simulated results are compared and show good agreement with prior published data on Frac-N realizations.

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Index TermsCharge pump (CP), deltasigma, dynamic mismatch, dynamic mismatch corner frequency, icker noise, icker noise corner frequency, fractional-N frequency synthesizer (Frac-N), frequency synthesizer, gain mismatch, gain mismatch corner frequency, phase frequency detector (PFD), phase noise, reset delay mismatch, rms phase error, spurs, thermal noise, voltage-controlled oscillator (VCO).

I. INTRODUCTION

HE PHASE noise of fractional-N frequency synthesizers (Frac-N) is a key gure of merit in communications system design. From a design perspective, the quantities of interest are the spectral properties of the output noise of Frac-N and the rms phase error. In [8], [9] behavioral simulation techniques for Frac-N are presented. These techniques allow fast simulation of Frac-N in the time domain by assuming the charge pump (CP) is linear and its effect is included by merely scaling the output of the phase frequency detector (PFD) by the CP current [9]. This approach fails to capture nonlinearities of the CP and PFD due

Manuscript received June 21, 2004; revised September 13, 2004 and September 29, 2004. The work of H. Arora, J. Morizio, and P. Wolf was supported by the Defense Advanced Research Projects Agency (DARPA) Defense Sciences Ofce under Contract N66001-02-C-8022. This paper was recommended by Associate Editor Y. Lian. H. Arora and J. Morizio are with the Department of Electrical and Computer Engineering, Duke University, Durham, NC 27708 USA (e-mail: ha@ee.duke.edu; jmorizio@ee.duke.edu). N. Klemmer is with Analog Devices, Raleigh, NC 27606 USA (e-mail: nikolaus.klemmer@analog.com). P. Wolf is with the Department of Biomedical Engineering, Duke University, Durham, NC 27708 USA (e-mail: patrick.wolf@duke.edu). Digital Object Identier 10.1109/TCSI.2004.841594

to CP static gain mismatch, CP dynamic mismatch, and PFD reset delay mismatch. We found these to be major contributors of in-band Frac-N noise. In addition, the noise due to the time varying duty cycle of CP is not considered. Consequently, the simulated in-band noise oor in [9] shows a deviation from the measured results. In [11] a periodic steady state (PSS) analysis technique is used to capture CP gain mismatch noise in PLL systems. However, as pointed out in [9] this technique cannot be extended to Frac-N phase-locked-loop (PLL) systems as the Frac-N CP is operating with a time-varying nonperiodic duty cycle in the steady state. [10] presented the calculation of noise due to CP nonlinearities by assuming the timing error at the input of PFD is uniformly distributed. However, as pointed out in [10], for higher order deltasigma modulators (DSMs), the distribution of timing error at the input of PFD is Gaussian. Hence, the need for an improved noise model. The Frac-N model presented in this paper is a combined time and frequency-domain model. It simulates the noise performance of all the blocks of Frac-N, as shown in Fig. 1. Linearized frequency-domain analysis captures the noise due to the loop lter resistors, and the voltage controlled oscillator (VCO). Time-domain simulation facilitates calculation of the noise due to the nonlinearity of CP gain mismatch, CP dynamic mismatch, PFD reset delay mismatch, and the reduction in CP thermal noise, icker noise and icker noise corner frequency due to the time-varying duty-cycle of the CP. The nonlinearities in CP/PFD cause distortion which appears as white noise at low offset frequencies [6], [10], [20]. In this paper, we present a closed form expression of the CP gain mismatch noise and its dependence on the order of DSM for a Gaussian distribution of timing error at the input of PFD. This analytically derived result matches well with discrete time-domain simulation results. The rest of the paper is organized as follows. Section II presents an overview of the architecture and the principles of Frac-N. Section III explains in detail the derivation and modeling of DSM noise due to nonlinearities in the CP and the PFD: CP gain mismatch noise, CP dynamic mismatch noise, PFD reset delay mismatch noise, noise due to delay mismatch in prescalar, and the noise due to jitter in the PFD. Analysis and simulation of different topologies and orders of DSM used in Frac-N, considering the above noise mechanisms, is also presented. Section IV derives CP thermal noise, CP icker noise, and CP icker noise corner frequency under time-varying duty-cycle conditions. VCO noise and thermal noise from the loop lter resistors are presented in Sections V and VI, respectively. In Section VII, to verify the accuracy of the model, results from our model are compared with other published results of Frac-N [1], [3]. Finally, Section VIII concludes the paper.

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Fig. 1.

Frac-N.

II. GENERAL DESCRIPTION OF FRAC-N Fig. 1 shows a typical Frac-N. The input to the deltasigma with modulus is , where and are integers and the output sequence time average is . The DSM output sets the . As a instantaneous value of the multimodulus divider consequence, an instantaneous phase error appears at the PFD input. The CP converts this phase error to current pulses and delivers charge to the loop lter. The loop lter voltage controls the VCO frequency and ensures that the Frac-N remains in lock. The frequency-domain phase response of the Frac-N PLL, to the expressed in terms of the ratio of output phase reference phase , is given by

The overall rms phase error at the synthesizer output is given by [4]

III. NOISE MODEL OF DSM WITH NONLINEARITIES OF CP AND PFD Phase noise PSD in the output of Frac-N, due to an th-order and a quanDSM with noise transfer function (NTF) tization step of 1 is given by [21], [22]

rad Hz

(1)

where is the VCO gain in radians per second per volt, is PFD/CP gain in amperes per radian is the CP current in amperes, is the nominal division ratio, and Z(s) is the loop lter impedance. The objective of the modeling process is to calculate the power-spectral density (PSD) of the phase at offset frequencies , due to each of uctuations the Frac-N building blocks. The range of frequencies span to . is the two-sided spectral density [17] from with the unit radians square per hertz (also expressed in decibel scale). The Frac-N noise analysis cycles per hertz on depends on a number of assumptions. 1) The Frac-N is in lock (the average phase error at the input of PFD is constant). 2) All the noise sources in the loop are uncorrelated. 3) The loop behavior is linear (superposition holds). Phase noise due to the individual blocks of Frac-N is added, to give an overall two-sided phase noise PSD

where is the clock rate of DSM. Equation (1) is derived using standard linear-time-invariant (LTI) concepts. Hence, it fails to capture noise mechanisms which occur due to nonlinearities in the Frac-N, namely: 1) gain mismatch in Up and Dn currents of the CP [1], [2]; 2) dynamic mismatch in Up and Dn currents of CP; 3) reset delay mismatch in the PFD; 4) propagation delay mismatch in the feedback dividers; 5) the noise oor increase due to dithering and possible quantizer overload in the digital DSM. The time-domain simulation of DSM captures the noise due to above nonlinearities and thus should give a more accurate representation of phase noise PSD than the linearized frequency-domain model of (1). The methodology of discrete time open-loop simulation of the Frac-N PLL to capture the nonlinearities of CP/PFD was reported in [4]. A. Ideal CP Behavior In order to determine the noise due to the nonlinearity of CP/PFD, we rst derive the expression for instantaneous phase error at the PFD input. Fig. 2 illustrates the relationship between

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Fig. 2.

Timing waveform of reference clock and feedback clock from divider.

the th rising edge of the divider output, given by the th rising edge of the reference clock given by

, and
Fig. 3. CP even-order nonlinearity as a combination of ideal and error CP component.

(2) (3) is the instantaneous integer division ratio, deIn (2), cided by the output of sigma delta (4) (5) In the above equation, is the time period of the reference is the VCO time period. From (2), (3), and (5), we clock, obtain

Fig. 4. (a) Original  sequence. (b) On-time for Up CP with  (c) On-time for Dn CP with   .

+

(6) We introduce the symbol , representing the time-of-arrival error (in seconds) of the th feedback edge with respect to the corresponding reference clock edge (7) From (4), (6), and (7), we obtain (8) Assuming the -transform of the output of a general DSM as (9) where NTF(z) is the NTF and is the rms quantization error, we obtain the -transform of the timing error at the PFD input as (10) is one order Thus, the PSD of the instantaneous phase error less than the PSD of the output of DSM itself. The CP converts to Up or Dn current pulses, the instantaneous timing error depending on the polarity of the phase error. The ideal charge to be delivered to the loop lter is given by

The equivalent ideal CP current is given by

However, due to CP/PFD nonlinearities an incorrect amount of charge is delivered to the loop lter. This distorts the CP current spectrum, thus raising the Frac-N in-band noise oor. B. DSM Noise Due to CP Static Gain Mismatch CP gain mismatch occurs when the Up and the Dn currents of the CP are of un-equal magnitude and (11)

where is the relative mismatch of the Up and Dn currents. The resulting even-order CP gain mismatch nonlinearity shown in Fig. 3 can be expressed as a sum of ideal and error CP components. The charge packets delivered to the loop lter during Up and Dn pulses are if if In order to compensate for the nite rise time and fall time of the CP, as shown in Fig. 4, both the Up and Dn CPs are turned [1], [12]. Then, the net on for a nite duration of time charge delivered to the loop lter is given by if if

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=T

TABLE I DSM

FOR DIFFERENT ORDERS OF (ANALYTICALLY COMPUTED)

Fig. 5. CP gain mismatch noise corner frequency.

For the following, we assume that the distribution of is approximately Gaussian [10] with mean 0 (under lock) and vari, where ance

Using (11), we obtain (12) delivered to the loop lter is zero. In lock, the net charge Thus, the rst term in (12) represents the correct noise shaped , and is responsible for term. The second term depends on the gain mismatch originated noise. The third term together with the nite average charge of the second term merely results in a dc offset charge which the loop in lock corrects by introducing a nite static phase error at the PFD input. Focusing on the distortion term in (12), we separate the CP current into an ideal term and a CP gain mismatch term given by

and is the variance of without considering the effects of dithering. Then, from (13), the total power in the ideal CP current is (18) Equating the two power expressions for ideal CP current pulses (17) and (18), yields

To compute the power in the CP current error component , we need to evaluate the variance of . Since we have assumed as a Gaussian random variable, we have (19) Under the assumption that the error CP current exhibits an approximately white noise PSD, the PSD can be obtained from (14) and (19), as

(13) (14) As shown in Fig. 5, equating PSD of the ideal CP current and the gain mismatch CP current, allows the characterization of the effect of static gain mismatch via a CP gain mismatch noise corner frequency. From (10) and (13), using a chain-of-integrators (MASH) [7] NTF for the DSM, we have the -transform of the ideal CP current: (15) For quantization step 1, the rms quantization error is with white PSD . Practically, dithering is done in DSM to avoid limit cycles. Thus, the quantization , where (for no error PSD is modeled by, . Using (15), dithering). Typical values for are we obtain the PSD of the ideal CP current as

(20) Equating the PSD of the ideal CP current ((16), ) and error CP current (20), the expression for the gain mismatch noise corner frequency can be expressed as (21) where the analytically computed values of for different orders of DSM are listed in Table I. From (21), the following can be inferred about the gain mismatch noise corner frequency. 1) It increases with increasing CP current mismatch ac. cording to 2) Increasing the order of DSM increases the gain mismatch noise corner frequency. 3) Dithering has no effect on the gain mismatch noise corner frequency. 4) The higher the variance of the phase error, the higher the gain mismatch noise corner frequency.

(16) The total quantization noise power in the ideal CP current is obtained by integrating (16) (17)

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TABLE II FRAC-N WITH DIFFERENT DSM

Fig. 6. (a) MBSL-I DSM of [1], [2]. (b) MBSL-II DSM of [5].

Further, given the CP static current mismatch , from (20) the mismatch induced phase noise PSD referred to the PFD input can be expressed as

rad Hz

(22)

Equation (20), (21), and (22) were derived under the assumption that the static phase error (partly due to 3rd term in (12)) is much smaller than the variance of the delta-sigma induced phase error at the input of PFD. The negative feedback action of the closed-loop PLL tries to make a zero time-average charge delivered from CP (including leakage) to the loop lter. It does this by introducing a timing offset at the input of PFD which is the negative of the static offset term. If the magnitude of this timing offset is more than the variance of the phase error introduced by the DSM then only the Up or Dn CP current pulsewidth is varying, while the other is xed to the minimum pulsewidth . Thus, the noise due to the CP static mismatch [due to 2nd term in (12)] is reduced. This was experimentally veri. ed in [10] by the introduction of a CP offset current Table II presents in detail the peak-to-peak dither amplitude (in terms of number of quantization steps) added to the quantizer input and the number of levels used in the quantizers for simulating the DSMs used in Frac-N. The output of the DSM sets

the span of divider values required for realizing the Frac-N. Fig. 6 depicts two different multibit single-loop (MBSL) DSMs used in [1] and [5]. Simulated performance in terms of quantizer output range and the variance of the timing error at the input of PFD, for different DSM topologies, is summarized in Table II. for different orders The simulated values of of DSMs is in good agreement with the analytically computed values listed in Table I, thus verifying our earlier assumption about the Gaussian nature of the timing error at the input of PFD

for for for for for (23) Fig. 7 shows PSD plots of the ideal CP current (13) and the CP gain mismatch error current (14) for Frac-Ns using the DSMs listed in Table II. The PSD of the ideal CP current using thirdorder DSM has a slope of 40 dB/decade and a fourth-order DSM has a slope of 60 dB/decade. Fig. 7 shows, for a given CP static gain mismatch, MBSL-I has lower folded quantization noise than MASH-12 and MASH-1111. This is because the quantization noise variance in MBSL-I DSM is lower than MASH-

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Fig. 7. DSM noise due to 10% CP static gain mismatch ( = 0:10) referred to the input of PFD. (a) MBSL-I. (b) MASH-12. (c) MASH-11. (d) MASH-1111. TABLE III PREDICTED AND SIMULATED CP GAIN MISMATCH NOISE CORNER FREQUENCY FOR DIFFERENT FRAC-Ns

1111 and MASH-12 (Table II) thus reducing folded quantization noise. In addition to this, poles and zeros of NTFs of different DSMs (23) decide the frequency distribution of quantization noise. Fig. 7 shows that MBSL-I has lower quantization than MASH-12 and MASH-1111. This, in noise around conjunction with lower span of divider values required to implement MBSL contributes to reduced CP gain mismatch noise. Fig. 8 and Table III compare the predicted and the simulated value of gain mismatch noise corner frequencies for the Frac-Ns listed in Table II. It illustrates that the CP gain mismatch noise is higher for Frac-N that use a higher order of DSM. As a result of the higher order of the DSM, the quantization noise at higher offset frequencies is increased. CP distortion raises the Frac-N in-band noise oor thus, negating the advantages of increasing the order of the DSM. Amongst the Frac-N using third-order DSM, MBSL-I and MBSL-II are more robust to CP gain mismatch, partially due to the fact that they use the minimum range of divider values (Table II) and hence minimize the

. As shown in Table II, both MBSL-I and MBSL-II variance have the same divider range and the peak to peak dither values. In-spite of this, MBSL-II offers a reduced CP gain mismatch noise and CP gain mismatch noise corner frequency (Table III) than MBSL-I. This is because MBSL-II has lower variance of than MBSL-I (Table II). Furtiming error ther, it is interesting to note that even though the range of divider values is different for Frac-N with MASH-12, MASH-21 and MASH-111 DSM, their gain mismatch noise corner frequency is approximately equal (Table III). This is because the gain mismatch corner frequency depends on the variance of which, as shown in Table II, is approximately equal for these topologies. Further, the predicted value of gain mismatch noise corner frequency (21) matches well with the simulated value. The correlation between the predicted and simulated values of gain mismatch noise corner frequency increases and the phase error becomes more Gaussian as the order of DSM increases. Further, the slope of the gain mismatch noise corner

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Fig. 8. Predicted and simulated CP gain mismatch noise corner frequency for different Frac-Ns.

) Fig. 9. (a) Timing diagram of two consecutive Up CP pulses ( ) and ( at the input of PFD. (b) Up CP current pulse with nite rise time and fall time constants. (c) Dn CP current pulse with nite rise time and fall time constants.

frequency vs CP gain mismatch is where is the order of DSM.

on a loglog scale,

C. DSM Noise Due to CP Dynamic Mismatch Generally, nonminimum gate length devices are used in CP in contrast to the minimum gate length devices used in PFD. Thus, and fall time as shown in Fig. 9, the nite rise time constants of the CP affect the charge delivered to the loop lter. To analyze the resulting dynamic mismatch effect, we assume rst-order CP dynamics with un-equal rise and fall time constants for the respective current pulses. For the case of two ) as shown in Fig. 9 the net consecutive Up pulses ( and charge delivered to the loop lter during Up pulse is given by

Fig. 10.
(

(a) Timing diagram of CP Dn pulse ( ) followed by an Up pulse ) at the input of PFD. (b) Up CP current pulse with nite rise time and

fall time constants. (c) Dn CP pulse with nite rise time and fall time constants.

where

For the case of Dn pulse followed by Up pulse as shown in Fig. 10, the net charge delivered to the loop lter Dn pulse is given by (24a) at the bottom of the next during page, where

For and (for all ), the above expressions can be resolved into (24b) at the bottom of the next page. Thus, the CP current consists of an ideal term and a CP dynamic mismatch term given by (24c), shown at the and , bottom of the next page. Assuming the following cases emerge. 1) CPs settle fully even for the minimum pulse duration . 2) CPs do not settle fully (either or both Up/Dn pulses). If is large enough (case 1), then all the Up and Dn CP pulses fully settle and deliver equal amounts of error charge to and , the loop lter, given by respectively. Therefore, the error charge delivered to the loop lter is independent of , and simply results in a dc offset. The loop takes care of the dc offset by introducing a nite static phase error in the locked condition. On the contrary, an interesting situation (case 2) occurs when is not large enough for the CP to fully settle and . Here, wider CP pulses have enough time to settle, whereas the narrower CP pulses do not have suf, the Up and the cient time to settle. For large Dn CP pulses will deliver error charge to the loop lter, given

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by and , as in case 1. On the con, the Up CP pulses deliver an error trary, for small charge given by and Dn CP pulses deliver an error charge given by . This unequal error charge being delivered for wide and narrow CP pulses is a nonlinear function of . This results in dynamic mismatch and distorts the CP spectrum. These results have been summarized in and , there is Table IV. Note that for no distortion created in either case. In [6] and [23], efforts were made to ensure that the CP was turned on and turned off quickly. and . It will This helped in minimizing also be benecial to ensure that the rise and fall constants are . matched , For evaluation, the minimum turn-on time of the CP rise time constant and fall time constant were chosen to be consistent with other parameters found in [1]. Fig. 11 plots different cases of CP dynamic mismatch noise and dynamic mismatch corner frequency for a Frac-N using

MBSL-I DSM. The CP parameters used for the simulation of different cases of dynamic mismatch in Fig. 11 are listed in Table V. Fig. 12 plots the PSD of the ideal CP currents and the PSD of the CP error currents due to dynamic mismatch for various DSM topologies. The set of parameters used for the simulation of dynamic mismatch is listed in Table VI. The results show that the dynamic mismatch noise and its corner frequency are the highest for MASH-1111. Further, amongst Frac-Ns, using thirdorder DSMs, MBSL-I is more robust to CP dynamic mismatch noise than MASH-12. From Figs. 11 and 12, the following can be concluded about CP dynamic mismatch noise for a given set of rise and fall time constants: 1) The higher the order of DSM the higher is the dynamic mismatch noise and corresponding noise corner frequency, as a higher order DSM causes a higher spread of .

(24a)

if if if (24b) if

if

if

(24c)

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Fig. 11.

MBSL-I DSM noise due to CP dynamic mismatch referred to the input of PFD. CP parameters for cases (a), (b), (c), and (d) are listed in Table V.

TABLE IV DYNAMIC MISMATCH CASES

4) Local matching of the rise time and fall time constants Up will eliminate the and Dn CPs dynamic mismatch noise. 5) Matching the rise time constant of Up and Dn CPs will reduce the impact of dynamic mismatch . D. DSM Noise Due to PFD Reset Delay Mismatch Fig. 1 shows a conventional D-ip-op (DFF) based PFD being used in Frac-N. Short pulses (FB) appear at the output of is the output of a crystal oscillator with the prescalar, and approximately 50% duty cycle. The minimum CP on-time is created by the feedback delay circuit. The propagation delay from the Reset input to the output (Up and Dn) of the DFF is . We are assuming that the propagation delay through the AND gate and delay circuit, is independent of whether the Up or Dn and represent the signal changes its state rst. In Fig. 13, DFF reset propagation delay for high and low clock input levels, is the FB clock pulsewidth. For the FB pulse arrespectively. riving early [Fig. 13(a)], the net on-time of the CP is given by (25) is the arrival time of the rising edge of reference where is the arrival time of the rising edge of feedback clock, and clock. The un-equal propagation delays of the DFF ( and ) result in an offset from the ideal on-time of the CP given by . On the contrary, for a FB pulse arriving late [Fig. 13(b)], both the REF and FB signals are high when Reset goes active. The net on-time of the CP for this case is given by (26)

TABLE V PARAMETERS OF CP USED FOR SIMULATING DYNAMIC MISMATCH IN FIG. 11

2) The lower the variance of the timing error at the input of PFD, the lower is the CP dynamic mismatch noise, and its corresponding noise corner frequency. 3) To minimize CP dynamic mismatch noise for Frac-N using higher order DSMs, a larger minimum turn-on time is required so that the Up and Dn CPs of the CP fully settle for all . This increases the CP thermal and icker noise contributions to the overall in-band noise oor. Hence, there will be an implementation dependent for minimum phase noise. optimum

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TABLE VI PARAMETERS OF CP USED FOR SIMULATING DYNAMIC MISMATCH IN DIFFERENT FRAC-Ns

Fig. 12.

DSM noise for various Frac-Ns due to CP dynamic mismatch, referred to the input of PFD. (a) MBSL-I. (b) MASH-12. (c) MASH-11. (d) MASH-1111.

In this case, the net CP on-time is correct. The objective is therefore to derive the noise PSD due to reset delay mismatch in the DFF used in the PFD. As shown in (25) and (26), reset delay mismatch modies the net on-time of the CP. We make the assumption that we get the timing offset with probabilities p and in a statistically independent manner. As before, the instantaneous value of (output of DSM), sets the divider value which in-turn decides the net CP on-time with probability with probability (27)

TABLE VII RESET DELAY MISMATCH CASES

is the CP on-time taking into account the effect of where DFF reset delay mismatch. The total noise power in the distorin (28)] is tion component [represented by random variable given by its variance as (28) As observed from the reset delay mismatch noise PSD plots, reset delay mismatch results in approximately white noise. The PSD of the phase noise due to reset delay mismatch, referred to the input of the PFD is therefore given by rad Hz (29)

In the worst case scenario , there exists equal probaof occurrence of error . bility Fig. 14 shows the PSD of ideal CP current and CP error curand rent due to PFD reset delay mismatch of in Frac-Ns with different DSMs (Table II). Note that the jitter noise oor due to reset delay mismatch in PFD is comparable to the noise oor due to CP gain mismatch (Fig. 7). From (25) and (26), and Fig. 13, it can be derived that reset delay mismatch noise occurs for the following cases: 1) for FB late: 2) for FB early: ; .

Table VII lists the cases of the reset delay mismatch noise and the probability of their occurrence for those cases. Some of the design strategies which can help in eliminating the noise due to reset delay mismatch are stated as follows.

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Fig. 13.

Reset delay mismatch. (a) Early FB pulse. (b) Late FB pulse.

Fig. 14.

DSM noise due to PFD reset delay mismatch referred to the input of PFD ( = 0:10

2T

).

1) Prescalar output pulsewidth less than the minimum on-time of the CP . 2) Prescalar output pulsewidth larger than the maximum difference between REF and FB edges plus reset delay( ). 3) DFFs with reset propagation delay independent of the . clock level 4) DFF clock level periodically alternates when the reset pulse occurs. Option 1) presents the systematically best solution. However, extremely short prescalar output pulses may be required for

small . Option (2) comes at a price of higher thermal and icker noise in the output of the CP. Option (3) involves the design of custom DFFs. Digital design techniques can easily accomplish option (4) and will convert the noise mechanism into a reference spur at the PLL output (which can be suppressed via the loop lter impedance roll-off). E. Prescalar Noise Modulus-dependent delay mismatches in the feedback divider also contribute to PLL noise oor [27]. Considering a

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Fig. 15. (a) Periodic CP pulses with constant on-time  (dened as the time taken by the CP to rise from 0:50 I current to reach the steady state CP current I and then fall to 0:50 I ) and equal rise time and fall time ( ). (b) Fourier Spectra of CP pulses shown in (a).

simple case of dual-modulus divider for modeling purposes, the modied phase error can be modeled by (30) is the dual-modulus delay mismatch. If the where number of moduli in the prescalar is more than 2, then, as shown in Fig. 1, the error term is going to be dependent on the . Since, the distribution of the output distribution of of DSM is Gaussian, the distribution of is also Gaussian. The resulting charge delivered to the loop lter is given by

and the modied CP current is

during the time period . Intuitively this leads to a reduction in the output noise power. For the CP output pulsewidth to be directly proportional to the input phase difference, the bandwidth of the CP is large compared to the sampling frequency. Consequently, the CP broadband noise is under-sampled. Typis well below the ically, the icker noise corner frequency sampling frequency; therefore, icker noise is oversampled. The of Frac-N CP time varying duty cycle complicates the thermal and icker noise analysis of the CP. To simplify our understanding, we rst consider the case where the CP operates with constant duty cycle such as an Integer-N PLL in lock. Then we will extend the analysis to Frac-N CP operating with a time varying duty cycle. To derive the output spectrum of sampled broadband noise of the CP, we evaluate it using Fourier series. Assuming equal , the CP pulses are approximately rise time and fall times in Fig. 15(a)]. The trapezoids Fourier trapezoidal in nature [ series is given by

Along the lines of phase noise due to PFD reset delay mismatch (29), the two-sided phase noise due to modulus-dependent delay mismatch, input referred to the PFD, is given by rad Hz where is the rms delay mismatch between the prescalar states used. F. PFD Jitter The two-sided phase noise due to the white noise rms jitter present in the digital logic of PFD, input referred to the PFD, has been reported elsewhere [13], [14], [25], and is repeated here for completeness rad Hz (31)

for The total power in the Fourier series is given by [26]

(32) where . Aliasing is represented by the sum term in (32). Hence, the output PSD of the sampled broadband noise is scaled by , the area under the power spectrum of the sinc pulse (33) Flicker noise is usually oversampled by the reference clock of the PLL. In the frequency domain, this oversampling corresponds to a convolution of the PSD of the icker noise with a spectrum of periodic pulses of unity height. Hence, the omission of the aliasing sum-term in (32). The dc term of the Fourier series in (32) determines the total resulting icker noise power in the baseband (34)

is the rms timing jitter in PFD. As a result, PFD where , divider delay mismatch jitter noise input referred noise and PFD reset delay jitter will be indistinguishable in the Frac-N output spectrum. IV. NOISE MODEL OF CP WITH TIME-VARYING DUTY CYCLE A. CP Thermal and Flicker Noise With Constant Duty-Cycle A CP has both broadband noise and icker noise. The CP of a Frac-N is on for only a fraction of time,

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Let and represent the probability that the on time and , of the Up and Dn CP is respectively, where if if if if The Up CP noise gets modied by the time-varying duty cycle and is given by

Fig. 16. Comparison of CP thermal and icker noise PSD when operating under different conditions.

Assuming a icker noise frequency exponent AF, the noise PSD for the two cases shown in Fig. 16 can be expressed as (35)

(38)

(39) Since (36) From (35) and (36), we obtain the icker noise corner frequency of CP current pulses operating with duty cycle as (37) The above analysis of CP of Integer-N PLL, leads to the following results: 1) The thermal noise PSD scales by the duty cycle (33). 2) The icker noise PSD scales by the square of the duty cycle (34). 3) The icker noise corner frequency scales by the duty cycle ]. [(37) for Note that (35)(37) apply to the Up and Dn pumps indiviually , and AF. with their respective values of B. Time-Varying Duty Cycle The above discussion assumes that the Up (or Dn) CPs are operating with a xed duty cycle. On the contrary, the Up and Dn CPs of Frac-N operate with a time-varying nonperiodic duty cycle given by In locked state is Gaussian, hence (38) and (39) can be expressed as

. Thus, along the lines of Up CP noise, similar expression for Dn CP noise under time-varying duty cycle conditions can be written. Assuming that the noise in the Up and the Dn CPs is uncorrelated, the total CP noise is given by

if if if if

Thus, reduced variance of not only minimizes the noise due to CP/PFD nonlinearities but also minimizes the CP thermal noise, icker noise and icker noise corner frequency. V. NOISE MODEL OF VCO The modied Leeson equation, derived in [15], [16], [18] expresses the output phase noise PSD of the VCO. This VCO noise

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TABLE VIII PARAMETERS OF FRAC-N NOISE MODEL

where , and VII. SIMULATION A. Simulation Methodology of DSM Noise

Fig. 17. Third-order passive loop lter.

is high pass ltered by the PLL, and appears in the output of the Frac-N as

rad Hz where is device two-sided noise factor of VCO operating at is Boltzmanns constant, is temperature, power level is average power dissipated in the resistive part of the tank, is loaded Q of VCO, is frequency offset from carrier, is oscillator carrier frequency, and is the icker noise corner frequency. VI. NOISE MODEL OF THE LOOP FILTER For the sake of simplicity and completeness a third-order passive loop lter of Fig. 17, designed as in [24], is considered for this noise analysis. The two-sided phase noise PSD in the output of Frac-N due to thermal noise of the resistors, is given by

A common methodology is used for obtaining the PSD due to CP gain mismatch, CP dynamic mismatch and PFD reset delay mismatch. The difference equation of the chosen topology of delta sigma is used for simulating the DSM in the time domain, , where F and Q are integers. The with the input being decides the instantaneous value of the output of DSM . This divider value is then used to multimodulus divider compute the instantaneous timing error between the reference clock edge and the output of prescalar ( in (8)). The simulation of (8) is done in discrete time domain under open-loop conditions assuming the Frac-N PLL is in the locked state. The total DSM noise, including the effects discussed above is obtained by distorting the ideal CP current sequence in the time domain. Next, the PSD of CP current is multiplied by the square magnitude of the transfer function from the CP output to the output of in the Frac-N to obtain the total DSM noise PSD output of Frac-N. B. Frac-N Model Parameters The model was used to analyze the noise performance of the Frac-N described in [1] and [2] using the VCO of [3]. The noise performance was simulated in MATLAB for the parameters of the various macros of Frac-N listed in Table VIII. Reference [1] states that the on-time fraction of the CP due to delay is less than 10% of the reference clock. Keeping this in mind, we chose . In the minimum turn-on time of the CP Table VIII the items marked are estimated parameters of [1]. C. Simulation Results As shown in Fig. 18, the third-order passive loop lter of Fig. 17 was designed to produce the same unity gain loop bandwidth of 35 kHz and phase margin (PM) of 57 as the

rad Hz

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TABLE IX RMS PHASE ERROR DUE TO EACH MACRO OF FRAC-N USING MBSL-I DSM

Fig. 19. Noise spectrum of Frac-N macros at the output of Frac-N using MBSL-I DSM. Fig. 18. Comparison of dual-path active third-order loop lter of [1] and third-order passive loop lter of Fig. 17. (a) Open-loop magnitude response. (b) Open-loop phase response. (c) Closed-loop response.

dual-path active loop lter used in [1]. As shown in Table VIII, the resistor values of the passive lter were chosen to be comparable to the resistor values of the dual-path loop lter. This was done to match the thermal noise of resistors in both lters. The dual-path loop lter implements poles at dc, 209.5 and 207.2 kHz and a zero at 9.2 kHz. On the contrary, the passive and kHz by implementing lter achieves the PM poles at dc, 124 kHz, and 2.85 MHz and a zero at 10.4 kHz. The simulated icker noise corner frequency of Frac-N Dn CP was approximately 15.6 kHz (Fig. 19). Welchs method of power spectrum estimation was used to compute the PSD of individual CP/PFD and DSM noise mechanisms. In the frequency range from 100 kHz to 1 MHz our simulated phase noise matched quite well with the measured phase noise of [1]. MHz the dual-path active As shown in Fig. 18(c), for loop lter offers more than 10 dB higher attenuation than the passive lter. This accounts for reduced hump in the measured MHz to MHz in [1]. The phase noise from Frac-N model predicts a lower rms phase error. This is probably due to the following reasons: 1) High jitter and ringing at the prescalar input [4] resulting in phase noise in [1] to be 20 dB higher at 10 kHz frequency offset than the simulated phase noise. 2) The dual-path loop lter, consisting of an active lter and a summer, linearization circuit at the input of VCO, and a buffer between the pre-scalar and the VCO are present in [1].

3) The divider in our model had 7 moduli in contrast to the phase-switching topology of the divider with 16 moduli being used in [1]. 4) The MATLAB simulations were performed without taking into account the noise coupling through the substrate and the power supply lines. These noise mechanisms not present in our model, likely contribute to the additional rms phase error. Further, in [1], the function of DSM is emulated by HP80000 data generator the output of which is fed to the prescalar. The authors of [1] in their subsequent publication [4] have outlined the following reasons for kHz. the higher measured phase noise at 1) The high jitter of the data generator output signals, which is 10 ps typical and ps maximal [4], 2) The terminations of the connections between the on chip prescalar and the data generator were not well dened. This resulted in reections and hence, lot of ringing on the prescalar input [4]. The impact of the noise on the prescalar input is partially substantiated in Fig. 19 which shows that the prescalar delay miswas the dominant contributor match noise to the Frac-N phase noise. Table IX presents the rms phase error in the output of Frac-N due to each macro of the Frac-N. Table X summarizes the simulated results of the Frac-N in comparison to the previously published results. Table XI compares the performance of Frac-N for different topologies of DSM with the specications listed in Table II. Clearly, amongst the third-order DSMs, MBSL-I and MBSL-II demonstrated the lowest DSM phase noise due to the nonlinearities of CP/PFD. This as earlier stated, is because MBSL-I and MBSL-II have lower variance of intrinsic (Table II), reduced

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TABLE X COMPARISON OF PERFORMANCE WITH PREVIOUS WORK

TABLE XI DSM RMS PHASE ERROR AND Dn CP FLICKER NOISE CORNER FREQUENCY OF FRAC-N WITH DIFFERENT DSMS

quantization noise around and achieve noise shaping using the least number of dividers compared to other third-order DSM topologies like MBSL-I, MASH-12, MASH-21 and MASH111. Further, the simulation results agree well with analytically derived results that an increase in the order of DSM increases DSM noise due to nonlinearities of CP/PFD. Also, amongst the third-order DSMs, MBSL-I and MBSL-II offer the lowest icker noise corner frequency. This is because as compared to . other third-order DSMs, MBSL-I, and MBSL-II have lower

REFERENCES

VIII. CONCLUSION A combined time- and frequency-domain model of a delta sigma controlled Frac-N was developed. The noise models of ve building blocks, namely the DSM, the PFD, the CP, the feedback divider, the low pass lter, and the VCO were analyzed. The DSM noise model captured the noise due to nonlinearities of CP gain mismatch, CP dynamic mismatch and PFD reset delay mismatch. It was shown that the inequality of the fall time constant and rise time constant is the cause of the CP dynamic mismatch. The CP model also takes into account the reduction of CP icker noise, thermal noise and the icker noise corner frequency due to the varying duty-cycle of the CP. It was found that the topology of DSM with the least duty cycle variance of the Frac-N CP, is the most robust to CP nonlinearities and offers the least thermal, and icker noise of the CP. The derivation of DSM noise due to reset delay mismatch in the PFD is also presented. The above-mentioned CP and PFD nonlinearities were simulated and analyzed for different topologies and orders of DSMs used in Frac-Ns. Simple, easy to use formulae were presented to predict the noise in the output of Frac-N due to CP gain mismatch and PFD reset delay mismatch. The simulated results were compared with the previously published results on Frac-N.

ACKNOWLEDGMENT The authors would like to thank Dr. E. Hegazi, Ericsson, Research Triangle Park, NC, for useful inputs on Welchs method of power-spectrum analysis.

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[20] E. Hegazi and A. A. Abidi, A 17-mW transmitter and frequency synthesizer for 900-MHz GSM fully integrated in 0.35-/spl-m CMOS, IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 782792, May 2003. [21] B. Miller and B. Conley, A multiple modulator fractional divider, in Proc. 44th Ann. Symp. Freq. Contr., May 1990, pp. 559568. [22] B. Miller and R. J. Conley, A multiple modulator fractional divider, IEEE Trans. Instrum. Meas., vol. 40, no. 3, pp. 578583, Jun. 1991. [23] M. H. Perrott, T. L. Tewksbury III, and C. G. Sodini, A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation, IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 20482060, Dec. 1997. [24] D. Rosemarin. (1999, Feb.) Accurately compute PLL charge-pump lter parameters. Microwaves RF J. [Online], pp. 8994. Available: www.mwrf.com [25] D. Banerjee. (1998) PLL performance, simulation, and design. National Semiconductor [Online]. Available: www.national.com [26] F. G. Stremler, Introduction to Communication Systems, 3rd ed. Reading, MA: Addison Wesley, 1992. [27] S. Pamarti, L. Jansson, and I. Galton, A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation, IEEE J. Solid-State Circuits, pp. 4962, Jan. 2004.

Himanshu Arora (S04) received the B.Tech. degree in electrical and electronics engineering and the M.S. degree in electrical and computer engineering from the Regional Engineering College, Warangal, India, and the Duke University, Durham, NC, in 1996, and 2001, respectively. He is working toward the Ph.D. degree at the same university. From 1996 to 1998, he was with the Power Electronics and Drives Division of Asea Brown Boveri, Bangalore, India. In 1998, he was an R&D Engineer in the Real Time Embedded Systems Group, CMC, Hyderabad, India. During the summer of 2002, he interned with Ericsson Inc., Research Triangle Park, NC. His current research interests include mixed signal and RF integrated circuit design.

James C. Morizio (S76M90) was born in Endicott, NY, in 1957. He received the B.S.E.E., the M.S.E.E., and the Ph.D. degrees from Virginia Polytechnic Institute, Blacksburg, VA, the University of Colorado, Boulder, CO, and Duke University, Durham, NC, in 1982, 1984, and 1995, respectively. His doctoral work involved the research of adaptive-gain sigmadelta data converters. He was employed by IBM Corporations PC Division and Networking Hardware Division, Boca Raton, FL, and Research Triangle Park, NC, from 1984 to 1995, where he worked on numerous mixed-signal application-specic integrated circuits (ASICs) including a liquid crystal at panel interface device, an audio CVSD codec and 4/16 Mb/s token ring AFE transceiver. From 1995 to 2001, he was employed by Mitsubishi Electronics Corporation, Durham, NC, as a Principal Engineer and Group Leader of the Mixed Signal VLSI Design Group where he designed audio and broad-band sigmadelta codecs and phase-locked loop CMOS circuits and systems. In 2001, he became the Founder and President of Triangle BioSystems, Inc., Durham, NC, where he designs and manages several low noise and low power integrated biomedical instrumentation areas of neural prosthetics and broadband ultrasound. He is the author and co-author of numerous patents and publications in the area of integrated analog circuit and system design. He is also a Research Assistant Professor at Duke University, where his research interests include mixed-signal ASIC design for areas of liquid crystal on silicon and biomedical instrumentation circuits.

Nikolaus Klemmer (M92SM04) received the Dipl.Phys. degree in physics from the Technical University of Munich, Munich, Germany in 1992. From 1992 to 1995 he was with Sican Inc., Hannover, Germany, where he worked on planar inductor modeling and synthesis for monolithic and multichip module applications. In 1996, he joined Ericsson Inc., Research Triangle Park, NC, where he was involved in the design of several generations of mobile telephony radio transceivers. In 2000, he was appointed Manager of the RF and Mixed Signal Design Group. Since 2004, he has been with Analog Devices Inc., as a Senior Integrated Circuit Designer, where he is working on the development of wireless LAN and high-performance clocking products. His general research interest lies in analog circuit design and modeling for wireless transceivers, frequency synthesizers, and data converters. He has published 10 papers and has been granted 15 patents.

Patrick D. Wolf was born in Altoona, PA, in 1956. He received the B.S. degree in electrical engineering and the M.S. degree in bioengineering from the Pennsylvania State University, University Park, and the Ph.D. degree from Duke University, Durham, NC, in 1978, 1986, and 1992, respectively. In 1992, he joined the faculty in Biomedical Engineering at Duke university where he is currently pursuing his research interests in instrumentation, cardiac arrhythmias and the brainmachine interface.