A novel low-power area efficient ERROR-TOLERRANT ADDER II and its application in digital signal processing

Vishnu sai.D M.Tech(VLSI), vishnudivvela@yahoo.com ABSTRACT In latest technology advances, the error in the circuit are inevitable. By adopting new concepts in vlsi. we can achieve the low-power and high speed circuits. In this paper we adopting a new novel approach for ETAII. By this approach we can achieve the accuracy, low-power and speed. When compared to the ETA. We have used the cadence virtuoso for simulation in TSMC 180nm technology. Prof.R.Sakthivel. Assistant Prof (Senior), rsakthivel@vit.ac.in

Introducation In latest digital vlsi design the circuit/system should always provide the accurate results. But nowdays such a perfect operations are rare in analog circuits. Which generates good enough results rather than accurate results[1]. The output of many digital system may already contain some error. Many applications such as communications system. Before converting the analog to digital signal it must be sampled at certain frequency. Then only digital data should be transmitted in noisy channel. In this process many error make occur to reduce the error some rules like size of the transistor, noise are explained in todays digital ic design[2]. For the basic principles of digital vlsi concepts. Some novel concepts and design techniques have been proposed. The concepts of error tolerance(ET)[3]-[10] and the PCMOS technology[11]-[13] are two of them according to the definition of the circuit is error tolerance if 1)it contain defect that both internal and external error and 2)due to this error the circuit may not get the acceptable results[3].so however to solve the error tolerant circuit [3]-[10] was foretold in the 2003 international Technology roadmap for semiconductors(ITRS)[2]. To solve the error tolerant problem some of the adders/multipliers have been proposed[14][15] but the results was not good the the flagged prefixed adder[14] performs better than the previous one in both area 2% and speed 1.3%. as per the low-error area-efficient fixed widthmultiplier [15]. It has good results in area 44.67% and average error reaching 12.4%. The rest of the paper is organized as follows. Section II proposes the addition arithmetic as well as the structure of the error tolerant adderII(ETAII). In section III the detailed design of the ETAII is explained. In the section IV we explained the results and the conclusion. 2)ERROR-TOLERANT ADDER Before studying the ETAII the definitions of some commonly used terminologies shown in this paper given below. Overall error(OE):OE=Rc-Re. where Rc is the correct result and Re is obtained by the adder.

Accuracy(ACC): in the scenario of the error-tolerant design . the accuracy of an adder is used to indicate how correct the output of an adder is for particular input. It is defined as:ACC=(1(OE/Rc))*100. its value ranges for 0% to 100%. Minimum acceptable accuracy(MAA):Although some error are allowed to exist at the output of an ETA, the accuracy of an acceptable output should be high enough (higher than a thresholdvalue) to meet the requirement of the whole system. Minimum acceptable accuracy is just that threshold value. The result obtained whose accuracy is higher than the minimum acceptable accuracy is called acceptable result. Acceptance probability (AP): Acceptance probability is the probability that the accuracy of an adder is higher than the minimum acceptable accuracy. It can be expressed asAP=p(ACC>MAA), with its value ranging from 0 to 1.

Need of the ERROR-TOLERRANT ADDERII(ETAII) In the latest technology the increasing huge of the data sets and need the instant response require the adder it will large and fast. The are many traditional adders like carry-ripple adder. Such as caary-skip adder[16],carry select adder[17],carry-look ahead adder[18]and error tolerant adder[20], have been developed. Also they many low power techniques have been proposed[19]. In every low power design circuit there must be trade of between power and speed.

Proposed addition arithmetic In the a normal adder the carry will propagation along the critical path by this power will and delay will increase if the carry propagation will reduce then the power and delay will be reduced. in the paper we proposed for the first time an innovative and novel addition arithmetic that can attain great saving in speed, power and delay. We first split the operands in two parts a)accurate part b)inaccurate part the split of operands need not be equal it may be unequal

accurate part in the accurate part we can see only the higher order bits.in this part we only use the normal addition rules. Inaccurate part: In the inaccurate part we can see only the lower order bits.in this part we apply the some addition rules 1)if both input operands are zero then the result will be the zero. 2)if both inputs operands are one and zero then the result will be one. 3)if both inputs are operands are zero and one then the result will be one. 4)if the inputs are operands are one then the results will be one and remains same for reaming all. Let us take an example to understand the above rules.

Example (MSB)

Accurate part

starting point

inaccurate part(LSB)

0 1 1

1 1 0 1 1 1

1 0 1

0 1 1

0 0 1

1 1 0

0 1 1

1 0 1

0 0 0

1 0 1

1 1 1

1 0 1

0 1 1

0 0 1

0 0 1

Fig .1 proposed addition arthmetic From the above example we can explain the above steps. we have taken the two operands A=0110010101110001(25969) B=1001011000101001(38441).and this operands are divided into two parts.it may divided into equal or unequal.in this example we divided the operands in to two equal parts of the size 8bits each In the accurate part the addition will start from the starting point to MSB side in the accurate part we can use the normal addition like CSA etc. In the inaccurate part where the addition part will start from starting point to LSB we need to apply the above rules.(we can see the where the first bit was both inputs are zero).

The example given in above fig 1. the 1111101101111111(64383).but the actual result was 1111101110011010(64410)

final

result

was

Control block

Conversational adder

Modified or block

Fig 2. Hardware implementation of the proposed ETAII 3)Hardware implementation Strategy of Dividing the adder The first step in algorithm is to divided the operands into two part. The accurate and inaccurate part. the division of operands is need to be equal but the accuracy, speed and power are depend on the separation of operands. For example we can take the calculation of delay as Td=MAX(Th,Tl).where Th is delay of the accurate part and Tl is the delay of the inaccurate part.

The block diagram of the hardware implementation of ETAII that adopts the our proposed addition arithmetic is provided above . this structure consists of two parts an accurate part and inaccurate part. in accurate part we can use the any normal adder structure like RCA,CSK,CSL and CLA. the carry is connected to ground. The in accurate part consists of two blocks. The control block is

used to generate the control signal. The working of modified xor will explained with an of 32-bit adder example in the next section. Design of 32-bit error tolerant adder Design of the accurate part In the accurate part it consists of 12 bits. The overall delay is determined by the inaccurate part and so the accurate part need not be a fast adder. The ripple carry adder which is most power saving conventional adder has been chosen for the accurate part of the circuit. Design of the inaccurate part The inaccurate part is the most important part in the proposed ETAII as it says that the power,delay,accuracy will be reduced in the part only. In this inaccurate they are two block first one control block and next one is the carry free addition block(modified or block) in this consist of 20 modified or gates and each gate will give sum bit. The block diagram and schematic implementation of modified or gate is given above diagram--------- in the modified or gate three transistors are used M1,M2,M3 and CTL. Where CTL is control signal where it depends on the inputs bits. When CTL=0 M1 and M2 will on.M3 will of mode then normal or operation will done. When CTL=1 M1 and M2 will in off.M3 will in on mode then vdd is connected to sum.

Vdd Vdd

CTL

M1 M3

A B

Modified xor logic

SUM

M2 GND

(a)

CTL19 A19 B19 A18

CTL18

CTL1 A1 B1 A0 B0

CTL0

B18

Modified xor

Modified xor

Modified xor

Modified xor

S19

S18

S1

S0

(b) Fig .3. modified or logic (a) schematic diagram of a modified or gate and (b) overall architecture

5 blocks 5 blocks

II

(a) Ai Bi Ai Bi

CTLi+1 CTLi+1 CTLi+4

CTLi CSGC TYPE I

CTLi CSGC TYPE II

(b) Fig .4 control block (a)overall architecture (b)schematic implementations of CSGC types

4)Results

Type of the adder Modified xor gate Modified or gate

Power (mW) 0.6327 0.4986

Dealy(nS) 4.29 4.20

PDP 2.17p 2.09p

No of transistor count 1006 606

Layout of the modified or gate