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Torus-pyramid-NOC: Regular Topology of Grid-Pyramid For Network-On-Chip

Reza Kourdy Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran Mohammad Reza Nouri rad Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran

Abstract The choice of network topology is important in designing an Efficient NoC. Different NoC topologies can dramatically affect the network characteristics, such as fault-tolerant, wire length, hop count and communication load. These characteristics in turn determine the efficiency of NoC architectures. The Torus-pyramid-NOC is a generalized pyramid network based on a general Grid structure. Such pyramid networks form a wide class of interconnection networks that possess rich topological properties. In this paper, we simulate a general class of pyramid networks that are based on grid connections between the nodes in each level and is suitable for multiprocessor networks such as NOCs. Index Terms RTCC-Pyramid, Network-on-Chip (NoC), Recursive Transpose-Connected Cycles (RTCC), System-on-Chip (SoC), WK-Recursive.

1 INTRODUCTION

NoC is an efficient on-chip communication architecture for SoC architectures. It enables integration of a large number of computational and storage blocks on a single chip. NoCs have tackled many disadvantages of the SoCs and are structured, reusable, scalable, and have high performance [1] [2]. NoCs are a new paradigm for scalable communication among the several cores located into a single chip [3]. The basic idea is borrowed from the off-chip network domain, and consists of a point-to-point switch based network with packet-switched communication that forwards packets to destinations through a certain number of intermediate hops. As aforementioned, NoCs have restrictions in terms of power consumption and cost (mainly silicon area and design cost), since total system cost and power consumption should not be seriously affected by the employed NoC. The common trend in interconnect architecture research is to improve network performance at the cost of increasing physical implementation complexity. For instance in [4] the mesh topology is modified to increase its performance by halving the number of switches, but doubling the switch radix. Hence, switch complexity is doubled. Another example is shown in [5], where two HTrees are combined to build a torus-like topology with a reduced network diameter, thus decreasing packet latency. For this, network interfaces are modified to allow packet switching, also increasing the number of network links and switches.
Fig.1. Generic NoC Architecture (a 33 MESH)

2 NOC TOPOLOGIES
Lots of topologies have been proposed for NoCs so far,

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such as Mesh [6], Torus [7], Star [8], Octagon [9], SPIN [10]. Among these topologies, mesh topology has gained more consideration by designers due to its simplicity (cf. Figure 1). The main problem with the mesh topology is its long diameter that has negative effect on communication latency. Torus topology was proposed to reduce the latency of mesh and keep its simplicity (cf. Figure 2). The only difference between torus and mesh topology is that the switches on the edges are connected to the switches on the opposite edges through wrap-around channels. Every switch has five active ports: one is connected to the local resource while the others are connected to the closest neighboring switches. Although the torus architecture reduces the network diameter, the long wrap-around connections may result in excessive delay. However, this problem can be avoided by folding the torus [11]. Due to importance of these two topologies, i.e., mesh and torus, we compare the performance and power consumption of these NoC topologies under different routing algorithms.

3.2. Torus network A The a b torus network, denoted as Ta,b, consists of a set of nodes V(Ta,b) = {(x, y) | 1 x a, 1 y b}, where each node (x1, y1) is connected to its four neighboring nodes (x1 1 mod a, y1) and (x1, y1 1 mod b). See Fig. 3(b).

Fig. 2: NOC- Torus topology

3.1. grid-pyramid network The grid-pyramid networks were first introduced in [12] as a generalized pyramid topology. Various topological properties of these networks were studied in [12]. We selected these classes of networks to show how efficient they can be placed on chips.

Fig.3. The topologies of (a)M4,4 (b)T4,4.

3 DEFINITIONS AND PRELIMINARIES

3.1. Mesh network An a b mesh network, Ma,b, is a set of nodes V(Ma,b) = {(x, y) | 1 x a, 1 y b), where nodes (x1,y1) and (x2, y2) are connected by an edge iff |x1 x2| + |y1 y2| = 1[1]. See Fig. 3(a).

3.3. grid-pyramid A A grid-pyramid of n levels, denoted by PG,n, consists of a set of nodes V(PG,n) = {(k, x, y) |0 k n, 1x, y2k}. A node (k, x, y) V (PG,n) is said to be node at level k. All the nodes in level k form a 2k2k grid network G which can be one of the grid-based networks: mesh, torus, hypermesh or WK-recursive mesh, i.e. (G M, T, HM, WK); The resulted pyramid can then be then denoted as Pm,n , PT,n, PHM,n, and PWK,n, respectively. Fig. 4 shows all grid

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Fig.4. The topologies of (a)PM,2 (b)PT,2 (c)PWK,2 (d)PHM,4

pyramid networks.

4 RELATED WORK
Pande and Grecu in [13] focused on performance evaluation of a set of recently proposed NoC architectures with realistic traffic models, using a deterministic routing without addressing the effect of different routing algorithms.

5. SIMULATION METHODOLOGY
In this section, simulation of RTCC-Pyramid on-chip interconnects is done by using a simulator developed in [14]. This discrete event driven simulator is based on ns2 [15] that provides many facilities to describe network topology, transmission protocols, routing algorithms, and traffics generation. The main objective of using ns2 is to rapidly explore and evaluate the performance metrics as well as the energy consumption of on-chip interconnects.

node, in which PE (Processing Element) and router are the main components. The PE is a module that injects/ejects the generated/receiving packets based on a traffic model like uniform, hot spot, etc. Routers receive packets on their input channels and after routing a packet based on the routing algorithm and destination address, the packet is sent to the selected output channel. When a specific topology like mesh or WK-recursive is supposed to be modeled by such components, a top-level wrapper module is implemented that connects several nodes of this type to each other based on the structure of the specified topology. Ns-2 [16] is a discrete event network simulator designed for simulation of ordinary networks of computers. As many models of network components are provided, the user can simulate at a high abstraction level. Yet, it is possible to implement new components in the network model. Ns-2 has support for local area networks, mobile networks and even satellite networks. Two computer languages are used in ns-2, namely C++ and OTcl.

7.1 SIMULATION DETAILS The top most shared component in simulation is the NoC

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8. SIMULATION RESULTS
In this section, we present the Simulation of NoC with different levels with the topology pyramid-noc-RTCC. We survey the ability and flexibility of ns2 in simulations. Figures 5 to 14, show different views of simulations

8.1. Pyramid-noc-torus with 3 levels Simulation of PYRAMID-NOC- TORUS with 3 levels:

Fig.7. 3rd view of pyramid-NOC-torus

8.2. Pyramid-noc-torus with 4 levels

Simulation of PYRAMID-NOC- TORUS with 4 levels:

Fig.5. 1st view of pyramid-NOC-torus

Fig.8. 1st view of pyramid-NOC-torus (4 Levels)

Fig.6. 2nd view of pyramid-NOC-torus

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Fig.9. 2nd view of pyramid-NOC-torus (4 Levels) Fig.11. 4rd view of pyramid-NOC-torus (4 Levels)

Fig.10. 3rd view of pyramid-NOC-torus (4 Levels)

Fig.12. 5rd view of pyramid-NOC-torus (4 Levels)

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Fig.13. 1st view of pyramid-NOC-torus (5 Levels)

Fig.14. 2nd view of pyramid-NOC-torus (5 Levels)

8.3. Pyramid-noc-torus with 5 levels

Simulation of PYRAMID-NOC- TORUS with 5 levels:

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REFERENCES
[1] L. Benini and G. de Micheli, Networks-on-Chip: A new Paradigm for System on Chip Design, Design Automation and Test in Europe, IEEE computer, vol. 35, no. 1, pp. 70-78, January 2002. [2] F. Moraes, N. Calazans, A. Mello, L. Moller, L. Ost, HERMES: an Infrastructure for Low Area Overhead Packet-Switching Networks on Chip, Integration,

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Reza Kourdy received his B.Sc. Degree in Computer Engineering and his M.Sc. Degree in Computer Architecture both from Azad University of Arak, Iran, in 2002 and 2007, respectively. His research interests include Network-On-Chip Architecture and Faulttolerance.
Mohammad Reza Nouri Rad received his B.Sc. Degree in Computer Engineering Software from Azad University of Najafabad, Iran, in 2001, and his M.Sc. Degree in Computer Software from Azad University of Arak, Iran, in 2010. His research interests include NetworkOn-Chip Architecture and Network Security. He is Program Committee of following conferences : WICT 2011 CSNT 2011 CICN 2011 SocProS 2011 CSNT 2012 CICN 2012 BIC-TA 2012