Chapter 5: The Processor: Datapath and Control

I. MIPS Implementation
All instructions have the same first 2 steps: 1. Send the program counter (PC) to the memory that contains the code and fetch the instruction from that memory. 2. Read registers, using fields of the instruction to select the registers to read. 3. The 3rd step (using ALU) depend on the instruction class (except jump): a. The memory-reference instructions: use for address calculation b. The arithmetic-logical instructions: use for operation execution c. Branches: use for comparison 4. The actions required to complete various instruction classes differ: a. The memory-reference instruction: access the memory either to write data (store) or read data (load) b. The arithmetic-logical instruction: write the data from the ALU back into a register. c. The branch instruction: change the next instruction address based on the comparison

II. Building Data Path 5.

Datapath element: A functional unit used to operate on or hold data within a processor. In the MIPS the datapath elements include the instruction and data memories, the register file, the arithmetic logic unit (ALU), and adders.2 1. Elements that operate on data values (combinational): o ALU (add, subtract, multiply, divide, tt c control instructions) o NOT gate, AND gate, OR gate, NOR gate, NAND gate, XOR gate, XNOR gate o Decoder, Encoder, Multiplexer, De-multiplexer, Adder, Comparator - Outputs always depend only on the current inputs (has no internal storage ) - Given the same input / a set of inputs always produces the same output 2. Elements that contain state (sequential): example Data Memories, Register - It has some internal storage. - A state element can be read at any time - Register: o Uses a clock signal to determine when to update the stored value o Edge-triggered: update when Clock changes from 0 to 1 - Register with Control: o Only updates on clock edge when write control input is 1 o Used when stored value is required later

A Simple Data path

- Load the address of the next instruction: PC + 4 - Branch instruction: Load the st address of the 1 instruction in the target Label

- Hold the address of the current instruction - Transfer it to the Instruction Memory - PC load the next instruction address (+4 or branch)

- Receive the address from PC

- Find out which registers and instruction are used

- Hold the address of registers, data of registers - It will read the data of registers from the Data Memory (load instructions) - It transfer the address of registers ALU Data Memory to read/write the data value

- Hold the data value of the registers - The value can be read / write - Usually use in load / save instructions

IV. Simple SIngle Implementation

A Full Data path with control

A data path for R-type instruction (Arithmetic: +, -, *, /): usually 4 cycles (uses 4 units: PC, Instruction Memory, Register, ALU)
- Control transfer the ALUOp to the ALU control to determine the operation - PC load the instruction address - Transfer it to Instruction Memory - PC += 4

- Read the registers address and data from register - Transfer the data to ALU and compute the result

- Transfer the data to the destination register

Step-by-step of instruction: add $t1, $t2, $t3 1. The instruction is fetched, and the PC is incremented. 2. Two registers, $t2 and $t3, are read from the register file. The main control unit computes the setting of the control lines during this step also 3. The ALU operates on the data read from the register file, using the function code Sto generate the ALU function. 4. The result from the ALU is written into the register file using bits 15:11 of the instruction to select the destination register ($t1).

A data path for I-type instruction (lw / sw): 5 cycles (PC, Instruction Memory, Register, ALU, Data Memory) except sw (4 cycles)
- Control transfer the ALUOp to the ALU control to determine the operation - Read the registers address and address contains in the register - Transfer the data to ALU and compute the result - lw $t1,offset($t2) $t1 = write register $t2 = read register1 - sw $t1,offset($t2) $t1 = read register1 $t2 = read register2 for address

Step-by-step of instruction: lw $t1,offset($t2) 1. An instruction is fetched from the instruction memory, and the PC is incremented. 2. A register ($t2) value is read from the register file. 3. The ALU computes the sum of the value read from the register file and the sign-extended, lower 16 bits of the instruction (offset). 4. The sum from the ALU is used as the address for the data memory. 5. The data from the memory unit is written into the register file; the registerdestination is given by bits 20:16 of the instruction ($t1) A data path for I-type instruction (branch): 4 cycles (PC, Instruction Memory, Register, ALU)

Step-by-step of instruction: beq $t1,$t2,offset 1. An instruction is fetched from the instruction memory, and the PC is incremented. 2. Two registers, $t1 and $t2, are read from the register file. 3. The ALU performs a subtract on the data values read from the register file. The value of PC + 4 is added to the sign-extended, lower 16 bits of the instruction (offset) shifted left by two; the result is the branch target address. 4. The Zero result from the ALU is used to decide which adder result to store into the PC. A data path for Jump instruction: 2 cycles (PC, Instruction Memory)

How to Use Pathsim4