VLSI CMOS Fabrication Modules Combine with Power Device Methods to Produce 40mQ & 65mQ, 7V Logic Level

P-Power FETs
Taylor Efland, Dale Skelton, Steve Keller, Kathy Frank, Quang Mai,
Computer Peripheral and Custom Power, HFAB Texas Instruments Incorporated Dallas, Texas, USA
Abstract Layout and Process Definition

In this paper, results are discussed from work completed on logic level low voltage power PMOS switches. The devices were fabricated using base line 7V rated PMOS from an existing scaleable technology and applying power device design techniques to the structure. The goals were to demonstrate area efficient high current low on resistance switches with fast switching and robust performance in an SO8 form factor. Device performance achieved was %,,=65mQ @ V,=-S.OV, L=-6A with UIS switching up to 40A at Vdd=-6V;this device is shown along side an 80% shrunk version in figure 1. A 4 m @ V,=-S.OV, hs=-12A O R version was demonstrated and is also reported in this work. Competitive RJpwas characterized for both N and P channel 7V rated devices.
Introduction

Layout methods conforming to packaging and power devices contributed to a large amount of the success of the device. Generally in CMOS logic devices layout is generated with respect to packing density number one, contacts and metal lines are minimized, the back-gate connection is periodic and location is dictated by latch-up conditions. This is sufficient for logic operation where a voltage switch is what is needed. On the other hand, power switches are involved with moving large DC and transient currents in both forward and reverse directions. Additionally the conduction path is different depending on bias conditions. Because of these factors geometric layout and interconnect to the various regions becomes extremely important in order to assure uniform and symmetric. Layout of these switches consisted of parallel linear arrays of

An ever growing market exists for low voltage, low on resistance power switches used in current switching applications. Major applications include battery operated portables such as laptop PCs, low voltage DC/DC converters, regulators and power supplies. It is a general misconception that because of the low voltage specification that these devices do not fit into the category of power devices. The fact of the matter is that these devices need all of the same traditional care abouts as HV power devices. This means that they should have reliable fast switching characteristics and they have to be very robust if considered for catalog contingency. O e method of addressing this market is CO utilize the n knowledge from building higher voltage power devices and applying it to lateral VLSI CMOS devices. To our knowledge other approaches to providing devices for these applications have been with vertical technologies where the solution is generally one discrete or multiple discretes in one package'. An advantage here is that complementary devices cm be fabricated simultaneously and monolithically. In this work the goal was to demonstrate very robust area efficient logic level PMOS devices based on the scaleable Texas Instruments PRISM' technology. The demonsuated performance of the devices was a first pass success and as such TI decided to market the 65mQ packaged version symbolized as a TPSllIO.
0-7803-3 106-0/96$5.0001996 IEEE
71

:igure 1. &-5C ,6m2 device top with 80% shrink device b t o for otm omparison. The die area for t e 100% device is approximately 5K mil2 (3.23 h. mZ)

striped geomeq's. The striped geometry source and drain regions are defined by radiused comer poly silicon (normally not considered as a feature in CMOS devices.) The poly silicon of course is

SOS

% ,, W/L (d) @
Vgs=5V

(a)
@1M Hz

GS

Ci,,(pF)
@Vdd=OV

CO,, Cis, C,,,(PF)

@Vdd=-6V

@IMHz

PMOS
PMOS

65
40

367
641

5.1 5.1

350 600

410,282, 77

NA

accurate. The width to length ration coverts roughly to the width value since it is a 1.0 pm channel length process. Z, is the input impedance and is useful for gaining insight

to the gate oxide thickness. The N-Tank is the same as that used by the 5V logic process and no modifications were made to the other processes steps. The process used is a twin-well 1.Op.m CMOS flow with LOCOS isolation, 2OOA. gate oxide, and triple level metal. Threshold voltages are set at about +/- 0.9V. The first two metal levels are standard across TI. The third level of metal is very thick to keep debiasing down and allow maximum RIPefficiency to be achieved.
Device Electrical Performance and Discussion The devices were packaged in a modified SO8 package for characterization. The die were wired to the lead frame using gold ball bonds. The lateral PMOS device specification rating performance is summarized in table 1 as characterized in the package. Spice equivalent circuit modeling using parametric data obtained from logic devices and process parameters was used to estimate target Rdson values of 69 and 40 Q. Low % is important for low energy loss in the on, state for portable operation. AS indicated in the table 1 and .&own in figure 2 the modeling method proved fairly
72

and very competitive.

Vds = 7v,Id = 3 q s

I1

TPSl 1 10 Vds - 2y/div

!lz

..

. . .

...

: Gate Charge 2.5nCIdiv

j . . .

. .

A. .

..

_.. _.

'Figure 3. Gate Charge U W ~ S for the lateral PMOS T P S ~ ~VS competitor IO vertical PMOS devices. As can be seen, Switching is considerably sharper due h to t e lower amount of charge needing transferred during transition.

Figure 2 shows measured %+ vs 4, performance for the ,, , 2 switches as packaged. The graph indicates fairly linear performance for the 65 rnQ device up to the 6A rating and device out to about 12A for the 40 mQ device. The 40 performs about like the 65 ms;Z device at the V,=-3.0V level. This performance is very flat for lateral devices of this type. Gate charge is defined as the amount of charge that must be transferred to the gate of a MOSFET transistor to drive the device from a full-off state to a full-on state, whle a constant load current is connected to the drain of the DUT. Typical waveforms during the gate charge test are shown in figure 3 for the 6 5 d TPSlllO version. For comparison a competitor part having similar Ronspec&ications is shown. Gate charge is very important for power devices used in switching applications where energy lost in switching time is of utmost importance since the power dissipated by the driver equals Q,'V;f, where f is the switching frequency. The existence of gate charge degrades the performance of a power switch in the following ways: 1. Qps causes a delay-totum-on below VT: 2. There is a finite delay-to-turn-off time because charge must be extracted from the gate: 3. Qgd limits the rate at which v d , can slew: and 4. The total value of gate charge, Qg, must be supplied and dissipated by the user's gate driver circuit during each switching cycle and thus represents an efficiency loss and a power management problem. The time scale of the wave-form in figure 3 is a direct measurement of the charge supplied to the gate since I=dQ/dt and a constant current is supplied to the gate during the test. If the magnitude of the current source is lmA, then lpS of time corresponds to InC of gate charge. The gate charge curve is thus the resultant V wave-form from the , gate charge test. The vd, wave-form indicates the operational state of the transistor. As can be seen in comparison to a competitive device, higher gate charge leads to longer switching time for a given drive and more energy required to transition between states. The surprisingly low capacitances are realized because of the minimal gate to drain overlap associated with lateral devices. The very low input impedance and low gate charge means reduced switching losses, reduced power loss from charge transfer, and reduced power requirements for the drive circuitry. Another advantage to the low capacitance and hence fast switching rate is the ability to switch more uniformly allowing excellent SOA The 2 most rugged types of SOA tests are un-clamped inductive switching ( U I S ) and commutating SOA (CSOA).3 The ruggedness capability is very important to the operation of the device while driving inductive loads. Typical waveforms for these tests are found in figures 4 and 5.
Figure 4. UIS ruggedness testing for the TPSl110 with V a = -6V. V,,= -5V, L-8mH. I,- -40A.

Vds - 5Vfdiv

Figure 5. A typical CSOA switching wave-form shows 28A be& rate of 150A/@S.

switched at a

The UIS test is a stress test where a power device must switch off an un-clamped inductive load. Figure 4 shows a typical UIS characteristic for the 65m!2 device. In the figure, Vd,=-6V and V,=-SV is sourced. The inductive current builds up through the switch while Vds=&,L,n . When the switch is turned off it flys to reverse bias BV govemed by the rate and directional change of di/dt until the inductive energy is dissipated. During this time a very high peak power is attained, and sustaining this peak power is a measure of the avalanche energy capability. In general a robust switch should be able to handle 3 to 5 times the rated current. As can be seen the switch was capable of switching 40A and dissipating l O m J of energy indicating very robust performance!

CSOA is a stress test for the internal body-drain diode of a power transistor. In a CSOA test, a diode is forced to recover while it is still conducting current. A typical CSOA characteristic is shown in figure 5 for the 65mQ device. The
73

Conclusion
2.0 1.8
5

-$

1.6
1.4 1.2

1 1.0 2 o-8 0.6

0.4

3 s
a 22
0

0.2

0.0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 vgs 0 [+V@ m, -vgs

As shown in figure 7 measured at the same gate stress (3MVicm SiO;?),RSpis generally in line with other state of the art lateral and vertical power devices referenced in the figure 4.5,6,7.8,9,10 , making these devices competitive in the low voltage power market with an advantage of being integral with a mature VLSI technology. It is noted that the R,, performance trend tends to flatten since the pitch and hence area factor becomes fairly constant with shrinking feature sizes. An 0.8~1, version of the 65-16? device was produced with a shrink process (shown in figure 1); RSp scaled accordingly while maintaining a 7V rating. By using power device techniques rugged and reliable low voltage lateral power devices can be made from scaleable VLSI CMOS processes.
Acknowledgments

Figure 6. R,, is shown characterized for both n and p channel 7V rated devices. At V,,4V. R,=@.242 and 0.811 mQ2.cm2for n and p channel devices respectively
10
. . .. . .......... . :..+ .......... . .
. .

.Th,t

wo,c

. .................................. . . . . .

The authors thank management support from CP&CP, and HFAB for supporting the development work. We thank Chriss Cooper and Eddie Rivera for die layout support, and many thanks to the outstanding technical support provided by Margie Campbell and Ira Frost on test evaluation.

10

100

BV 0 Figure 7. This works N and P channel performance is shown in comparison with other reported lateral and vertical device performance.

diode forward current is 28A, and the current decay rate during commutation is 15ONp. Again, the device proves to be quite robust! Figure 6 shows RSp vs V characterization. The PMOS , characteristic is not as flat as the NMOS since v ~ 0 . 9 V where for the NMOS Vy0.8V. For VG=6.0V, R,,-0.214&.cm2 and 0.814mChcm2 for n and p devices respectively. Recently ratios of p to n performance of better than 3 have been reported; however, here the ratio as measured under the same conditions is approximately 3 which indicates proportionality to the 3 to 1 mobility of p over n type material.

(11 F. G d e n o u g h , TRENCH-GATE DMOSFETS IN SO* SWITCH 1OA AT 30V, Electronic Design, March 1996, pp.65-72 [21 M. Smayling, et al., A MODULAR MERGED TECHNOLOGY PROCESS INCLUDING SUBMICRON CMOS LOGIC, NONVOLATILE MEMORIES, LINEAR FUNCIIONS, AND POWER COMPONENTS, IEEE CICC, 1993, pp.24.5.1-24.5.4 I31 T. Efland, A. Marshall. D. Skelton, T. Summerlin, SAFE OPERATING AREA TESTING, PRISM, Texas Instruments Technical Journal (dedicated issue), 1994, Vol.11, No.2, pp.82-91. [4] T. Efland et al., AN OFTIMIZED RESURF LDMOS POWER DEVICE MODULE COMPATIBLE WITH ADVANCED LOGIC PROCESSES, IEDM, 1992, pp.237-240 [51 R.S Wrathall, et al., CHARGE CONTROLLED 80 VOLT LATERAL DMOSFET WITH VERY LOW SPECIFIC ON-RESISTANCE DESIGNED FOR AN INTEGRATED POWER PROCESS, IEDM, 1990, pp.954-957 [61 O.Kwon, et al., OFTIMIZED 60V LATERAL DMOS DEVICE FOR VLSI POWER APPLICATIONS, VLSI Technology Symp, 1991, pp.115116 [7] M.Hoshi, et al., LOW ON-RESISTANCE POWER LDMOSFET USING DOUBLE METAL PROCESS TECHNOLOGY, ISPSD, 1991, pp.61-64 ( 1 P.Mei, et al., A HIGH PERFORMANCE 30V EXTENDED DRAIN 8 RESURF C M O S DEVICE FOR VLSI INTELLIGENT POWER APPLICATIONS, VLSI Technology Symp, 1994, pp.81-82 [9] T. Efland, et al.. OPIIMIZED COMPLEMENTARY 40V POWER LDMOS-FETS USE EXISTING FABRICATION STEPS IN SUBMICRON CMOS TECHNOLOGY, IEDM,1994, pp.399-402. [lo] M. Morikawa, et al., A 30V 75 mChmm* POWER MOSFET FOR INTELLIGENT DRIVER LSIs; ISPSD,1992, pp.150-154

74