IRFP460A, SiHFP460A

Vishay Siliconix

Power MOSFET
PRODUCT SUMMARY
VDS (V) RDS(on) () Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 105 26 42 Single
D

FEATURES
500 0.27

Low Gate Charge Qg Results in Simple Drive Available Requirement Improved Gate, Avalanche and Dynamic dV/dt RoHS* COMPLIANT Ruggedness Fully Characterized Capacitance and Avalanche Voltage and Current Effective Coss Specified Compliant to RoHS Directive 2002/95/EC

TO-247

APPLICATIONS
Switch Mode Power Supply (SMPS) Uninterruptable Power Supply High Speed Power Switching

TYPICAL SMPS TOPOLOGIES

S D G S N-Channel MOSFET

Full Bridge PFC Boost

ORDERING INFORMATION
Package Lead (Pb)-free SnPb TO-247 IRFP460APbF SiHFP460A-E3 IRFP460A SiHFP460A

ABSOLUTE MAXIMUM RATINGS TC = 25 C, unless otherwise noted

PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta VGS at 10 V TC = 25 C TC = 100 C SYMBOL VDS VGS ID IDM EAS IAR EAR TC = 25 C PD dV/dt TJ, Tstg for 10 s 6-32 or M3 screw LIMIT 500 30 20 13 80 2.2 960 20 28 280 3.8 - 55 to + 150 300d 10 1.1 W/C mJ A mJ W V/ns C lbf in Nm A UNIT V

Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque

Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 C, L = 4.3 mH, Rg = 25 , IAS = 20 A (see fig. 12). c. ISD 20 A, dI/dt 125 A/s, VDD VDS, TJ 150 C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91234 S09-1284-Rev. B, 13-Jul-09 www.vishay.com 1

IRFP460A, SiHFP460A
Vishay Siliconix

THERMAL RESISTANCE RATINGS

PARAMETER Maximum Junction-to-Ambient Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Case (Drain) SYMBOL RthJA RthCS RthJC TYP. 0.24 MAX. 40 0.45 C/W UNIT

SPECIFICATIONS TJ = 25 C, unless otherwise noted

PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode
D

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

VDS VDS/TJ VGS(th) IGSS IDSS RDS(on) gfs Ciss Coss Crss Coss Coss eff. Qg Qgs Qgd td(on) tr td(off) tf

VGS = 0 V, ID = 250 A Reference to 25 C, ID = 1 mA VDS = VGS, ID = 250 A VGS = 30 V VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 125 C VGS = 10 V ID = 12 Ab Ab

500 2.0 11

0.61 -

4.0 100 25 250 0.27 -

V V/C V nA A S

VDS = 50 V, ID = 12

VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VDS = 1.0 V, f = 1.0 MHz VGS = 0 V VDS = 400 V, f = 1.0 MHz VDS = 0 V to 400 Vc

3100 480 18 4430 130 140

pF

VGS = 10 V ID = 20 A, VDS = 400 V, see fig. 6 and 13b VDD = 250 V, ID = 20 A, RG = 4.3 , RD = 13 , see fig. 10b -

18 55 45 39

105 26 42 ns nC

480 5.0

20 A 80 1.8 710 7.5 V ns C

TJ = 25 C, IS = 20A, VGS = 0

Vb

TJ = 25 C, IF = 20 A, dI/dt = 100 A/sb

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 s; duty cycle 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDS.

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Document Number: 91234 S09-1284-Rev. B, 13-Jul-09

IRFP460A, SiHFP460A
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 C, unless otherwise noted

102

VGS

102

ID, Drain-to-Source Current (A)

ID, Drain-to-Source Current (A)

Top

10

15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V

150 C 10 25 C

4.5 V

0.1 0.1
91234_01

20 s Pulse Width TC = 25 C 1 10 102

0.1 4.0
91234_03

20 s Pulse Width VDS = 50 V 5.0 6.0 7.0 8.0 9.0

VDS, Drain-to-Source Voltage (V)

Fig. 1 - Typical Output Characteristics

VGS, Gate-to-Source Voltage (V)

Fig. 3 - Typical Transfer Characteristics

RDS(on), Drain-to-Source On Resistance (Normalized)

102

VGS
Top 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V

3.0 2.5 2.0 1.5 1.0 0.5

ID, Drain-to-Source Current (A)

ID = 20 A VGS = 10 V

10

4.5 V

1 1
91234_02

20 s Pulse Width TC = 150 C 10 102

0.0 - 60 - 40 - 20

20 40 60 80 100 120 140 160

VDS, Drain-to-Source Voltage (V)

Fig. 2 - Typical Output Characteristics

91234_04

TJ, Junction Temperature (C)

Fig. 4 - Normalized On-Resistance vs. Temperature

Document Number: 91234 S09-1284-Rev. B, 13-Jul-09

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IRFP460A, SiHFP460A
Vishay Siliconix

105

104

ISD, Reverse Drain Current (A)

Capacitance (pF)

VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd Ciss

102

10

150 C 25 C

103

102

Coss

10 Crss 1 1
91234_05

0.1 10 102 103

91234_07

VGS = 0 V 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

VDS, Drain-to-Source Voltage (V)

VSD, Source-to-Drain Voltage (V)

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

20

VGS, Gate-to-Source Voltage (V)

ID = 20 A VDS = 400 V VDS = 250 V

103

Operation in this area limited by RDS(on)

16

ID, Drain Current (A)

102 10 s 100 s 10 1 ms TC = 25 C TJ = 150 C Single Pulse 10 102 10 ms 103 104

12

VDS = 100 V

4
For test circuit see figure 13

0 0
91234_06

20

40

60

80

100
91234_08

QG, Total Gate Charge (nC)

VDS, Drain-to-Source Voltage (V)

Fig. 8 - Maximum Safe Operating Area

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

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Document Number: 91234 S09-1284-Rev. B, 13-Jul-09

IRFP460A, SiHFP460A
Vishay Siliconix
RD VDS VGS D.U.T. + - VDD 10 V
Pulse width 1 s Duty factor 0.1 %

20

RG

ID, Drain Current (A)

15

10

Fig. 10a - Switching Time Test Circuit

VDS 90 %

0 25
91234_09

50

75

100

125

150

TC, Case Temperature (C)

10 % VGS td(on) tr td(off) tf

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10b - Switching Time Waveforms

Thermal Response (ZthJC)

D = 0.5 0.1 0.2 0.1 0.05 10-2 0.02 0.01 Single Pulse (Thermal Response) PDM t1 t2 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC 10-4 10-3 10-2 0.1 1

10-3 10-5
91234_11

t1, Rectangular Pulse Duration (S)

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

15 V

VDS tp

VDS

Driver

RG 20 V tp

D.U.T. IAS 0.01

+ A - VDD

IAS

Fig. 12a - Unclamped Inductive Test Circuit

Fig. 12b - Unclamped Inductive Waveforms

Document Number: 91234 S09-1284-Rev. B, 13-Jul-09

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IRFP460A, SiHFP460A
Vishay Siliconix

EAS, Single Pulse Avalanche Energy (mJ)

2400 2000 1600 1200 800 400 0 25 50 75 100 125 150 Starting TJ, Junction Temperature (C)

VDSav, Avalanche Voltage (V)

ID Top 8.9 A 13 A Bottom 20 A

620

600

580

560

540 0
91234_12d

12

16

20

91234_12c

IAV, Avalanche Current (A)

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 12d - Typical Drain-to-Source Voltage vs. Avalanche Current

Current regulator Same type as D.U.T.

50 k
12 V

10 V QGS

QG
0.2 F

0.3 F

QGD D.U.T.

+ -

VDS

VG

VGS
3 mA

Charge
IG ID Current sampling resistors

Fig. 13a - Basic Gate Charge Waveform

Fig. 13b - Gate Charge Test Circuit

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Document Number: 91234 S09-1284-Rev. B, 13-Jul-09

IRFP460A, SiHFP460A
Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

D.U.T.

Circuit layout considerations Low stray inductance Ground plane Low leakage inductance current transformer

+ +

RG

dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test

+ VDD

Driver gate drive P.W. Period D=

P.W. Period VGS = 10 V*

D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt

VDD

Re-applied voltage Inductor current

Body diode forward drop

Ripple 5 %

ISD

* VGS = 5 V for logic level devices

Fig. 14 - For N-Channel

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91234.

Document Number: 91234 S09-1284-Rev. B, 13-Jul-09

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Package Information
Vishay Siliconix
TO-247AC (HIGH VOLTAGE)
4 B 3 R/2 Q 2xR (2) 1 5 L1 C L See view B 2 x b2 3xb 0.10 M C A M 2x e b4 A1 Planting D DE E C C (c) c1 (b, b2, b4) View B (4) Section C - C, D - D, E - E (b1, b3, b5) Base metal C A 5 E1 0.01 M D B M View A - A 2 3 E E/2 S A2 A D2 5 D D Thermal pad 4 D1 A 7 P k M DBM A (Datum B) P1

MILLIMETERS DIM. A A1 A2 b b1 b2 b3 b4 b5 c c1 D D1 MIN. 4.65 2.21 1.50 0.99 0.99 1.65 1.65 2.59 2.59 0.38 0.38 19.71 13.08 MAX. 5.31 2.59 2.49 1.40 1.35 2.39 2.37 3.43 3.38 0.86 0.76 20.70 MIN.

INCHES MAX. 0.209 0.102 0.098 0.055 0.053 0.094 0.093 0.135 0.133 0.034 0.030 0.815 DIM. D2 E E1 e k L L1 N P P1 Q R S

MILLIMETERS MIN. 0.51 15.29 13.72 5.46 BSC 0.254 14.20 3.71 16.10 4.29 MAX. 1.30 15.87 MIN.

INCHES MAX. 0.051 0.625 -

0.183 0.087 0.059 0.039 0.039 0.065 0.065 0.102 0.102 0.015 0.015 0.776 0.515

0.020 0.602 0.540

0.215 BSC 0.010 0.559 0.146 0.300 BSC 0.140 0.209 0.178 0.144 0.291 0.224 0.216 0.634 0.169

7.62 BSC 3.56 5.31 4.52 3.66 7.39 5.69 5.49

5.51 BSC

0.217 BSC

ECN: S-81920-Rev. A, 15-Sep-08 DWG: 5971 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Contour of slot optional. 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outermost extremes of the plastic body. 4. Thermal pad contour optional with dimensions D1 and E1. 5. Lead finish uncontrolled in L1. 6. P to have a maximum draft angle of 1.5 to the top of the part with a maximum hole diameter of 3.91 mm (0.154"). 7. Outline conforms to JEDEC outline TO-247 with exception of dimension c.

Document Number: 91360 Revision: 15-Sep-08

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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment (EEE) - recast, unless otherwise specified as non-compliant. Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.

Revision: 12-Mar-12

Document Number: 91000