SN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS

SDAS220B DECEMBER 1982 REVISED DECEMBER 1994

Multiplexed I/O Ports Provide Improved Bit Density Four Modes of Operation: Hold (Store) Shift Right Shift Left Load Data Operate With Outputs Enabled or at High Impedance 3-State Outputs Drive Bus Lines Directly Can Be Cascaded for n-Bit Word Lengths Direct Overriding Clear Applications: Stacked or Push-Down Registers Buffer Storage Accumulator Registers Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

SN54ALS299 . . . J PACKAGE SN74ALS299 . . . DW OR N PACKAGE (TOP VIEW)

S0 OE1 OE2 G/QG E/QE C/QC A/QA QA CLR GND

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

VCC S1 SL QH H/QH F/QF D/QD B/QB CLK SR

SN54ALS299 . . . FK PACKAGE (TOP VIEW)

OE2 OE1 S0 VCC G/QG E/QE C/QC A/QA QA

4 5 6 7 8

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

S1 SL QH H/QH F/QF D/QD

description
These 8-bit universal shift /storage registers feature multiplexed I/O ports to achieve full 8-bit data handling in a single 20-pin package. Two function-select (S0, S1) inputs and two outputenable (OE1, OE2) inputs can be used to choose the modes of operation listed in the function table.

Synchronous parallel loading is accomplished by taking both S0 and S1 high. This places the 3-state outputs in the high-impedance state and permits data applied on the I/O ports to be clocked into the register. Reading out of the register can be accomplished while the outputs are enabled in any mode. Clearing occurs asynchronously when the clear (CLR) input is low. Taking either OE1 or OE2 high disables the outputs, but has no effect on clearing, shifting, or storing data. The SN54ALS299 is characterized for operation over the full military temperature range of 55C to 125C. The SN74ALS299 is characterized for operation from 0C to 70C.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1994, Texas Instruments Incorporated

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CLR GND SR CLK B/Q B

SN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS

SDAS220B DECEMBER 1982 REVISED DECEMBER 1994

FUNCTION TABLE INPUTS MODE CLR L L L H H H H H H H S1 X L H L X L L H H H S0 L X H L X H H L L H OE1 L L X L L L L L L X OE2 L L X L L L L L L X CLK X X X X L SL X X X X X X X H L X SR X X X X X H L X X X A/QA L L X QA0 QA0 H L QBn QBn a B/QB L L X QB0 QB0 QAn QAn QCn QCn b C/QC L L X QC0 QC0 QBn QBn QDn QDn c I/O PORTS D/QD L L X QD0 QD0 QCn QCn QEn QEn d E/QE L L X QE0 QE0 QDn QDn QFn QFn e F/QF L L X QF0 QF0 QEn QEn QGn QGn f G/QG L L X QG0 QG0 QFn QFn QHn QHn g H/QH L L X QH0 QH0 QGn QGn H L h OUTPUTS QA L L L QA0 QA0 H L QBn QBn a QH L L L QH0 QH0 QGn QGn H L h

Clear

Hold Shift Right Shift Left Load

NOTE: a . . . h = the level of the steady-state input at inputs A through H, respectively. This data is loaded into the flip-flops while the flip-flop outputs are isolated from the I/O terminals. When one or both output-enable inputs are high, the eight I/O terminals are disabled to the high-impedance state; however, sequential operation or clearing of the register is not affected.

logic symbol
CLR OE1 OE2 S0 S1 CLK SR A /QA 13 1 19 12 C4/1/2 11 7 1,4D 3,4D 5, 13 B/QB 3,4D 6, 13 C/QC D/QD E/QE F/QF G/QG H/QH SL 6 14 5 15 4 16 3,4D 12, 13 2,4D Z12 17 QH Z6 Z5 8 QA 0 1 M 9 2 3 R & SRG8

3EN13 0 3

18

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

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SN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS

SDAS220B DECEMBER 1982 REVISED DECEMBER 1994

logic diagram (positive logic)

S0 1

S1

19 18 11 Six Identical Channels Not Shown 12 1D C1 R R 17 QH 1D C1 SL (shift left serial input)

SR (shift right serial input)

CLK

QA CLR

8 9

OE1 OE2

2 3 7 A /QA 16 H /QH

I/O ports not shown: B/QB (13), C/QC (6), D/QD (14), E/QE (5), F/QF (15), and G/QG (4).

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI: All inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range, TA: SN54ALS299 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 125C SN74ALS299 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to 70C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

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SN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS

SDAS220B DECEMBER 1982 REVISED DECEMBER 1994

recommended operating conditions

SN54ALS299 MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level High level output current Low level output current Low-level Operating free-air temperature QA or QH QA QH QA or QH QA QH 55 4.5 2 0.7 0.4 1 4 12 125 0 NOM 5 MAX 5.5 SN74ALS299 MIN 4.5 2 0.8 0.4 2.6 8 24 70 NOM 5 MAX 5.5 UNIT V V V mA mA C

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER VIK All outputs VOH QA QH QA or QH VOL QA QH II IIH IIL IO S0, S1, SR, SL Any others QA or QH QA QH AH Any others VCC = 4 5 V 4.5 VCC = 5 5 V 5.5 VCC = 5.5 V, VCC = 5 5 V 5.5 V, VCC = 5 5 V 5.5 V, TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V to 5.5 V, VCC = 4 5 V 4.5 VCC = 4 5 V 4.5 II = 18 mA IOH = 0.4 mA IOH = 1 mA IOH = 2.6 mA IOL = 4 mA IOL = 8 mA IOL = 12 mA IOL = 24 mA VI = 5.5 V VI = 7 V VI = 2.7 V VI = 0 4 V 0.4 VO = 2 25 V 2.25 Outputs high ICC VCC = 5.5 V Outputs low Outputs disabled 15 20 15 22 23 SN54ALS299 MIN TYP MAX 1.5 VCC 2 2.4 VCC 2 3.3 2.4 0.25 0.25 0.4 0.4 0.1 0.1 20 0.2 0.1 70 112 28 38 40 15 30 15 22 23 3.2 0.25 0.35 0.25 0.35 0.4 0.5 0.4 0.5 0.1 0.1 20 0.2 0.1 70 112 28 38 40 mA mA A mA mA V V SN74ALS299 MIN TYP MAX 1.5 UNIT V

All typical values are at VCC = 5 V, TA = 25C. For I/O ports (QA QH), the parameters IIH and IIL include the off-state output current. The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.

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SN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS

SDAS220B DECEMBER 1982 REVISED DECEMBER 1994

timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
SN54ALS299 MIN fclock tw Clock frequency (at 50% duty cycle) Pulse duration CLK high or low CLR low S0 or S1 tsu Setup time before CLK Inactive-state setup time before CLK th Hold time after CLK High Serial or parallel data CLR S0 or S1 Serial or parallel data Low 0 22 12 25 18 15 15 0 0 MAX 17 SN74ALS299 MIN 0 16.5 10 20 16 6 15 0 0 ns ns MAX 30 UNIT MHz ns

Inactive-state setup time is also referred to as recovery time.

switching characteristics (see Figure 1)

VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 , R2 = 500 , TA = MIN to MAX SN54ALS299 SN74ALS299 MIN fmax tPLH tPHL tPLH tPHL tPHL tPZH tPZL tPZH tPZL tPHZ tPLZ tPHZ tPLZ 17 2 CLK CLK QA QH QA or QH QA QH QA or QH QA QH QA QH QA QH QA QH 4 2 4 6 6 5 OE1, OE1 OE2 S0, S0 S1 OE1, OE1 OE2 S0, S0 S1 6 5 6 1 4 1 4 19 25 21 25 29 29 22 27 27 26 15 38 16 34 MAX MIN 30 4 7 5 8 6 6 6 8 7 8 1 5 1 8 13 19 15 18 22 22 16 22 17 22 8 15 12 25 MAX MHz ns ns

PARAMETER

FROM (INPUT)

TO (OUTPUT)

UNIT

CLR

ns

ns ns ns ns

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

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SN54ALS299, SN74ALS299 8-BIT UNIVERSAL SHIFT/STORAGE REGISTERS WITH 3-STATE OUTPUTS

SDAS220B DECEMBER 1982 REVISED DECEMBER 1994

PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES

7V VCC S1 RL From Output Under Test CL (see Note A) RL Test Point R1 From Output Under Test CL (see Note A) Test Point From Output Under Test CL (see Note A) R2 Test Point RL = R1 = R2

LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS

LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS

LOAD CIRCUIT FOR 3-STATE OUTPUTS

Timing Input tsu Data Input 1.3 V

3.5 V 1.3 V 0.3 V th 3.5 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES

High-Level Pulse

3.5 V 1.3 V tw 1.3 V 0.3 V

Low-Level Pulse

3.5 V 1.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS PULSE DURATIONS

Output Control (low-level enabling) tPZL Waveform 1 S1 Closed (see Note B)

3.5 V 1.3 V 1.3 V 0.3 V tPLZ 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V 3.5 V Input tPLH In-Phase Output 1.3 V 1.3 V 1.3 V 0.3 V tPHL VOH 1.3 V VOL tPLH VOH 1.3 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 1.3 V VOL

[3.5 V

tPHZ tPZH Waveform 2 S1 Open (see Note B)

tPHL Out-of-Phase Output (see Note C)

[0 V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

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