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This chapter provides guidelines to help simulate your Altera designs using EDA simulators. Simulation is the process of verifying the design behavior before configuring the device. You can use one of the following simulation tool flows:
Automatically create scripts to set up and launch an EDA simulator with the Quartus II NativeLink feature Manually set up a simulation in your EDA simulator, optionally using the Simulation Library Compiler Use the scripts provided with your IP to set up your simulation environment, if your design includes IP cores
Altera supports ModelSim, ModelSim-Altera, QuestaSim, VCS, VCS MX, Cadence Incisive Enterprise Simulator, Active-HDL, and Riviera-PRO simulators. f The Altera Complete Design Suite (ACDS) provides the ModelSim-Altera simulator in which all Altera libraries are precompiled. For more information about ModelSimAltera software, refer to the ModelSim-Altera Software page of the Altera website. This chapter includes the following topics:
Design Flow on page 12 Simulation Library Compiler on page 18 Launching the EDA Simulator with the NativeLink Feature on page 19 Simulating Altera IP Cores on page 114 Simulating Qsys and SOPC Builder System Designs on page 124
2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Design Flow
This section describes the simulation flows supported by the Quartus II software, including functional, post-synthesis, and gate-level simulation. Figure 11 shows how these simulation flows fit within a typical design flow.
Figure 11. Quartus II Design Flow Incorporating Simulation
Design entry (Verilog HDL/VHDL/BDF) (4) Functional simulation (3)
Fitter (place-and-route) Optional (2) Timing analysis with the TimeQuest Timing Analyzer Generate simulation netlist files (Timing/Functional) (1) Gate-level simulation (3)
Program device
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Yes
No
No (6)
Yes
No
No (4)
Yes Specify NativeLink settings and run Analysis and Elaboration (1)
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h For more information about performing functional simulation with ModelSim, QuestaSim, VCS, VCS-MX, Incisive Enterprise Simulator, Active-HDL, and Riviera-PRO, refer to the following, respectively, in Quartus II Help:
Performing a Functional Simulation with the ModelSim Software Performing a Timing Simulation with the QuestaSim Software Performing a Functional Simulation with the VCS Software Performing a Functional Simulation with the VCS MX Software Performing a Functional Simulation with the Incisive Enterprise Simulator Software Performing a Simulation of a Verilog HDL Design with the Active-HDL Software Performing a Simulation of a VHDL Design with the Active-HDL Software Performing an Functional Simulation with the Riviera-PRO Software
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No
No (4)
Yes Specify NativeLink settings and run Analysis and Elaboration (1)
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Altera Corporation
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h For more information about performing timing simulation with ModelSim, QuestaSim, VCS, VCS-MX, Incisive Enterprise Simulator, Active-HDL, and Riviera-PRO, refer to the following, respectively, in Quartus II Help:
Performing a Timing Simulation with the ModelSim Software Performing a Timing Simulation with the QuestaSim Software Performing a Timing Simulation with the VCS Software Performing a Timing Simulation with the VCS-MX (VHDL) Software Performing a Timing Simulation with the Incisive Enterprise Simulator Software Performing a Simulation of a Verilog HDL Design with the Active-HDL Software Performing a Simulation of a VHDL Design with the Active-HDL Software Performing a Gate-Level Simulation with the Riviera-PRO Software
Altera recommends that you use the TimeQuest Timing analyzer to achieve timing closure, rather than gate-level timing simulation. Post-fit gate-level timing simulation is not available for Stratix V, Arria V, and Cyclone V device families.
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To generate the post-synthesis simulation netlist using the command line, type the following commands at a command prompt:
quartus_map <project name> -c <revision name> r quartus_sta <project name> -c <revision name> --post_map r quartus_eda <project name> -c <revision name> --simulation --functional \ --tool= <3rd-party EDA tool> --format=<HDL language> r
For more information about the -format and -tool options, type the following command at a command prompt:
quartus_eda --help=<option> r
Generating Timing Simulation Netlist Files with Different Timing Models In Arria II GX, Cyclone III, HardCopy III, Stratix III, and later devices, you can specify different temperature and voltage parameters to generate the timing simulation netlist files with the Quartus II TimeQuest analyzer. When you generate the timing simulation netlist files (.vo, .vho, and .sdo files), different timing models for different operating conditions are used by default. Multi corner timing analysis is run by default during the full compilation. h For more information about generating timing simulation netlist files with different timing models, refer to EDA Gate Level Simulation (Tools Menu) in Quartus II Help. To manually generate the simulation netlist files (.vo or .vho and .sdo) for the three different operating conditions, follow these steps: 1. Generate all available corner models at all operating conditions by typing the following command at a command prompt:
quartus_sta <project name> --multicorner r
2. Generate the timing simulation netlist files for all three corners. The output files are generated in the simulation output directory. h For more information about how to generate a gate-level timing simulation netlist in the Quartus II software, refer to Generating Simulation Netlist Files in Quartus II Help. The following examples show the timing simulation netlist file names generated for the operating conditions of the preceding steps when Verilog HDL is selected as the output netlist format. First Slow Corner (slow, 1100 mV, 85 C)
The <revision_name>.vo and <revision name>_v.sdo are generated for backward compatibility when there are existing scripts that continue to use them.
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Altera Corporation
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f For more information about performing multi-corner timing analysis, refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook.
h For more information about compiling simulation libraries from the GUI, refer to Compiling Simulation Libraries in the Quartus II Software in Quartus II Help.
Chapter 1: Simulating Altera Designs Launching the EDA Simulator with the NativeLink Feature
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Chapter 1: Simulating Altera Designs Launching the EDA Simulator with the NativeLink Feature
5. Click OK. You can also specify the path to the simulators executables by typing the set_user_option Tcl command at the Tcl console, as follows:
set_user_option -name EDA_TOOL_PATH_MODELSIM <path to executables> r set_user_option -name EDA_TOOL_PATH_MODELSIM_ALTERA <path to \ executables> r set_user_option -name EDA_TOOL_PATH_QUESTASIM <path to executables> r set_user_option -name EDA_TOOL_PATH_VCS <path to executables> r set_user_option -name EDA_TOOL_PATH_VCS_MX <path to executables> r set_user_option -name EDA_TOOL_PATH_NCSIM <path to executables> r set_user_option -name EDA_TOOL_PATH_ACTIVEHDL <path to executables> r set_user_option -name EDA_TOOL_PATH_RIVIERAPRO <path to executables> r
To open the Tcl console, on the View menu, point to Utility Windows, then click Tcl Console.
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For more information about setting up a testbench file with NativeLink, refer to Setting Up Testbench Files Using the NativeLink Feature on page 112. 6. If you want to run the EDA simulator in command-line mode, follow these steps: a. On the Simulation page, click More NativeLink Settings. The More NativeLink Settings dialog box appears. b. Under Existing option settings, click Launch third-party EDA tool in command-line mode. c. In the Setting box, click On. d. Click OK. 7. If you want to generate only the simulation script without launching the EDA simulator during NativeLink simulation, follow these steps: a. On the Simulation page, click More NativeLink Settings. The More NativeLink Settings dialog box appears. b. Under Existing option settings, click Generate third-party EDA tool command scripts without running the EDA tool. c. In the Setting box, click On. d. Click OK. If you turn this option on and run NativeLink, only the simulation command script is generated. The file names of simulation command scripts for various simulators are as follows:
<project_name>_run_msim_<rtl/gate>_level_<verilog/vhdl>.do (ModelSim) <project_name>_run_questasim_<rtl/gate>_level_<verilog/vhdl>.do (QuestaSim) <project_name>_sim_<rtl/gate>_<verilog/vhdl>.do (Riviera-PRO and Active-HDL) script_file.sh and <project_name>_rtl.vcs (VCS) <project_name>_vcsmx_<rtl/gate>_<vhdl/verilog>.tcl (VCS MX) <project_name>_ncsim_<rtl/gate>_<verilog/vhdl>.tcl (Incisive Enterprise Simulator)
8. Depending on the simulator, perform the simulation by typing one of the following commands: do <script>.do r (ModelSim/Aldec/Riviera-PRO macro file) quartus_sh -t <script>.tcl r (Tcl Script File) sh <script>.sh r (Shell script)
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Chapter 1: Simulating Altera Designs Launching the EDA Simulator with the NativeLink Feature
9. If you have compiled libraries using the Simulation Library Compiler, follow these steps: a. On the Simulation page, click More EDA Netlist Writer Settings. The More EDA Netlist Writer Settings dialog box appears. b. Under Existing option settings, click Location of user compiled simulation library. c. In the Setting box, type the path that contains the user-compiled libraries generated from the Simulation Library Compiler. The path should be the same as the path you have set in the Output Directory in the Simulation Library Compiler. 1 Step 9 is not applicable for Active-HDL and Riviera-PRO.
For more information about the Simulation Library Compiler, refer to Simulation Library Compiler on page 18. h For more information about using the Quartus II software with other EDA tools, refer to About Using the Quartus II Software with Other EDA Tools in Quartus II Help.
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4. Under NativeLink settings, select None, Compile test bench, or Script to compile test bench (Table 12).
Table 12. NativeLink Testbench Settings Setting None Compile test bench Description NativeLink compiles simulation models and design files. NativeLink compiles simulation models, design files, testbench files, and starts simulation. NativeLink compiles the simulation models and design files. The script you provide is sourced after design files are compiled. Use this option when you want to create your own script to compile your testbench file and perform simulation.
If you select Compile test bench, select your testbench setup from the Compile test bench list. You can use different testbench setups to specify different test scenarios. If there are no testbench setups entered, create a testbench setup by following these steps:
a. Click Test Benches. The Test Benches dialog box appears. b. Click New. The New Test Bench Settings dialog box appears. c. In the Top level module in test bench box, type the top-level testbench entity or module name. The testbench name in the Test bench name box automatically follows the top-level testbench entity or module name. d. If you are running gate-level timing simulation for VHDL designs, turn on Use test bench to perform VHDL timing simulation checkbox and specify your top level instance name of your design. This is equivalent to the vsim command option -sdftyp. In the Design instance name in test bench box, type the full instance path to the top level of your FPGA design. e. Under Simulation period, select Run simulation until all vector stimuli are used or specify the end time of the simulation. f. Under Test bench files, browse and add all of your testbench files in the File name box. Use the Up and Down buttons to reorder your files. The NativeLink feature compiles the files in order from top to bottom. 1 You can also specify the library name and HDL version to compile the testbench file by adding the file, selecting it from the list, and clicking Properties. The NativeLink feature compiles the testbench file to a library name using the specified HDL version.
g. Click OK. h. In the Test benches dialog box, click OK. i. If you have a script to set up your simulation, turn on Use script to set up simulation. Click Browse and select your simulation setup script.
If you select Script to compile test bench, browse to your script, and then click OK.
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You can also use the NativeLink feature in your script to compile your design files and testbench files with customized settings.
c Use IPFS models for simulation only. Do not use them for synthesis or any other purpose. Using these models for synthesis results in a nonfunctional design. 1 Encrypted Altera simulation model files shipped with the Quartus II software version 10.1 and later can only be read by the ModelSim-Altera Edition Software version 6.6c and later. These encrypted simulation model files are located at the <Quartus II System directory>/quartus/eda/sim_lib/<eda simulation vendor> directory, where <eda simulation vendor> is aldec, cadence, mentor, or synopsys.
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IP Simulation Flows
The parameter editor for each IP core allows you to quickly and easily view documentation, specify parameters, and generate simulation models and other output files necessary to integrate the IP core into your design. When you use the MegaWizard Plug-In Manager to parameterize your IP core, the Quartus II software generates a Quartus II IP File (.qip) for inclusion in your Quartus II project. For IP cores that use IPFS models, the Quartus II software can also generate a .vo or .vho file that contains an IPFS model. For IP cores that use IEEE encrypted Verilog HDL models or plain-text HDL, the generated directory structure is shown in Figure 15 on page 117. h For a list of the functional simulation library files, refer to Altera Functional Simulation Libraries in Quartus II Help. For a list of the gate-level timing simulation library files, refer to Altera Post-Fit Libraries in Quartus II Help.
Synthesis Files
For synthesis purposes, a <variant_name>.qip is generated in your project directory for each IP core variation in your design. If you specify Verilog HDL or VHDL as the output file type, an IP variant file (<variant_name>.v or <variant_name>.vhd) is generated, respectively. The .qip is a single file that contains synthesis information required for processing by the Quartus II Compiler. For hw.tcl compliant IP cores, a <variant_name> subdirectory is created in the project directory. This directory contains files needed for synthesis, and might also contain Synopsys Design Constraints Files (.sdc), Tcl Script Files (.tcl), and Pin Planner Files (.ppf). To compile your design in the Quartus II software, add the <variant_name>.qip files to your project, along with your design files. Additional steps might be necessary, depending on the IP core. f For more information, refer to the appropriate IP core user guide, available on the User Guides literature page of the Altera website.
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Simulation Files
The form and structure of simulation models that support Altera IP cores vary. IP cores use the simulation models that are provided in the quartus/eda/sim_lib directory of your Quartus II installation. Altera provides some of the models in this directory as plain-text VHDL and Verilog HDL, while other models are IEEE encrypted Verilog HDL for each of the Altera-supported EDA simulation vendors. You can simulate the IEEE encrypted Verilog HDL models in VHDL designs if you have a VHDL/Verilog HDL co-simulator. You can also simulate the IEEE encrypted Verilog HDL models in any version of ModelSim, including the VHDL-only versions of ModelSim-Altera and ModelSim PE, because of the special arrangement between Altera and Mentor Graphics. Depending on the specific IP core, Altera may provide simulation models in one or more of the following formats:
Plain-text in Verilog HDL, VHDL, or both Mixed structural IPFS model in .vho and .vo IEEE encrypted Verilog models for each supported EDA simulation vendor
IP cores that use the hw.tcl infrastructure provide a set of standardized vendorspecific simulation scripts, which you can use to compile and elaborate the IP cores in your simulator. You can use these scripts as a reference for developing your systemlevel simulation scripts. When you generate your IP cores, the Quartus II software creates the simulation files in the project directory. Figure 14 shows an example of the directory hierarchy for simulation models and scripts for hw.tcl-based IP cores.
Figure 14. Directory Hierarchy for hw.tcl Based IP
<variant_name>_sim This directory contains the files for simulation. <variant_name>.v for Verilog models <variant_name>.vhd for VHDL models <vendor_name> <simulation_script_files> <sub_module_name> <simulation_model_files>
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Figure 15 shows examples of directory hierarchies for simulation files for other IP cores.
Figure 15. Directory Hierarchy for Other IP Cores
<variant_name>_sim This directory contains the files for simulation. <simulation_model_files>
<variant_name>_sim This directory contains the files for simulation. <IP_core_name> <simulation_model_files> <simulation_vendor_name> <IEEE_encrypted_Verilog_simulation_model_files>
Some Altera IP cores include design examples, testbenches, simulator script examples, and/or Quartus II project examples within one of the directory structures in Figure 14 and Figure 15. f For IP core-specific information and details about simulating IP example designs and testbenches, refer to the appropriate IP core user guide, available on the User Guides Literature page of the Altera website.
TOP_LEVEL_NAME: If the IP core is not the top-level instance in your simulation environment because you instantiate the IP testbench within your own top-level simulation file, set the TOP_LEVEL_NAME variable to the top-level hierarchy name.
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QSYS_SIMDIR: If the simulation files generated by your IP cores are not in the simulation working directory, use the QSYS_SIMDIR variable to specify the directory location of the simulation files. This variable name is also used for designs generated by the Qsys system integration tool. Other variables to control the compilation, elaboration, and simulation process.
If your top-level design includes multiple hw.tcl-based IP cores, you can use a combination of the generated scripts as a reference to create your own top-level system simulation scripts. Example 11 shows a simple top-level simulation HDL file for an IP core my_ip. The top.sv file defines the top module that instantiates the IP simulation model as well as a custom SystemVerilog testbench program with test stimulus, called test_program.
Example 11. Top-level Simulation HDL File Example top.sv
module top(); my_ip tb(); test_program pgm(); endmodule
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The script calls the generated ModelSim script and uses the alias commands from msim_setup.tcl to compile and elaborate the IP files required for simulation along with the custom test program and top-level simulation file. You can specify additional ModelSim elaboration command options when you run the elab command, for example, elab +nowarnTFMPC. The last run command starts the simulation.
Example 12. Top-level ModelSim Simulation Script Including Custom Test Program
# Set hierarchy variables used in the IP-generated files set TOP_LEVEL_NAME "top" set QSYS_SIMDIR "./my_ip_sim" # Source generated script and set up alias commands used below source $QSYS_SIMDIR/mentor/msim_setup.tcl # Compile device library files dev_com # Compile design files in correct order com # Compile the additional test files vlog -sv ./test_program.sv vlog -sv ./top.sv # Elaborate the top-level design elab # Run the full simulation run - all
Using a top-level simulation script and test program takes advantage of the generated ModelSim script to ensure you compile all the required simulation files and allows you to modify the top-level simulation environment independently of the IP simulation files that are over-written when you modify your IP parameterization core and regenerate. Example 13 shows how you can use the generated scripts in your own top-level system simulation environment if your top-level design includes multiple hw.tclbased IP cores. This example script complies two IP cores and elaborates the second IP.
Example 13. Top-level Modelism Simulation Script Including Two IP Cores
// compile first IP set QSYS_SIMDIR "./ip_one_top_sim" source $QSYS_SIMDIR/mentor/msim_setup.tcl dev_com com // compile and elaborate second IP set QSYS_SIMDIR "./ip_two_top_sim" set TOP_LEVEL_NAME "ip_two_top" source $QSYS_SIMDIR/mentor/msim_setup.tcl dev_com com elab
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h The hard IP implementation of the IP Compiler for PCI Express requires the PCIe libraries for simulation. For more information, refer to Altera Functional Simulation Libraries in Quartus II Help. This section describes the different options available to simulate Altera IP cores that are not based on hw.tcl. If your IP core is based on hw.tcl and generates vendor-specific simulation scripts, refer to Perform Functional Simulation with IP Cores Based on _hw.tcl on page 117.
f Generating an IPFS model for Altera IP cores does not require a license. However, generating an IPFS model for AMPP megafunctions may require a license. For more information about AMPP licensing requirements, refer to Obtaining and Licensing an AMPP Megafunction in AN 343: OpenCore Evaluation of AMPP Megafunctions.
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If your design uses a mix of VHDL and Verilog HDL that references Altera simulation models, you should use the Altera Verilog HDL models with the Verilog HDL portion of your design and the Altera VHDL models with the VHDL portion of your design. You do this by specifying, mapping, and searching the Verilog HDL and VHDL files of your simulator. For instructions about how to compile models into logical libraries and how to map logical libraries to physical libraries, refer to your EDA simulator documentation.
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Simulating Altera IP Cores Manually You can also simulate Altera IP cores in your third-party simulator by adding its variation file to your simulation project. If the IP core requires IPFS model files, do not add the IP core variation file to your simulation project. Instead, add its IPFS model files (either Verilog HDL or VHDL) to your simulation project. If your IP core generates any other type of simulation models, as described in IP Variant Directory Structure on page 115, you must compile all of the IP simulation files (including the appropriate Altera simulation model library files) along with your design and testbench. To properly compile, load, and simulate the IP cores, you must first compile the libraries in your simulation tool. h For a list of library files, refer to Altera Functional Simulation Libraries in Quartus II Help.
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Chapter 1: Simulating Altera Designs Simulating Qsys and SOPC Builder System Designs
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Changes Removed link to Quartus II Help in Simulation Library Compiler on page 18 Added information about encrypted Altera simulation model files in Simulating Altera IP Cores on page 114 Added Perform Functional Simulation with IP Cores Based on _hw.tcl on page 117 Perform Functional Simulation with IP Cores not Based on hw.tcl on page 120 Stratix V Simulation Model Libraries on page 121 Added note to Figure 11 on page 12 Added new section Converting Block Design Files (.bdf) to HDL Format (.v/.vhd) on page 14 Updated information in Simulation Netlist Files on page 16 Updated information in Generating Gate-Level Timing Simulation Netlist Files on page 16 Updated information in Generating Post-Synthesis Simulation Netlist Files on page 16 Removed information from Generating Timing Simulation Netlist Files with Different Timing Models on page 17 Removed information from Running the Simulation Library Compiler Through the GUI on page 18 and linked to Quartus II Help Updated Table 11 on page 19 Updated Simulating Qsys and SOPC Builder System Designs on page 120 Title changed from Simulating Designs with EDA Tools Merged content from Simulating Altera IP in Third-Party Simulation Tools chapter to Simulating Altera IP Cores on page 114 Added new section IP Variant Directory Structure on page 115 Added new section Simulating Qsys and SOPC Builder System Designs on page 121 Added information about simulating designs with Stratix V devices Updated chapter to new template Linked to Quartus II Help where appropriate Removed Referenced Documents section Removed Creating Testbench Files Added VCS and QuestaSim as third-party simulation tools Updated Running the EDA Simulation Library Compiler Through the GUI on page 118 Updated Setting Up the EDA Simulator Execution Path on page 119 Updated Configuring NativeLink Settings on page 120 Updated Setting Up Testbench Files Using the NativeLink Feature on page 122
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11.1.0
May 2011
11.0.0
December 2010
10.1.0
July 2010
10.0.0
November 2009
9.1.0
Initial release
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f For previous versions of the Quartus II Handbook, refer to the Quartus II Handbook Archive. f Take an online survey to provide feedback about this handbook chapter.