S3C2410 RISC MICROPROCESSOR S3C2410X DEVELOPER NOTICE

3C2410X DEVELOPER NOTICE

February 04, 2003
This document includes the following contents
- Revision points of S3C2410X Engineering Sample (ES)
- Known problem list
- S/W work-around
- Notes for the developers

REVISION POINTS FOR S3C2410X

No Problem ES 1 ES 2 ES 3 ES4 ES 5
1 Although nBATT_FLT pin is asserted, RTC_ALARM wake-up
- Fixed / /
can’t be masked.
2 If USB device is plugged in, the USB host receives false USB
signalling and USB host will malfunction. It’s because one of the - Fixed / /
USB device port signal is routed to the USB host.
3 In the Power_OFF mode, the GPHDAT[10:9] output pin level will
be GPHDAT[8] value instead GPHDAT[10:9] value if - Fixed / /
GPHDAT[10:9] is configured as an output port.
4 The nWAIT pin is used for NAND flash RnB signal. If the RnB
holds nWAIT pin for a long time, the variable length I/O
operation of other external peripherals will be postponed until - Fixed / /
the RnB signal is released.
So, NCON0 pin has been dedicated for R/nB signal.
5 The voltage margin of ADC & Touch Screen Panel is improved - - Fixed /
6 IIS slave mode is not working. (The IISSCLK signal isn’t
connected to the internal logic in slave mode. The IIS Master - - - Fixed
mode has no problem.)
7 The ball size of the package is changed from 0.4mm to 0.45mm. - Changed
8 The size of IIS Rx FIFO had been 4-byte really though it has 64-
byte memory. So, if IIS Rx FIFO gets more than 1 sample data,
the IIS Rx FIFO will stall. This problem may appear sometimes
- - - - Fixed
when the internal AHB bus is busy because of insufficiency of
the bus bandwidth. The improved Rx FIFO will receive up to 16
samples and will not stall even if the FIFO is overflowed

Package Marking Information

ES 1 (Rev 0) : K5Z3Nxxx , K5Z3Mxxx (First of April)

ES 2 (Rev 1) : K8Z5Fxxx , K8Z5Gxxx (First of July)
ES 3 (Rev 4) : K8Z50xxx , K8Z5Zxxx (First of August)

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ES 4 (Rev 5) : KA320AA , KA321A (End of September)

ES 5 (Rev 9) : KEZ1GB (On the 13th of January in 2003)

( Rev x ) : manufacturing management revision number(internal use only)

KNOWN PROBLEMS

No Problem Solution
1 NAND flash controller can’t be accessed by DMA. Instead of DMA, use LDM/STM
Instructions like our boot loader
example code.
2 In a MDS, such as Multi-ICE, some of the LCD controller registers The LCD controller register will be
may be displayed incorrectly in the memory view window of the ARM displayed correctly unless the
debugger. memory view window is used.
Instead, use ‘pr’ command in the
debugger console window.
3 SPI slave Rx mode with format B
If the SPI slave Rx mode is activated and SPI format is set to format B, then SPI operation will be failed:
The READY signal, one of internal signals, becomes high before the SPI_CNT reaches 0. Therefore, in
DMA mode, DATA_READ signal is generated before the last data is latched.

Guide
1) DMA mode: This mode cannot be used at SPI slave Rx mode with format B.
2) Polling mode: DATA_READ signal should be delayed by 1phase of SPICLK at SPI slave Rx mode with
format B.
3) Interrupt mode: DATA_READ signal should be delayed 1phase of SPICLK at SPI slave Rx mode with
format B.

SPI Data Receive Function Error (Slave/Receive/format B mode)

SPI_CNT Value
7 6 5 4 3 2 1 0
SPICLK
Data latch

READY (Internal)
Data read

DATA_READ(Internal)

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4 SDI data/ busy timer register

SDI data/ busy timer register has 16-bit counter. In case of 25MHz operation, the countable maximum time
is 2.6ms (40ns * 0x10000). But, some cards have very long access time (TAAC), their TAAC are up to
100ms. In this case the SDI generates data timeout error state. To solve this problem follow the below flow
chart.

Start

Read
(multil or single block)

Yes 25MHz
Is timeout occurs? 25MHz or 600KHz ? Send stop command

No

Send stop command if Change SDI clock to

600KHz
multi block 600KHz

Retry

Change SDI clock to

Real-timeout error
25MHz if 600KHz

Return Return error

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S/W WORK-AROUNDS

No Work-Around Items
1 The DMA auto-reload is occurred only when the DMA request is issued after the DMA counter reaches 0.
So, the following code should be used in the DMA done interrupt handler before setting the DMA source
address, destination address and counter register for the next auto-reload. This code will wait until the first
DMA request is issued and the previous auto-reload value is loaded.

while((rDSTATn&0xfffff)==0);
2 After 'wake-up' from the Power_OFF mode by RTC_ALARM, the RTC source pending bit of the SRCPND
register is not set. So, the ALARM date has to be checked after the wake-up from Power_OFF mode.

NOTES FOR DEVELOPERS

1. RTC X-tal Load Capacitance Has To Be Reduced.

The RTC load capacitor is the two 22pF capacitors on the each terminal of the X-tal. It has been 22pF up to
now. We have known that 22pF is too big to get exact 32768Hz. If the load capacitance is bigger than needed, the
RTC clock frequency will be lower than 32768Hz(For example,32766Hz).

This capacitance value has to be adjusted to the optimal value for each X-tal. By our experiment, some X-tal
needs 6pF but the other X-tal needs 12pF. It depends on the maker of X-tal. Also, the parasitic capacitance may
be considered.

2. SmartMediaCard(SMC) Removal/Insertion On The SMDK2410 Board.

In SMDK2410 board, SMC card isn’t allowed to remove/insert the card during the power-on.

If you want to eject/insert the SMC card during the power-on, a buffer logic has to be implemented in order to
protect the system bus from the bus interference by the SMC card removal/insertion.

3. The PCB Artwork guide for S3C2410X

- The recommended land open size is 0.39 ~ 0.41mm diameter on the bottom of the BGA.
(Pattern 0.1mm, Space 0.12mm, Escape Via pad 0.4mm/Drill 0.2mm)

- All the SDRAM signals(nSCS,nSRAS,nSCAS,nWE,DQMn,SCKE,SCLK,BAn,ADDR,DATA) have to be similar

length. By our lab test result, this PCB routing method has enhanced the SDRAM I/O voltage margin up to 2.5V

- SCLK0,SCLK1 are exactly same signal. Although there are only two 16-bit SDRAM for 32-bit configuration, it’s
recommend to use all SCLKn signal. (For example, SCLK0 for one SDRAM, SCLK1 for the other SDRAM)

- Power signal (GND, 1.8V, 3.3V) should be reinforced as soon as possible. Also, the bypass capacitor has to be
nearest to the power pads.

- All the memory signals are simulated at 35pF load. So, all capacitance including the board parasitic should be
smaller than 35pF. The parasitic capacitance of the S3C2410 is typically 5pF.

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4. Cautions in clearing the INTPND register

The INTPND register is cleared to ‘0’ by writing ‘1’. If the INTPND bit, which has ‘1’, is cleared by ‘0’, the INTPND
register & INTOFFSET register may have unexpected value in some case.

So, you never write ‘0’ on the INTPND bit having ‘1’. The convenient method to clear the INTPND register is
writing the INTPND register value on the INTPND register. (In even our example code, this guide hasn’t been
applied yet.)

5. MDS (JTAG debugger) Compatibility Problem

If you have problem in MDS connection, please remove the 470-ohm resistor(R 98) between nTRST and
nRESET. This resister disturbs some MDS equipment. Multi-ICE and Open-ICE has been working well in spite of
this resistor. However, if you are not using MDS, there should be this resister between nTRST and nRESET.

So, we recommend the resistor being replaced with a jumper switch. If JTAG MDS is used, open the jumper
switch. If not, close the jumper switch, which is very important.

6. IIC data hold time

The IIC data hold time(tSDAH) is minimum 0ns.

(IIC data hold time is minimum 0ns for standard/fast bus mode in IIC specification v2.1.)
Please check the data hold time of your IIC device if it's 0 nS or not.
The IIC controller supports only IIC bus device(standard/fast bus mode), not C bus device.

7. Simultaneous IIS Audio Record and IIS Audio Play

To do the IIS_play and the IIS_record simultaneously, Please refer to the follow chart in Fig 7-1 & 7-2. The IIS
controller is always turned on. The audio play is controlled by DMA. The audio record should be controlled by
DMA and IIS control register because IIS_Rx_FIFO control register should not to be Rx_FIFO_FULL state.

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IIS Function START

rDMASKTRIG1 = 0x4; //Dma1(record) Stop

rDMASKTRIG2 = 0x4; //Dma2(play) Stop
rIISCON=0x32; //TxDMAReqEn,RxDMAReqEn,IISPrescalerEn
rIISMOD=0xc9; //Master,Tx&Rx,IisFormat,16bit,256fs,32fs
rIISPSR=0x63; //PreScalerA=PCLK/4,PreScalerB=PCLK/4
rIISFCON=0xe00; //TxFifo=DMA,RxFifo=DMA,TxFifoEn,RxFifoDis
rIISCON||=0x1; //IIS Enable
DMA1,2 done interrupt handler is initailzed.
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Play/Rec.
Start/Stop
Audio Play Audio Play Audio Rec. Audio Rec.
Start Stop Stop Start

stopPlay=FALSE; stopRec=TRUE
stopPlay = stopRec =
rDISRC2 =pPlayBuf[m++]; rDISRC1 = (U32)IISFIFO;
TRUE; TRUE;
rDISRCC2 =0x0; //Src=AHB,Increment rDISRCC1 = 0x3; //Src=APB,Fixed
rDIDST2 = (U32)IISFIFO; rDIDST1 = pRecBuf[n++];
rDIDSTC2 = 0x3; //Dst=APB,Fixed; rDIDSTC1 = 0x0; //DSt=AHB,Increment
rDCON2 = 0xa0900000|PlayBufSize; rDCON1 = 0xa2900000|RecBufSize;
//Handshake,PCLK,IntEn,Unit,single, //Handshake,PCLK,IntEn,unit,single,
I2SSDO,HwReq,AutoReload,HalfWord I2SSDI,HwReq,AutoReload,Halfword
rDMASKTRIG2 = 0x2; //DMA2En rDMASKTRIG1 = 0x2; //DMA1En

rIISFCON|=(1<<12); //RxFifoEn
while ((rDSTAT2&0xFFFFF) == 0);
rIISCON|=(1<<4); //RxDmaSvcReqEn

rDISRC2 = pPlayBuf[m++] while ((rDSTAT1&0xFFFFF) == 0);

rDIDST1 = pRecBuf[n++]

Fig. 7-1. Main Functions For The Simultaneous IIS Audio Record and IIS Audio Play

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DMA2 Interrupt Handler DMA1 Interrupt Handler

START START

ClearPending(BIT_DMA2); ClearPending(BIT_DMA1);

Y Y
stopPlay==TRUE stopRec==TRUE

rIISCON&=~(1<<4); //RxDmaSvcReqDis
rDMASKTRIG2= (1<<2);
N rIISFCON&=~(1<<12); //RxFifoDis N
//StopDMA2
rDMASKTRIG1= (1<<2);

while
while (rDMASKTRIG1&0x2);
(rDMASKTRIG2&0x2);

while ((rDSTAT2&0xFFFFF)==0); while ((rDSTAT1&0xFFFFF)==0);

rDISRC2 = pPlayBuf[m++] rDIDST1 = pRecBuf[n++]

DMA2 Interrupt Handler END DMA1 Interrupt Handler END

Fig. 7-2. ISR Handlers For The Simultaneous IIS Audio Record and IIS Audio Play