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A Gain-Controllable Wide-Band Low-Noise Amplifier in Low-Cost 0.8-m Si BiCMOS Technology

Fabrice Seguin, Balwant Godara, Frederic Alicalapa, and Alain Fabre, Senior Member, IEEE
AbstractA low-noise amplifier (LNA) implemented in a low-cost Si-BiCMOS 0.8- m process is presented. It utilizes current conveyors as building blocks. The principle and design methodology are presented, followed by results obtained from simulations. A brief technology and measurement technique description is then made, leading up to the measurement results obtained. The performance is compared with some other LNA realizations. The potentialities of the LNA are finally touched upon, with particular regard to future communications systems. The gain of the LNA is controllable, in the range of 020 dB, by varying the dc bias current. Negative decibel gains can also be obtained, making it an attenuator circuit. Using a 1.5 V supply, and at a measured gain of 14 dB, the LNA has measured 3 dB bandwidth of dc to 1.9 GHz, IN , 11 dB, and a simulated noise figure dB, input 1dB dBm, and consumes only 3.8 mA. A judicious tradeoff between the decibel gain and bandwidth yields 3 dB bandwidths of up to 5.5 GHz, while in the 10-dB cutoff specified for ultra-wide-band (UWB) systems, passbands greater than 10 GHz are enabled. The LNA occupies 0.24 mm2 of chip area, including pads. The prospective applications range from current global system for mobile communications, code division multiple access, and multiband systems, to the upcoming UWB.

=33

= 50

= 21 = 33

Fig. 1. Electrical equivalent representation of CCCII.

Index TermsBiCMOS, controlled current conveyors (CCCs), gain control, low-noise amplifier (LNA), multiband receivers, silicon, ultra-wide-band (UWB).

), and ( in parallel with ), for ports parallel with , , and , respectively, and is shown in Fig. 1. The nature and values of these impedances, principally , depend on the technology of fabrication and the polarization of the circuit [10]. This latter dependence gives rise current to the concept of a controlled current conveyor (CCCII) [2], [4], [10], with the relationship matrix given by

I. INTRODUCTION A. Current Conveyors (CCs)

(1)

Cs [1] are used as building blocks for analog circuits for implementing functions like filters [2], inductances [3], gyrators [4], mode [5] and impedance converters [6], oscillators [7], and operational amplifiers [4]. CCs are active devices comprising three ports, designated , , and [8]. The nonideal operation of the second-generation current conveyor (CCII) [9] results in parasitic elements at each ( in series with ), ( in port, represented as
Manuscript received March 11, 2003; revised June 27, 2003. F. Seguin is with the Department of Electronics, Ecole Nationale Suprieure des Tlcommunications, Bretagne, Brest 29238, France (e-mail: fabrice.seguin@enst-bretagne.fr). B. Godara, F. Alicalapa, and A. Fabre are with the Laboratoire dEtude de lIntgration des Composants et Systmes ElectroniquesEcole Nationale Superieure dElectronique, dInformatique et de Radiocommunications de Bordeaux, Groupe Telecommunications, Circuits et Systemes, Unit Mixte de Recherche Centre National de la Recherche Scientifique 5818, Universite Bordeaux I, Talence 33402, France (e-mail: godara@ ixl.u-bordeaux.fr; alica@ ixl.u-bordeaux.fr; fabre@enseirb.fr). Digital Object Identifier 10.1109/TMTT.2003.821265

and represent the conductance of ports and Here, , respectively; while and are the unity current and voltage transfers. The CCCII acts as a current follower (beand ), voltage follower (between and ), tween ports , in and transconductor (between and ) [5]. Resistance particular, is important, being instrumental in defining the relationship between the ports and, thereby, the applications to which the CCCII can be adapted [2], [4], [10]. B. CCs for Voltage AmplificationPrinciple The CCCII can be used to design a gain-variable voltage amplifier [11], [12], the gain of which can be controlled by . Two CCCII blocks [11], [13], [14] are connected, as shown in Fig. 2. The two blocks are designated CCCII1 and CCCII2; their respective ports bear the same subscripts, as do their polarization is provided at . Ports and currents. The input signal are connected to each other; and the output signal is tapped at this common connection. Assuming and

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Fig. 2.

Connection of two CCCII blocks to provide voltage amplification.

to be purely resistive in nature, with and , into , which is given by first converted by

is
Fig. 3. Class-A CCCII base schema.

(2) is copied to as (because of currentfollower passes to function of the CCCII between and [9]). , where it is converted into a voltage signal by . The is given by resulting voltage signal (3) The intrinsic resistances being inversely proportional to in [14] and polarization currents (e.g., in [15]), the gain of the amplifier is given by (4) enables higher gains at lower The inverse relation of to currents and, thus, at lower power consumption. C. Plan of this Paper This paper describes the implementation of a low-noise amplifier (LNA) using the above principle. The LNA was simulated using a Cadence 0.8- m Si-BiCMOS SpectreS simulator [16]. We start with a brief description of the process followed in designing the LNA. We then present the simulation results obtained. The LNA was implemented in a low-cost industrial 0.8- m Si-BiCMOS process from Austria Mikro System (AMS), Schloss Premsttten, Austria [16]. A brief overview of the measurement procedure is followed by the results obtained from these measurements. Finally, we present a comparison with three other LNA structures, putting our design into the context of current and future communications systems. II. CIRCUIT DESIGN Fig. 3 gives the base schematic of a class-A CCCII [14] using n-p-n transistors to convey the signal. Two of these blocks, when connected as shown in Fig. 2, yield the amplifier topology of Fig. 4. Some of the redundant components can be eliminated by departing from the conventional CCCII blocks and altering signal paths of Fig. 4, allowing better performance to be achieved. To k for [14]), we reduce the input impedance (typical

Fig. 4. Topology of voltage amplifier using two base class-A CCCII blocks.

supply the input signal at (typical for [14]) instead of . This allows us to eliminate transistor (Fig. 4) and its associated current sources. The final schema of the amplifier is shown in Fig. 5(a). Note that the configuration contains the minimum number of n-p-n transistors possible, thereby allowing for higher bandwidths to be obtained, and improving the noise performance. After substituting the current sources with CMOS transistors, we arrive at the final LNA design, given in Fig. 5(b). Fig. 6 presents a small-signal equivalent of the amplifier. represents the total capacitance resulting from a Here, , , and of , , parallel connection of , respectively, from Fig. 5(b). The input impedance and of the amplifier is given by a series combination of and . (550 A), can be obtained At a particular value of around 50 and we, thus, maintain this polarization current fixed at this value. The output impedance is given by a parallel and . By assuming base resistances of combination of and low enough not to show any inductive element, we obtain an expression for the gain

(5)

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(a)

(b) Fig. 5. Final LNA. (a) Schematic representation. (b) Implementation.

Fig. 6. Electrical equivalent circuit of the LNA.

where m and m are the transconductances of and . This expression is first order, and, theoretically, gives no rebound. This is duly illustrated by Fig. 7, which presents the A, theoretical gain profile of the LNA with A, and V. III. SIMULATIONS This amplifier was simulated using the Cadence SpectreS 0.8- m Si BiCMOS simulator from AMS [16]. The transition

50 A, and V

Fig. 7.

Theoretical gain profile of the LNA with 1:5 V.

06

= 550 A, I

of the n-p-n transistors in this technology is frequency 12 GHz. The sizes and models of transistors were monitored, and finally settled upon a set that gives optimum performance. , The schematic uses the following sizes and models: , and have five base contacts, thus reducing to is twice the size of and . a fifth, and the size of The CMOS transistors have width-by-length ratios 30 m/3

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TABLE I SUMMARY OF SIMULATION RESULTS WITH I = 550 A, V AND Signal Frequency = 1 GHz

= 61:5 V,

Fig. 9. Measured gain profiles for various = 1:5 V. V

with

= 550 A and

Fig. 8.

Microphotograph of LNA.

Fig. 10. Gain control and bandwidth variation with I V = 1:5 V.

,I

= 550 A, and

m for to , 60 m/2.2 m for and , and and . The design utilizes three n-p-n 57 m/2.2 m for and ten CMOS transistors, the minimum number possible while was kept still maintaining the basic connectivity of Fig. 2. constant at 550 A, as explained earlier, and the bias voltage V. The performance obtained was also fixed at from the various simulations is summarized in Table I. The noise figure of the LNA is obtained from the simulations as 3.3 dB. IV. CIRCUIT AND MEASUREMENT TECHNIQUES The LNA was fabricated in the low-cost 0.8- m Si-BiCMOS process from AMS [16]. Fig. 8 presents a microphotograph of the chip. The total size of the circuit is 0.24 mm with test pads, and 0.013 mm without. Each pad occupies an area of 100 m 100 m, and the amplifier core measures 120 m 110 m. The circuit was designed to facilitate on-chip measurement with a wafer probe, thus eliminating any parasitic inductive elements resulting from bonding. In addition, the test pads were placed as near as possible to the circuit in order to reduce any parasitic impedances [17]. The measurement technique utilized was the test-under-points, which allows direct on-chip measurements [18]. This makes the measures more true-to-system because it takes a fuller account of real operating conditions, and includes the effects of the bonding and pads. It uses micropoints or probes positioned on the chip using micromanipulators. DC

micropoints, which allow static measures, while assuring that the polarization of circuit is kept constant, are present m), and ac in the form of fine needles (of diameter micropoints, for high-frequency measures, are placed as groundsignalground (GSG) probethree probes separated from one another by 150 m. The measurement bank [19] ) consists of the parametric analyzer HP4155 (for varying and the network analyzer HP8510 (allows signals ranging from 45 MHz to 27 GHz). The static measures were made using the dc points and HP4155, and allowed the determination of impedances, and current and voltage transfers. Dynamic measures (or in-frequency measures) were made using the ac probes and HP8510, with an input signal of 30 dBm, and gave the scattering-parameter matrix. V. MEASUREMENT RESULTS The gain profiles are presented in Fig. 9 for various values of . These profiles show stable gains over large frequencies, while also exhibiting negligible rebounds. The gain control, shown in Fig. 10, exhibits excellent conformity with theoretical values. is varied, the 3 dB bandwidth ranges between dc When to 1.0 GHz and dc to 5.5 GHz (Fig. 10). Another critical parameter for the performance of an LNA is . Fig. 11 presents the coefficient of reflection at the entry the frequency variation of measured with A, A, and V. At a frequency of 1 GHz,

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Fig. 11. and V

0 61:5 V.

Frequency variation of

with I

= 550 A, I

= 100 A,

COMPARISON

OF

TABLE II MEASURED PERFORMANCE WITH THREE OTHER LNA STRUCTURES

has a value of 21 dB, and it remains below 10 dB for frequencies up to 5 GHz. The noise figure could not be measured because of sensitivity constraints of the HP6530E spectral analyzer (which is unable to detect noise lower than 20 nV Hz) and, hence, the simulated values are taken: 3.30 dB. These simulations showed that over 85% of this noise is contributed by a single component, i.e., . In addition, the number of components the input transistor in the signal chain is low: only three n-p-n transistors. There is a total absence of any other active components (capacitors, inductors, resistors, etc.), and the noise introduced to the circuit as a result of spurious parasitic elements is expected to be minimal. Thus, the simulated value is a good indicator of the actual performance. The quality of the output signal (in terms of total harmonic distortion (THD) and offset voltage) remains essentially the same as that obtained for the simulations, as does the current consumption (Table II). The measurement results show excellent conformity with those obtained from simulations. The LNA has a stable operation with respect to temperature, and shows a C, and drop of only 1 dB in gain in the range 60 C to a drop in the passbands of 0.1 GHz. VI. COMPARISONS AND POTENTIAL APPLICATIONS Table II provides a comparison of the LNA designed here with three other realizations, placing it in the context of industrial and research standards. These three LNAs have been chosen to highlight specific points: the first [20] is designed specifically for third- and fourth-generation wide-band code-division multiple-access (WCDMA) systems, thus giving a reference for the performance of our LNA for future wide-band mobile systems,

the second [21] is a commercially available global system for mobile communications (GSM) 900 LNA, and allows comparison with industrially accepted standards, the third [22] uses active elements (an active inductance) other than the transistors, while our LNA obtains similar or better performance without the use of additional elements. The gain control is inferior in range to only [20]. The present structure allows negative gains to be obtained (e.g., at mA, A, V, and Gain dB), thus expanding its field of application to attenuator circuits. At a nominal gain of 14 dB, the bandwidth obtained is the highest in spite of having utilized a technology with low transition frequency . For LNAs, the bandwidth expressed as a fraction of the transition frequency of the technology allows a direct comparison of the efficiency of the design. Here, bandto were obtained, whereas, widths ranging from . At a gain of for example, the LNA in [22] has only for this study and around 15 dB, the bandwidths are for [20]. The noise performance, indicated by the noise figure, is the lowest among the four. The linearity obtained ( dB dBm) is low, primarily because of the class-A function of CCCII blocks, but still within acceptable limits in comparison with the others. The LNA consumes the lowest current for comparable gains, while working at similar bias voltages. BiCMOS technology, though among the oldest, and of limited performance, still has low fabrication cost to recommend itself, and cost is an important criterion in todays competitive wireless market. Further, attempts at single-chip RF front-ends [23] and receiver systems that are being made are mostly in BiCMOS or CMOS because of the versatility these technologies show in permitting the design of components ranging from RF filters and switches to amplifiers. The LNA forms an integral part of any single-chip system and this provides another advantage of using BiCMOS for LNAs. In most receiver systems, an LNA is placed immediately after the antenna-switch system. The antenna has an output impedance of 50 , and to reduce the impedance mismatch (and, thus, losses), the input impedance of the LNA should be 50 and constant. The output impedance, on the other hand, is not as critical because the LNA is placed before the RF filter, the input of which directly charges the LNA output to high impedance. The wide range of performance, without any change in topology or placement, validate the use of this new amplifier as an LNA for multiband receiver systems [24] and software radio [25]. The neo-nascent ultra-wide-band (UWB) systems for commercial applications [26], [27] can form another excellent field of application, especially in the 02-GHz band because of the high measured bandwidths. As mentioned in Section V, the LNA designed here has an excellent thermal stability: in the temperature range of 60 C to 60 C, the gain drops by 1 dB, and the bandwidth reduces by 0.1 GHz. The superiority of these figures is evident upon comparison with the three other LNAs: for the LNA in [20], in the temperature range from 0 C to 85 C, the gain profiles deviate by 3 dB, for the LNA in [21], in the temperature range of 40 C to 85 C, these profiles have a variation of 2 dB, and, finally, for the LNA in [22], in the temperature range from

SEGUIN et al.: GAIN-CONTROLLABLE WIDE-BAND LNA IN LOW-COST 0.8- m Si BiCMOS TECHNOLOGY

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50 C to 80 C, the gain has a variation of 1 dB, while the passband reduces from 1.6 to 0.95 GHz, which is a drop of 650 MHz.

VII. CONCLUSIONS A new single-ended LNA, simulated and then implemented in a low-cost 0.8- m Si-BiCMOS technology, has been presented. The LNA uses only three n-p-n transistors for conveying the signal, has no other active components, requires no additional external components, and occupies only 0.013 mm of chip area. The measurement results obtained convincingly demonstrate its acceptability for various current mobile communications receivers and a strong potentiality in future systems by dint of the versatility of its performance. The low number of components, along with the fact that the 0.8- m BiCMOS process is among the most inexpensive available industrially, further increases the advantageous position of the amplifier designed here. A comparative analysis vis--vis other LNAs has yielded encouraging results for GSM-900, WCDMA, and upcoming UWB systems.

[17] J. L. Carbonero, Dveloppement des mthodes de mesures en hyperfrquences sur tranches de silicium et application la caractrization des technologies CMOS et BiCMOS sub-microniques, Thse de doctorat (in French), Inst. Nat. Polytech. Grenoble, Grenoble, France, 1996. [18] F. Seguin, Etude et ralization de circuits convoyeurs de courant de seconde gnration en technologie BiCMOS. Application lamplification RF rglable, Thse de doctorat (in French), Dept. Electron., Univ. Bordeaux I, Talence, France, 2001. [19] Suss Pa200-II, Semi-Automatic Prober User Manual, Suss MicroTec, Dresden, Germany, 1995. [20] S. Otaka, G. Takemura, and H. Tanimoto, A low power low noise accurate linear in dB variable gain amplifier with 500 MHz bandwidth, IEEE J. Solid-State Circuits, vol. 35, pp. 19421948, Dec. 2000. [21] (1997) MAX2630 VHF-to-microwave, 3 V, general-purpose amplifiers. Maxim Integrated Products, Sunnyvale, CA. [Online]. Available: http://www.maxim-ic.com [22] F. Carreto-Castro, J. Silva-Martinez, and R. Murphy-Arteaga, RF lownoise amplifiers in BiCMOS technologies, IEEE Trans. Circuits Syst. II, vol. 46, pp. 974977, July 1999. [23] K. Yamamoto, T. Heima, A. Furukawa, M. Ono, Y. Hashizume, H. Komurasaki, S. Maeda, H. Sato, and N. Kato, A 2.4-GHz-band 1.8-V operation single-chip Si-CMOS T/R-MMIC front-end with a low insertion loss switch, IEEE J. Solid-State Circuits, vol. 36, pp. 11861197, Aug. 2001. [24] B. Razavi, A 900-MHz/1.8-GHz CMOS transmitter for dual-band applications, in VLSI Circuits Symp. Tech. Dig., June 1113, 1998, pp. 128131. [25] B. Bing and N. Jayant, A cell-phone for all standards, IEEE Spectr., pp. 3439, May 2002. [26] R. J. Fontana. (2000) Recent applications of ultra wideband radar and communications systems. [Online]. Available: http://www.multispectral.com/pdf/Advances_Comm.pdf [27] K. Greer, UWB faces its toughest battle, in Wireless Eur., UWB for commercial applications, Jan. 2003, p. 17.

REFERENCES
[1] K. C. Smith and A. S. Sedra, The current conveyor, a new circuit building block, Proc. IEEE, vol. 56, pp. 13681369, Aug. 1968. [2] C. Toumazou, F. J. Lidgey, and D. G. Haigh, Analog IC Design: The Current Mode Approach. London, U.K.: Peregrinus, 1990. [3] A. Fabre, O. Saaid, F. Weist, and C. Boucheron, Low power current mode second order bandpass IF filter, IEEE Trans. Circuits Syst. II, vol. 44, pp. 105765, June 1997. [4] A. Fabre, Insensitive voltage mode and current mode filters from commercially available transimpedance operational amplifiers, Proc. Inst. Elect. Eng., vol. 140, pp. 319321, Oct. 1993. [5] A. Fabre and O. Saaid, Phase compensation of ideal inductances based second-generation current conveyors, Analog Integrated Circuits and Signal Processing, vol. 24, pp. 153162, 2000. [6] C. Toumazou and F. J. Lidgey, Universal active filter using current conveyors, Electron. Lett., vol. 21, pp. 640642, 1985. [7] P. A. Martinez, S. Celma, and I. Gutierez, Wien type oscillator using CCCII , Analog Integrated Circuits and Signal Processing, vol. 7, no. 2, pp. 139149, 1995. [8] K. C. Smith and A. S. Sedra, A second generation current conveyor, and its applications, IEEE Trans. Circuits Theory, vol. CT-17, pp. 132134, Feb. 1970. [9] A. S. Sedra, The current conveyor: History and progress, in IEEE Int. Circuits and Systems Symp., 1989, pp. 15671571. [10] A. Fabre, O. Saaid, F. Wiest, and C. Boucheron, High-frequency, high Q BiCMOS current mode bandpass filter and mobile communications applications, IEEE J. Solid-State Circuits, vol. 33, pp. 614625, Apr. 1998. [11] , High-frequency applications based on a new current controlled conveyor, IEEE Trans. Circuits Syst. I, vol. 43, pp. 8291, Feb. 1996. [12] B. Wilson, Universal conveyor instrumentation amplifier, Electron. Lett., vol. 25, pp. 470471, 1989. [13] O. Oliaei and J. Porte, Compound current conveyor (CCII and CCII ), Electron. Lett., vol. 33, pp. 253254, Feb. 1997. [14] F. Seguin and A. Fabre, 2-GHz controlled current conveyor in standard 0.8 m BiCMOS technology, Electron. Lett., vol. 37, no. 6, pp. 329330, 2001. [15] , New second generation current conveyor with reduced parasitic resistance and bandpass filter application, IEEE Trans. Circuits Syst. I, vol. 48, pp. 781785, June 2001. [16] Austria Mikro Syst., Schloss Premsttten, Austria, A-8141 Unterprensttten, 1998.

Fabrice Seguin received the Ph.D. degree from the Universite Bordeaux 1, Talence, France, in 2001. His doctoral research concerned the current mode design of high-speed CCs and applications. In 2001, he joined the Ecole Nationale Superieure des Telecommunications (ENST) de Bretagne, Brest, France, as a Lecturer. His research at Traitement Algorithmique et Matriel de la Communication, de iInformation et de la Connaissance (TAMCIC), the laboratory of ENST, is focused on error-correcting codes and the analog implementation of turbo decoders.

Balwant Godara was born in Rajasthan, India, in March 1980. He received the Bachelor of Technology degree in electrical engineering from the Indian Institute of Technology, Delhi, India, in 2002, and is currently working toward the Ph.D. degree at the Universite Bordeaux 1, Talence, France. His doctoral research concerns RF subsystems for mobile communications. He is involved with design issues of LNAs, power amplifiers, RF switches, etc.

Frederic Alicalapa was born in Saint Pierre (Reunion Island), France, in June 1974. He received the Diplome dEtude Approfondie degree in electronics engineering from the Universite Bordeaux 1, Talence, France, in 1997, and is currently working toward the Ph.D. degree at the Universite Bordeaux 1. His doctoral research concerns analog electronics, tunable filters, and tunable active inductances for RF circuits. Following three years with the Universite de la Reunion, he joined the Universite Bordeaux 1, Talence, France.

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Alain Fabre (M94SM95) received the M.S. degree in electronics and Ph.D. (These de 3 eme cycle) in physics from the Universite Bordeaux, Talence, France, in 1972 and 1974, respectively, and the Post-Doctoral Thesis (These detat) degree in physics from the University of Perpignan, Perpignan, France, in 1987. His doctoral research concerned the development of a tunable spectrometer for the 1218-GHz range. From 1974 to 1987, he was an Assistant Professor in electronics in a cooperation program with the University of Oran, Oran, Algeria, where, in 1983, he began research concerning the exploitation of mixed translinear cells in the design of analog circuits working in the current mode. In September 1987, he joined the Ecole Centrale Paris, Paris, France, as an Assistant Professor of electronics, where he taught graduate and undergraduate courses. From 1988 to 1995, he was the Head of the Analog Integrated Circuit (IC) Design Group (COCAR), Laboratoire dElectronique et de Physique Appliquee, Ecole Centrale Paris, Paris, France. In 1991, he was a Visiting Researcher with the Ecole Polytechnique de Montreal, Montreal, QC, Canada. Since September 1995, he has been a Full Professor of electronics with the Ecole Nationale Superieure dElectronique, dInformatique et de Radiocommunications de Bordeaux (ENSEIRB), Talence, France, where he currently heads the High Speed Analog IC Design Team, Telecommunications Circuits and Systems (TCS) Group, Laboratoire dEtude de lIntgration des Composants et Systmes Electroniques (IXL), Unit Mixte de Recherche Centre National de la Recherche Scientifique 5818 (UMR CNRS 5818), Universite Bordeaux I, Talence, France. He authored two volumes of a book devoted to the practical aspects of electrical and electronic measures (Algiers, Algeria: O.P.U., 1983, 1984). He has authored or coauthored over 90 research papers published in scientific reviews or conference proceedings. He also coauthored a paper in the Encyclopedia of Electrical and Electronic Engineering (New York: Wiley, 1999). In 1995, he was a Guest Editor of the Analog Integrated Circuits and Signal Processing (AICSP) Journal for the March and May issues, which were devoted to current mode circuits. He holds one international patent. His current field of research principally concerns the various areas of design of BiCMOS RF analog circuits, analog RF filters, LNAs with adjustable gain, application-specific integrated circuits (ASICs), and current mode circuits, as well as theoretical tasks of translinear circuits. He is currently a member of International Steering Committees of numerous international electronics conferences.