Electric Power Systems Research 70 (2004) 6475

Novel unied power ow controller based on H-bridge modules

Byung-Moon Han a, , Seung-Taek Baek a , Hee-Joong Kim a , Jin-Boo Choo b , Gil-Su Jang c
a

Department of Electrical Engineering, College of Engineering, Myongji University, 38-2 Nam Dong, Yongin, Kyonggi Do 449 728, South Korea b Power System Stability Group, KEPRI, Daejeon 305-380, South Korea c Department of Electrical Engineering, Korea University, Seoul, South Korea Received 23 July 2003; received in revised form 24 October 2003; accepted 13 November 2003

Abstract This paper proposes a novel UPFC based on H-bridge modules, isolated through single-phase multi-winding transformers. The dynamic performance of proposed system was analyzed by simulations with EMTDC, assuming that the UPFC is connected with the 138-kV transmission line of one-machine-innite-bus power system. The proposed system can be directly connected to the transmission line without series injection transformers. It has exibility in expanding the operation voltage by increasing the number of H-bridge modules. 2004 Elsevier B.V. All rights reserved.
Keywords: STATCOM (static synchronous compensator); SSSC (static synchronous series compensator); UPFC (unied power ow controller); GTO (gate turn-off thyristor); PWM (pulse width modulation); THD (total harmonic distortion)

1. Introduction UPFC, based on GTO voltage source converters, was proposed as the most promising FACTS controller to improve the dynamic performance of power transmission system. The presently developed UPFC operates in a dc link voltage much lower than the operation voltage of power transmission system [1]. The reason for low dc link voltage is limitation on the maximum sustain voltage of high-power semiconductor switches. The maximum sustain voltage of commercially available GTO is about 6000 V. In order to increase the dc link voltage of UPFC, a technique called series connection of GTOs was developed. However, still there is limitation in the maximum allowable number of units. Step-down transformers are normally used for properly matching the converter operation voltage with the transmission voltage [2]. Multi-level converter was proposed to increase the system operation voltage avoiding series connection of switching devices [3]. But the multi-level converter has complexity in forming the output voltage and requires many back-connection diodes.

In order to improve this weak point, multi-bridge converter composed of ve H-bridge modules per phase was proposed by Peng for STATCOM application [4]. The system operation was veried through experimental works with a scaled model [5]. A commercial STATCOM of 75 MVar with chained H-bridge modules was developed and installed in National Grid Company in UK [6,7]. A multi-bridge converter composed of several H-bridge modules in cascaded connection was proposed in reference [8,9]. This system can operate without series injection transformers and has exibility in expanding the operation voltage by means of adding the number of modules. This paper proposes a novel UPFC based on H-bridge modules, isolated through single-phase multi-winding transformers. The operation of the proposed system was veried through simulations with EMTDC. The proposed system can be directly connected to the transmission line without series injection transformers.

2. Existing UPFC structure UPFC has two three-level converters connected in parallel through a common dc link capacitor as shown in Fig. 1. The three-level converter consists of four modules connected in parallel through phase-staggering transformers. The output voltage is built up in multi-pulse pattern to

Corresponding author. Tel.: +82-31-330-6366; fax: +82-31-321-0271. E-mail addresses: erichan@mju.ac.kr (B.-M. Han), jbchoo@kepri.re.kr (J.-B. Choo), gjang@korea.ac.kr (G.-S. Jang).

0378-7796/$ see front matter 2004 Elsevier B.V. All rights reserved. doi:10.1016/j.epsr.2003.11.012

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Fig. 1. System conguration of UPFC.

eliminate the low order harmonics. Each module consists of twelve GTO valves, each valve is composed of a number of series-connected GTOs. The conguration of UPFC can be considered as a compound system of STATCOM and SSSC sharing a common dc link capacitor. However, UPFC has direct control capability of the real and reactive powers through transmission line. The shunt converter has two functions. One function is to supply the real power required at the series converter through the dc link capacitor, which is critical to maintain the dc link voltage. Another function is to improve the voltage stability at the connection point by regulating the reactive current. The function of series converter is to control the real and reactive powers independently by means of injecting an ac voltage with arbitrary magnitude and phase. The fundamental frequency of injection voltage is the same as that of the

transmission system and its phase angle is determined by the converter phase angle pq . The converter phase angle can be adjusted within the range of 0 < pq < 2 . The magnitude of injection voltage Vpq can be adjusted by changing the level of dc link voltage with the shunt converter, and by changing the conduction angle of series converter. The computed injection voltage Vpq is added to the terminal voltage V and becomes V + Vpq .

3. Proposed UPFC structure This paper proposes a novel UPFC based on several pairs of H-bridge modules per phase as shown in Fig. 2. Each pair has two H-bridge modules connected in parallel through a common dc link capacitor. The H-bridge module in shunt part is connected through single-phase

Fig. 2. Conguration of novel UPFC.

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multi-winding transformer for isolation, while the H-bridge module in series part is directly inserted in the transmission line. The whole converter, its shunt part as well as its series part, must be insulated to the full insulation level of 138 kV line-to-line voltage. The proposed UPFC has bypass functions to remove the series converter from service during system faults. The bypass function is implemented by the operation of thyristor bypass switch and mechanical circuit breaker. The line over-current can be bypassed rst by the thyristor bypass switch and then by the mechanical circuit breaker. However, when the maximum fault current is lower than the maxi-

mum current rating of series converter switches, it is possible to attempt a bypass scheme using the converter control, instead of adding separate thyristor bypass switch. The proposed series converter has two possible bypassing ways by making a short circuit at the ac terminal. One is to turn on all the upper two switches in series part simultaneously and another is to turn on all the lower two switches in the series part simultaneously. Fig. 3 shows the converter structure and the switching pattern for the proposed UPFC. For the purpose of simulation convenience, the shunt and series parts are assumed to be composed of three H-bridge modules for each phase as

Fig. 3. Converter structure and switching pattern, (a) shunt part converter, (b) series part converter, (c) output voltage formation.

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shown in Fig. 3(a) and (b). The output voltage of one module and switching states can be explained using Fig. 3(c) and Table 1. The output of each module has three states +Vdc , 0, Vdc depending on states of switch S1S4. By changing the modulation index, the output voltage can be adjusted. Fig. 4 shows the principle of PWM gate-pulse generation for the proposed UPFC. Fig. 4(a) shows two carrier signals and the reference signal to generate the gate pulses for

Table 1 Switching pattern of multi-bridge converter V1A Vdc 0 Vdc Switching state S1, S4: on and S2, S3: off S1, S3: on and S2, S4: off S2, S4: on and S1, S3: off S2, S3: on and S1, S4: off Mode M1 M2 M3 M4

Fig. 4. Principle of gate pulse generation, (a) carrier and reference signal, (b) gate pulse generation scheme, (c) gate pulse and converter output.

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converter module INV1. The frequency of carrier T1, T2 is 360 Hz. Each of two carriers has 180 phase shift with each other. The reference signal Vref has maximum value of 0.9 in per unit and has a sinusoidal waveform of 60 Hz. Fig. 4(b) shows how to generate the gate pulses using the reference and carrier signals. Carrier T1 and T2 are compared with the reference signal. The gate pulses for switches S1 and S3 are inversed to make gate pulses for switches S2 and S4. Fig. 4(c) shows four gate pulses supplied to switch S1, S2, S3, and S4, and the output voltage of converter module

INV1 with the reference signal Vref . This gure indicates that each switch S1S4 is properly operated according to the switching state in Table 1. Fig. 5 shows the output voltage build-up of one phase and the harmonic analysis results of the output voltage. Fig. 5(a) shows the output voltage waveforms of each converter modules, V1, V2, V3, and the total output voltage of three converter modules, where the dc voltage Vdc is 1.0 per unit. As explained before, two carriers shown in Fig. 4(a) are used to generate gate pulses for building up the output voltage V1.

Fig. 5. Output voltage build-up and harmonic analysis, (a) converter output voltage, (b) harmonic spectrum V1 and VA, (c) THD of output voltage ((+): N = 3, (): N = 6, ( ): N = 12).

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Fig. 5. (Continued ).

Two sets of each two carriers, which are 180 phase shift each other, are needed to generate gate pulses for building up output voltage V2 and V3. These sets of carriers have 120 phase-shift with each other. Since each carrier has a frequency of 360 Hz and total output voltage VA has an

equivalent switching effect of N 360 Hz, where N is the number of modules. Fig. 5(b) shows the spectrum analysis result for the output voltage of one module and the output voltage of cascaded three modules. Large number of harmonics are involved in the output of one module, while signicantly small number of harmonics are involved in the output of cascaded three modules. Fig. 5(c) shows THD analysis results for the converter output voltage with respect to the number of modules. The THD of the output voltage is signicantly decreases as the number of modules increases. In the same number of modules it is relatively high when the modulation index (the amplitude ratio of the reference signal to the carrier signal) is less than 0.4. So, the desirable operation range of modulation index is located between 0.5 and 1.0. The proposed UPFC has three dc link capacitors for each phase. Each capacitor in the same phase might have a voltage deviation from the average voltage because each capacitor is isolated from others. This voltage unbalance is due to the unequal leakage current of the dc capacitor, the dead time of converter, unsymmetrical operation caused by the transient or the disturbance. By making the dc capacitor voltage balanced, it is possible to reduce the harmonics level of the converter output voltage. Fig. 6 shows the conguration of dc voltage unbalance controller for the dc capacitor. There are three controllers in the proposed UPFC because separate control was considered

Fig. 6. dc voltage unbalance controller.

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for each phase. The controller measures the voltage at the common connection point of shunt converter. This value is used to calculate the phase-lock angle by passing through the phase-lock loop. This value is adjusted by means of adding 2 /3 and 4 /3 for other two phases. The total dc link voltage is obtained by means of measuring each capacitor voltage with an isolated sensor and adding together. This voltage is used to obtain the average voltage of each capacitor by means of dividing by three. The average voltage is compared with the measured voltage of each capacitor and the error is passed through the PI controller and the limiter to obtain the phase-angle deviation . The phase-angle deviation is added to the phase-angle and the phase-lock angle . The total phase-angles are sent to the sine wave generator to obtain the reference signals Ref1, Ref2, Ref3, which have the phase deviation.

4. EMTDC simulation In order to analyze the operation of proposed UPFC, computer simulations with EMTDC were performed. The power system is represented by one-machine-innite-bus pattern. The transmission line is modeled considering lumped line reactance and resistance. The circuit parameters used in the simulation are shown in Table 2. Fig. 7 shows a conguration of the UPFC controller used in the simulation. Fig. 7(a) shows a control block diagram for the series converter and Fig. 7(b) for the shunt converter in automatic power ow control mode. The automatic power ow control is achieved by means of a vector control scheme that regulates the transmission line current using a synchronous frame, in which the control quantities appear as dc signals in the steady state. The appropriate reactive

Fig. 7. Block diagram of UPFC control, (a) series converter control, (b) shunt converter control.

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and real current components, i and i , are determined for q p a desired Pref and Qref . These are compared with the measured line currents, iq and ip , and used to drive the magnitude and angle of the series converter voltage, Vpq and pq , respectively. In the control scheme for the shunt converter, the magnitude of the output voltage is directly proportional to the dc voltage and only its angle is controllable. The outer voltage loop regulates the ac bus voltage and also controls the dc capacitor voltage. It changes the phase angle of the output voltage with respect to the ac bus voltage until the

Fig. 8. (Continued ). Table 2 Simulation parameters Base voltage Base current Rate voltage Power angle Line model 1 Fig. 8. Simulation results for normal operation, (a) desired real power (Pref ) and line real power (P), (b) desired reactive power (Qref ) and line reactive power (Q), (c) reference bus voltage (Vref ) and actual bus voltage (Vpu ), (d) reactive power at shunt converter, (e) dc capacitor voltages in phase A, (f) output voltage of shunt converter. Line model 2 DC capacitor Tr. leakage reactance 112.676 kV 946 A 138 kV 20 1.0053 19.73 mH 3.0159 59.19 mH 1000 F 0.12 p.u.

72 Table 3 Simulation scenario Time (s) Vref (p.u.) Pref (MW) Qref (MVar) 01.5 1.0 250 0 1.52.5 1.0 350 0

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2.53.5 1.0 450 50

3.54.5 1.0 450 100

4.55.5 1.0 450 150

dc capacitor voltage reached the value necessary to achieve the reactive power compensation demanded. The scenario considered in this simulation is shown in Table 3. It is assumed that the maximum simulation time is 5.5 s. The reference value of P, which is initially 250 MW, suddenly changes at 1.5, 2.5, 3.5, and 4.5 s as shown in the Table 3. The reference value of Q, which is initially 0 MVar, suddenly changes at 2.5 s as shown in Table 3. Fig. 8 shows the simulation results for the performance analysis of the proposed UPFC. Fig. 8(a) and (b) shows the tracking capability of the proposed UPFC with respect to the step-changes of P and Q reference values. The series converter injects a proper voltage into the transmission line to make the P and Q through the transmission line follow the reference values of Pref and Qref . Fig. 8(c) shows that the shunt converter maintains the bus voltage constant by means of STATCOM operation. Fig. 8(d) shows the reactive power

absorbed by the shunt converter, when the UPFC maintains the bus voltage. Fig. 8(e) shows the variation of each dc link capacitor in phase A. Although there is dispersion due to the PWM switching, it is known that the voltage of each capacitor is balanced evenly. Fig. 8(f) shows the output voltage waveform of the shunt converter. Since the shunt converter has coupling transformers, its output voltage waveform has lower level of harmonics. Fig. 9 shows the simulation results of the performance analysis of dc voltage unbalance controller. Fig. 9(a) shows the variation of dc capacitor voltage Vdc1, Vdc2, Vdc3, and the average dc link voltage Vdc , when the unbalanced controller works. It is assumed that each capacitor voltage, which is balanced initially, falls suddenly into the unbalanced state at 1.4 s. The voltage unbalance controller is activated at 1.8 s. This result conrms that the controller shown in Fig. 6 operates perfectly to make the dc link voltage balanced. Fig. 9(b) shows the phase-angle deviation of the reference signal when the unbalance controller detects the DC capacitor voltage unbalance. Since the capacitor voltage Vdc 2 has more deviation from others, the reference signal ref2 has more phase-angle deviation. When fault occurs at the transmission line, the proposed UPFC protects the shunt and series converters from the fault current using the protection scheme shown in Fig. 10. The over-current detector senses the fault current and generates a detection signal. This signal activates a mode change

Fig. 9. Simulation results of balancing dc voltage, (a) dc link capacitor voltage, (b) reference signal for unbalance control.

Fig. 10. Protection scheme for the proposed UPFC.

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of series converter from normal operation to short circuit operation. All the GTOs in upper parts of H-bridges are closed together to bypass the fault current rst, and then the mechanical circuit breaker is closed sequentially. The bus-voltage detector senses the low voltage due to the fault and generates a detection signal to block the gating of shunt converter. The gate pulses are restored to make the shunt converter in normal operation after clearing the fault. Once the shunt converter operates in normal, the series converter starts to inject the voltage by opening the circuit breaker. Table 4 shows a simulation scenario to conrm the protection when a single-line fault occurs. It is assumed that

Table 4 Simulation scenario Time (s) Shunt control 00.6 Iq mode 0 p.u. Series control Vdq mode Vd = Vq = 0 0.61.2 Vref mode 1.0 p.u. P, Q mode 200 MW 40 MVar 1.21.3 Fault & clear 1.452 Restart series converter

Fig. 11. Simulation results for fault and restart operation, (a) line current (rms value), (b) P and Q before UPFC, (c) dc capacitor voltages in phase A.

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Fig. 11. (Continued ).

from 0 to 0.6 s the shunt converter operates in the constant reactive current mode (Iq mode), while the series converter operates in the constant voltage injection mode (Vdq mode). From 0.6 to 1.2 s the shunt converter operates in the bus voltage regulation mode (Vref mode), while the series converter operates in constant real and reactive power mode

(P, Q mode). It is assumed that the single-line fault occurs at 1.2 s and cleared at 1.3 s. The series converter restarts at 1.45 s. Fig. 11 shows the simulation results for the single-line fault case, which occurs at 1.2 s and is cleared at 1.3 s. The series converter is assumed to restart at 1.45 s. Fig. 11(a)

Fig. 12. Conceptual diagram for system realization.

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shows the line current variation during the simulation time. The fault current increases up to 2.4 kA. Fig. 11(b) shows the real and reactive power variation through the line when the UPFC operates. The real and reactive powers have some transients during the fault, but these transients do not affect the restart operation through the protection scheme shown in Fig. 10. Fig. 11(c) shows the voltage across one capacitor in phase A. The voltage has some transients but it is under the limited value through proper operation of protection scheme. 5. System realization The system realization aims at the development of a practical system that can be built with commercially available and reliable components. A commercially available high-power GTO, Mitsubishi FG6000AU-120D, was considered for the building block of H-bridge. It has ratings of 6 kV peak off-state voltage (4.8 kV DC off-state voltage) and 6 kA controllable on-state current (1.5 kA average on-state current). In order to guarantee the safety, 4 kV DC off-state voltage and 1.25 kA average on-state current were considered for the system design. It is assumed that the proposed UPFC has 138 kV of nominal operating voltage and 150 MVA of power rating. There are 12 pairs of H-bridge modules for each phase in the proposed UPFC. The maximum injection voltage in series part is assumed 50% of the operation voltage (phase voltage of 32 kV). The turn-ratio of primary to each secondary winding in the single-phase multi-winding transformer is designed to be 24:1. The RMS voltage to be handled by each H-bridge is 2.7 kV, which is tolerable because the GTOs in one H-bridge have rating of 4 kV DC off-state voltage. Fig. 12 shows the conceptual diagram of the proposed UPFC including the simple power system. The proposed UPFC has twelve pairs of H-bridge module for each phase. There are total 36 pairs of H-bridge module, in which each pair of H-bridge has eight GTOs. Therefore, there are total 288 GTOs in the proposed UPFC. 6. Conclusion This paper proposes a novel UPFC based on H-bridge modules, isolated through single-phase multi-winding transformers. The dynamic performance of proposed system was analyzed by simulations with EMTDC, assuming that the UPFC is connected with the 138 kV transmission line

of one-machine-innite-bus power system. The proposed system can be directly connected to the transmission line without series injection transformers. It has exibility in expanding the operation voltage by increasing the number of H-bridge modules. The contribution of this paper is to propose a novel structure of UPFC to be connected in the transmission line directly without series injection transformer. The series transformer is a critical item in UPFC because it should have low saturation effect and low leakage impedance. The developed simulation model could be used to obtain design data for the actual hardware system.

Acknowledgements The research work described in this paper was supported by the research fund from the Next-Generation Power Technology Center in Myongii University, Korea.

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