Serial Peripheral Interface (SPI)

Serial Peripheral Interface (SPI)

SPI = Simple, 3 wire, full duplex, synchronous serial data transfer Interfaces to many devices, even many non-SPI peripherals Can be a master or slave interface 4 interface pins: -MOSI master out slave in -MIOS master in slave out -SCK serial clock -SS_n slave select 3 registers: -SPCR control register -SPSR status register -SPDR data register

Serial Peripheral Interface (SPI)

Full duplex, synchronous serial data transfer

master SPI device

slave SPI device

The SPI is a synchronous serial interface in which data in an 8-bit byte can be shifted in and/or out one bit at a time .It can be used to communicate with a serial peripheral device or with another microcontroller with an SPI interface.

Data is shifted out of the master's MOSI pin and in its MISO pin
Data transfer is initiated by simply writing data to the SPI data register. All data movement is coordinated by SCK. .

Operation of SPI
In the master SPI, the bits are sent out of the MOSI pin and received in the MISO pin. The bits to be shifted out are stored in the SPI data register, SP0DR, and are sent out most significant bit (bit 7) first. When bit 7 of the master is shifted out through MOSI pin, a bit from bit 7 of the slave is being shifted into bit 0 of the master via the MISO pin.

After 8 clock pulses or shifts, this bit will eventually end up in bit 7 of the master.

Operation of SPI
The least significant bit can be sent out first by setting the LSBF bit to 1 in the SPI Control Register.
The clock, which controls how fast the bits are shifted out and into SP0DR. The frequency of this clock can be controlled by the SPI baud rate register, SP0BR. The SS pin must be low to select a slave. This signal can come from any pin on the master, including its SS pin when it is configured as an output.

Serial Peripheral Interface (SPI)

SPI Control Rgister (SPCR)

interrupt enable: if set, interrupt occurs when SPI interrupt flag and global interrupt enable are set spi enable: if set, SPI interface is enabled data order: if set, LSB is transmitted first master/slave select: if set, SPI in master mode clock polarity: '0' SCK low in idle '1' SCK high in idle clock phase: '0' leading edge sample, trailing edge setup '1' leading edge setup, trailing edge sample

(in SPSR)

clock rate

SPI2X SPR1 SPR0 SCLK 0 0 0 fosc/4 0 0 1 fosc/16 0 1 0 fosc/64 0 1 1 fosc/128 1 0 0 fosc/2 1 0 1 fosc/8 1 1 0 fosc/32 1 1 1 fosc/64

Serial Peripheral Interface (SPI)

SPI Status Register (SPSR)

reserved bits interrupt flag: set when serial transfer is complete write collision: set if SPDR is written during a receive transfer

2x clock rate: if set, doubles clock rate in master mode

SPI Data Register (SPDR)

SPDR is a read/write register used for data transfer. Writing SPDR sends data out MOSI. Reading SPDR gets the data that was clocked into MISO.

Serial Peripheral Interface (SPI)

74HC595 A perfectly fine SPI peripheral

Serial Peripheral Interface (SPI)

74HC165 Another fine SPI peripheral

Advantages
Full duplex communication.
Complete protocol flexibility for the bits transferred. Not limited to 8-bit words.

Extremely simple hardware interfacing.

Typically lower power requirements than IC or SM Bus due to less circuitry.

Slaves use the master's clock, and don't need precision oscillators.
Transceivers are not needed.

Dis-Advantage
No hardware slave acknowledgment.

Supports only one master device.

No error-checking protocol is defined.

Only handles short distances compared to RS-232 and RS-485,CANbus.

Applications
Sensors: temperature, pressure, ADC, touch screens, video game controllers.

Control devices: audio codecs, digital potentiometers, DAC.

Communications: Ethernet, USB, USART, CAN etc

Real-time clocks.