Modifications in Microprocessor

Internal ROM Cache Memory Size L1 Cache + L2 Cache Data Bus Width

Microprocessors
4004:4-bit 8008:8-bit 8080:8-bit with advanced design 8085:8-bit with added features in architecture 8086:16-bit with data & address capability, high speed, powerful instruction set, more no. of general purpose registers

16 bit Microprocessor-8086
16-bit Data Lines 20-bit Address Lines 220 = 1 Megabytes Address Memory 6-byte instruction cache or queue 20,000 variation in instructions(246 in 8085) 5 Mhz Clock Frequency CISC(Complex Instruction Set Computers) Variants:8086-1(10 Mhz), 8086-2(8 Mhz)

16 bit Microprocessor-8086 (cont..d)

Approximately 29,000 transistors Support Multiplication & Division

Architecture of 8086
Divided into two units : 1. Bus Interface Unit 2. Execution Unit

Bus Interface Unit

Segment Registers Instruction Pointer 6-byte Instruction Queue or Caches

Function of Bus Interface Unit

It handles transfer of data and addresses between the processor and memory / IO. It reads data from memory and I/O devices. It writes data to memory and I/O devices. It computes and sends out addresses. It fetches instruction codes. It stores fetched instruction codes in a FIFO register called QUEUE.

Instruction Queue
To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time from memory. All six bytes are then held in first-in-first-out 6byte register called instruction queue. Then all bytes are given to EU one by one. This pre-fetching operation of BIU may be in parallel with execution operation of EU, which improves the execution speed of the instruction.

Execution Unit
General Purpose Registers Stack Pointer Base Pointer Index Registers ALU Flag Register Instruction Decoder Timing & Control Unit

Function of Execution Unit

It receives opcode of an instruction from the QUEUE. It decodes it and then executes it. It tells BIU where to fetch the instructions or data from. It contains the control circuitry to perform various internal operations. It has 16-bit ALU, which can perform arithmetic and logical operations on 8-bit as well as 16-bit data.

Pipelining
While EU executes instructions, BIU fetches instructions from memory and stores them in the QUEUE. BIU and EU operate in parallel independent of each other. This type of overlapped operation of the functional units of a MP is called Pipelining.

Register Organisation in 8086

General Purpose Registers Special Purpose Registers

General Purpose
16-bit register Can be used as 8-bit or 16-bit Used for holding or storing data/variables As counter or for storing offset address AX,BX,CX,DX are general purpose AX can be divided into AH & AL Similarly for BX,CX & DX

General Purpose (cont..d)

AX-16-bit Accumulator BX-Offset storage for forming physical address CX-Default counter for string & loop instruction DX-General Purpose use