MOS-AK/ESSDERC/ESSCIRC Workshop (Montreux 2006)

Verilog-A: An Introduction for Compact Modelers

Geoffrey Coram

Outline
The

Problem Modeling Languages Diode Example Guidelines Admonishments Compiler Optimizations Conclusion References (and Further Examples)

Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Many models, many simulators

VBIC ACM HiCUM Eldo ADS Spectre Smash

USIM
BSIM PSP HVEKV MM20
from McAndrew, BMAS 2003
3

Mextram
HiSIM

HSIM APLAC Nanosim HSPICE Golden Gate AMS

Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

The Solution
VBIC ACM Modeling Interface HiCUM Eldo ADS Spectre Smash

USIM
BSIM PSP HVEKV MM20
from McAndrew, BMAS 2003
4

Mextram
HiSIM

HSIM APLAC Nanosim HSPICE Golden Gate AMS

Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Modeling Languages
Programming
FORTRAN

languages:

(SPICE2) C (SPICE3) + Fast, direct access to simulator Must compute derivatives No standard interface
Intimate knowledge of simulator required
MATLAB

+ Excellent for data fitting Does not run directly in any analog simulator
5 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Behavioral Modeling Languages

VHDL-AMS
First

analog behavioral modeling language working group (IEEE 1076.1) Painfully slow to come to fruition Europe prefers VHDL (for digital) Runs in:
AMS Designer (Cadence), DiscoveryAMS (Synopsys), ADVance MS (Mentor), Smash (Dolphin), only AMS simulators!

No clear definition of VHDL-A (except by R. Shis MCAST model compiler)

6 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Behavioral Modeling Languages

Verilog-A
Pushed

Verilog-AMS

by Cadence, came to market earlier Verilog-A from Open Verilog International became part of Accellera Verilog-AMS IEEE 1800 authorized to develop SystemVerilog-AMS Verilog-AMS runs in the same AMS simulators as VHDL-AMS + Verilog-A runs in Spectre, HSpice, ADS, Eldo and internal simulators of semiconductor companies + Clear definition of A + Verilog-AMS LRM 2.2 was driven by the requirements for compact modeling

Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

V-AMS LRM 2.2 Additions

Highlights
output

for compact modeling:

/ operating point parameters

vdsat, id_chan also gm, cgs using new ddx() operator

$simparam

to access simulator quantities

(gmin)
$param_given paramsets

replace and extend Spice .model

cards
8 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

VHDL-AMS Diode
-- Modified from http://www.syssim.ecs.soton.ac.uk/vhdl-ams/examples/smpr.htm library IEEE; use IEEE.math_real.all; use IEEE.electrical_systems.all; use IEEE.FUNDAMENTAL_CONSTANTS.all; entity diode is generic (Isat: current := 1.0e-14); -- Saturation current [Amps] port (terminal p, n : electrical); end entity diode; architecture ideal of diode is quantity v across i through p to n; constant TempC : real := 27.0; -- Ambient Temperature [Degrees] constant vt : real := PHYS_K*(273.15 + TempC )/PHYS_Q; -- Thermal Voltage begin i == Isat*(limit_exp(v/vt) - 1.0); end architecture ideal;
9 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

VHDL-AMS Diode
-- Modified from http://www.syssim.ecs.soton.ac.uk/vhdl-ams/examples/smpr.htm library IEEE; use IEEE.math_real.all; use IEEE.electrical_systems.all; use IEEE.FUNDAMENTAL_CONSTANTS.all;

is is a keyword! entity diode is generic (Isat: current := 1.0e-14); -- Saturation current [Amps] port (terminal p, n : electrical); end entity diode;
architecture ideal of diode is quantity v across i through p to n; constant TempC : real := 27.0; -- Ambient Temperature [Degrees] constant vt : real := PHYS_K*(273.15 + TempC )/PHYS_Q; -- Thermal Voltage begin i == Isat*(limit_exp(v/vt) - 1.0); end architecture ideal;
10 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

TempC is a constant!

Verilog-A Diode
`include "disciplines.vams" module diode(a,c); inout a,c; electrical a,c; parameter real is = 10p from (0:inf); real id; (*desc = "conductance "*) real gd; analog begin id = is * (limexp(V(a,c) / $vt) 1.0); gd = ddx(id, V(a)); I(a,c) <+ id + V(a,c)*$simparam("gmin", 1e-12); end endmodule
11 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Verilog-A Diode
`include "disciplines.vams" module diode(a,c); inout a,c; electrical a,c; parameter real is = 10p from (0:inf); real id; (*desc = "conductance "*) real gd; analog begin id = is * (limexp(V(a,c) / $vt) 1.0); gd = ddx(id, V(a)); I(a,c) <+ id + V(a,c)*$simparam("gmin", 1e-12); end thermal voltage uses endmodule simulation temperature
12 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Verilog-A Diode
`include "disciplines.vams" disciplines define through and across module diode(a,c); inout a,c; electrical a,c; variables parameter real is = 10p from (0:inf); real id; (*desc = "conductance "*) real gd; analog begin id = is * (limexp(V(a,c) / $vt) 1.0); gd = ddx(id, V(a)); I(a,c) <+ id + V(a,c)*$simparam("gmin", 1e-12); end endmodule
13 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Verilog-A Diode
`include "disciplines.vams" modules module diode(a,c); combine entity inout a,c; electrical a,c; and architecture; parameter real is = 10p from (0:inf); real id; replace Spice (*desc = "conductance "*) real gd; primitives analog begin id = is * (limexp(V(a,c) / $vt) 1.0); gd = ddx(id, V(a)); I(a,c) <+ id + V(a,c)*$simparam("gmin", 1e-12); end endmodule
14 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Verilog-A Diode
`include "disciplines.vams" parameters have module diode(a,c); ranges (and defaults) inout a,c; electrical a,c; parameter real is = 10p from (0:inf); real id; (*desc = "conductance "*) real gd; analog begin id = is * (limexp(V(a,c) / $vt) 1.0); gd = ddx(id, V(a)); I(a,c) <+ id + V(a,c)*$simparam("gmin", 1e-12); end endmodule
15 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Verilog-A Diode
`include "disciplines.vams" module diode(a,c); inout a,c; electrical a,c; parameter real is = 10p from (0:inf); real id; (*desc = "conductance "*) real gd; analog begin id = is * (limexp(V(a,c) / $vt) 1.0); gd = ddx(id, V(a)); I(a,c) <+ id + V(a,c)*$simparam("gmin", 1e-12); end built-in function with endmodule improved convergence
16 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Verilog-A Jump Start

Looks

much like C

Intuitive

and easy to read and learn Start with an existing model and modify
Based
Set

on through and across variables

up is for KCL and KVL Understand the contribution operator

Dynamic

I(di,si) <+ Ids; // current di to si V(d ,di) <+ I(b_rd)*rd; // voltage d to di

flows are done via ddt()

I(t,b) <+ ddt(C * V(t,b));

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Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Best Practices
Models
most

formulated in currents I(V) and charges Q(V)

natural for modified nodal analysis (MNA) Q(V) not C(V) to ensure conservation of charge

ddt(Q(V)) != ddt(C(V) * V) != C(V) * ddt(V)

No

access to previous timesteps

watch

non-quasi-static formulations allows model to run in RF simulator

Noises

as current sources No discontinuities

18 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Discontinuities
Spice

requires continuous derivatives Consider this code: if (vbs == 0.0) begin qbs = 0.0; capbs = czbs+czbssw+czbsswg; end else if (vbs < 0.0) begin qbs = I(b,s) <+ ddt(qbs);
19 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Discontinuities
Resulting

C code: Automatic derivative if (vbs == 0.0) { differs from intended value qbs = 0.0; dqbs_dvbs = 0.0; //capbs=czbs+czbssw+czbsswg; } else if (vbs < 0.0) { qbs =

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Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Discontinuities
HiSIM2

Verilog-A (beta code) Clipping in C code may affect values and derivatives differently

4 3.5 3

HiSIM Verilog-A (beta code) ac drain current (real part) hisim ir(m1,d)

x1e-3

2.5 2 1.5 1 .5 0 -80 -40 0 40 80 vd, x1e-3 120 160 200

if ( Vds <= `epsm10 ) begin Pds = 0.0 ; Psl = Ps0 ;

21 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Compiler Optimizations
Common

subexpressions

id = is * (exp(vd/vtm) 1.0); gd = is/vtm * exp(vd/vtm);

Eliminating

internal nodes

if (rs == 0.0) V(b_res) <+ 0.0; else I(b_res) <+ V(b_res) / rs;
Dependency
replace
22

trees

analysis() and initial_step

Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

analysis()
Consider

this code:

if (analysis("tran")) begin qd =
No

capacitance in:

small-signal

ac analysis, harmonic balance, envelope following Pseudo-transient homotopy

23 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

analysis()
Consider

this code: if (analysis("noise")) begin flicker = strongInversionNoiseEval(vds, temp);

But

what about PNOISE, HBNoise, ?

MUST do this optimization

Compiler/Simulator
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Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Events
Consider

this code: @(initial_step) begin isdrain = jsat * ad; happens for a dc sweep?

What

dont

want re-computing for bias sweep need re-computing for temperature sweep
Even

for transient, initial_step is true for every iteration at time=0

MUST do this optimization

Compiler/Simulator
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Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

ADMS Magic Names

ADMS

uses special block names to identify sections of code PSP Verilog-A: begin : initializeModel NSUB0_i = `CLIP_LOW(NSUB0,1e20); // hurt for other compilers

Eg

Doesnt

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Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Software Practices
Use

consistent indentation Align code vertically on = Use meaningful names

use

maximum size (8) to help vertical alignment

Include

comments: brief description, reference documentation Physical constants are not dated and could change
model

results would then change define physical constants for a model

27 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

PSP Model Code

// 4.2.4 Surface potential at source side Gf2 = Gn2 * f_s; inv_Gf2 = 1.0 / Gf2; Gf = sqrt(Gf2); xi = 1.0 + Gf * `invSqrt2; inv_xi = 1.0 / xi; Ux = Vsbstar * inv_phit1; xn_s = phib * inv_phit1 + Ux; if (xn_s < `se) delta_ns = exp(-xn_s) * inv_f; else delta_ns = `ke * inv_f / `P3(xn_s - `se); margin = 1e-5 * xi; `sp_s(x_s, xg, xn_s, delta_ns)
28 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

PSP Model Code

// 4.2.4 Surface potential at source side Gf2 = Gn2 * f_s; inv_Gf2 = 1.0 / Gf2; equation number from Gf = sqrt(Gf2); documentation xi = 1.0 + Gf * and explanation inv_xi = 1.0 / xi; Ux = Vsbstar * inv_phit1; xn_s = phib * inv_phit1 + Ux; if (xn_s < `se) delta_ns = exp(-xn_s) * inv_f; else delta_ns = `ke * inv_f / `P3(xn_s - `se); margin = 1e-5 * xi; `sp_s(x_s, xg, xn_s, delta_ns)
29 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

PSP Model Code

// 4.2.4 Surface potential at source side Gf2 = Gn2 * f_s; alignment for inv_Gf2 = 1.0 / Gf2; readability Gf = sqrt(Gf2); xi = 1.0 + Gf * `invSqrt2; inv_xi = 1.0 / xi; Ux = Vsbstar * inv_phit1; xn_s = phib * inv_phit1 + Ux; if (xn_s < `se) delta_ns = exp(-xn_s) * inv_f; else delta_ns = `ke * inv_f / `P3(xn_s - `se); margin = 1e-5 * xi; `sp_s(x_s, xg, xn_s, delta_ns)
30 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

PSP Model Code

// 4.2.4 Surface potential at source side Gf2 = Gn2 * f_s; inv_Gf2 = 1.0 / Gf2; Gf = sqrt(Gf2); xi = 1.0 + Gf * `invSqrt2; inv_xi = 1.0 / xi; Ux = Vsbstar * inv_phit1; indentation xn_s = phib * inv_phit1 + Ux; if (xn_s < `se) of blocks delta_ns = exp(-xn_s) * inv_f; else delta_ns = `ke * inv_f / `P3(xn_s - `se); margin = 1e-5 * xi; `sp_s(x_s, xg, xn_s, delta_ns)
31 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Other Model Code

//----Self Heating Effect //(implemented only on mobility)-----PD = (VDE-VS)*Id; no reference to if (SH_switch ==1) begin documentation I(TH) <+ PD; RTHNOM = RTHNOM_298K*(1+alpha_SHE*(Tempp-TNOMK)); RTH = RTHNOM*(1+alpha_SHE*(Tempp+V(TH)-TNOMK)); I(TH) <+ - V(TH)/(RTH); I(TH) <+ - ddt(CTH*V(TH)); end else begin inconsistent I(TH) <+ 0; end indentation Tratio_SH=(Tempp+V(TH)*SH_switch)/TNOMK; BEX=BEX0/pow( abs(VG-VS) +1e-1,par_SHE); KP_T=KP0*pow(Tratio_SH,BEX);
32 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Other Model Code

//----Self Heating Effect //(implemented only on mobility)-----PD = (VDE-VS)*Id; if (SH_switch ==1) begin I(TH) <+ PD; RTHNOM = RTHNOM_298K*(1+alpha_SHE*(Tempp-TNOMK)); RTH = RTHNOM*(1+alpha_SHE*(Tempp+V(TH)-TNOMK)); I(TH) <+ - V(TH)/(RTH); I(TH) <+ - ddt(CTH*V(TH)); end else begin I(TH) <+ 0; end

correct indentation

Tratio_SH=(Tempp+V(TH)*SH_switch)/TNOMK; BEX=BEX0/pow( abs(VG-VS) +1e-1,par_SHE); KP_T=KP0*pow(Tratio_SH,BEX);

33 Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Other Model Code

// new model for mobility reduction, //linked to the charges model // !! mb 98/10/11 (r10) introduced fabs(Eeff) (jpm) //

cryptic comments where is Eeff??

if ((qb + eta_qi*qi) > 0.0) begin E0_Q_1 = 1.0 + T0*(qb + eta_qi*qi); end else begin E0_Q_1 = 1.0 - T0*(qb + eta_qi*qi); end T0_GAMMA_1 = 1.0 + T0*GAMMA_sqrt_PHI; // !! mb 97/06/02 ekv v2.6 beta = KP_Weff * T0_GAMMA_1 / (Leq * E0_Q_1+1e-60); // !! mb 97/07/18

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Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Coding Style
Verilog-A

can be very readable

Characterization

engineers and simulator people will read it a good impression!

Make

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Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Conclusion
Verilog-A

is a powerful and easy-to-use compact modeling language a good compact model still requires care and rigor examples now available

Writing

Many

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Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

References
Designers

Guide

http://www.designers-guide.org/ Forum Verilog-A model library (VBIC, MOS11, JFET, etc.)

MCAST

http://www.ee.washington.edu/research/ mscad/shi/mcast.html Automatic compiler beats hand-coded C

(Prof. CJ Richard Shi)

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Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)

Examples
Verilog-A

http://www.designers-guide.org/VerilogAMS/
VBIC, MOS11, JFET, etc.

model library at

Silvaco

https://src.silvaco.com/ResourceCenter/en/ downloads/verilogA.jsp
BSIM3,

public domain models (non-commercial use)

BSIM4, BJT, etc. But: watch out for @(initial_step)!

PSP

http://pspmodel.asu.edu/ http://hitec.ewi.tudelft.nl/mug/

Mextram HiCUM

http://www.iee.et.tu-dresden.de/iee/ eb/hic_new/hic_intro.html

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Coram: Verilog-A Introduction for Compact Modelers (MOS-AK Montreux 2006)