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Layout
Schematic
Transistors
Stick Diagram
VLSI Layout
out
The structure of the pFET array is the dual of the nFET array!
Stick Diagrams
VLSI design aims to translate circuit concepts onto silicon. Stick diagrams are a means of capturing topography and layer information - simple diagrams. Stick diagrams convey layer information through color codes (or monochrome encoding. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries, or any other form of compliance with layout or design rules. Useful for interconnect visualization, preliminary layout, layout compaction, power/ground routing, clock routing, etc.
Metal 1
Purple
Metal 2
Red
Poly
ndiff pdiff Contacts
Green Yellow Black
Can also draw in shades of gray/line style.
NMOS Transistor
S
D
PMOS Transistor
G S
Vdd
Demarcation Line
Vss
A B Vss
O/P
A
OUT
NOR Gate
3. 4.
5.
Out
C B
Ground
Cost: i) The Layer which costs more, should be used few times. ii) The Layer which costs less, should be used frequently. iii) The order of layers in terms of decreasing cost: a)Polysilicon b) N-diff & P-diff c) Metal. Complexity: If the Layers cross over each other frequently, then complexity increases and vice-versa.
Logic Circuits I.
Multiplexer Example
Y = S * A + S * B
A Y B
Y = =
Y =
NAND( NAND(S,A),NAND(NOT(S),B))
Y =
NAND( NAND(S,A),NAND(NOT(S),B))
Vd
P P P NAND(S,A) S A N N N NOT(S)
Vss
Y =
NAND( NAND(S,A),NAND(S,B))
Vd
P P P
S
S A
NAND(NOT(S),B)
N
N N
N B
Vss
Y =
NAND(P,Q)
Vd
P P P P S A N N N B N N P P Q N N P P
Vss
A B S
Vss
Area = 17 * 4 = 68 2
NMOS Encoding
Name of Layer Stick Encoding
Polysilicon
Color
Red
N-diff, N-active
Metal1
Green
Blue
Implant
Contact Cut
Yellow
Black
Y A B C VSS
BiCMOS Encoding
Layout
When "drawing layouts from stick diagram, there are rules that apply to spacing and sizes. Scalability of Layout is achieved by defining the unit of measure of your drawing. For example, if you draw a box to represent the diffusion mask, how big is that box in terms of the actual size of the diffusion region created in the silicon wafer? One approach is to set up a translation between the scale used for the drawing. For example, when creating this Word document, there is a "ruler" on the top defining the page, with units "1," "2," "3," etc. These numbers represent inches when you print out the page with magnification = 1. The size of the box below is easily measured with a ruler.
DESIGN RULES
Mask layers are tools for manufacturing of ICs. Manufacturing processes have inherent limitations in accuracy. Design rules specify geometry of masks which will provide reasonable yields. i.e. size and spacing of layers.
Allow translation of circuits (usually in stick diagram or symbolic form) into actual geometry in silicon Interface between circuit designer and fabrication engineer Compromise designer - tighter, smaller
Design rules based on single parameter, (lambda) :abstract unit. Scale the design to the appropriate actual dimensions using (.25m) when the chip is to be manufactured. Properties: 1) Simple for the designer 2) Wide acceptance 3) Provide feature size independent way of setting out mask 4) If design rules are obeyed, masks will produce working circuits 5) Minimum feature size is defined as 2 6) Used to preserve topological features on a chip 7) Prevents shorting, opens, contacts from slipping out of area to be contacted
Contact cuts
Butting Contact:
Metal2 is another metal layer which is Dark Blue or Purple. Metal2 should be used for global power and Clock rails. Metal1 should be used for local signal and power rails. The Contact between metal2 to metal1 contact is called VIA.
Advantages
Disadvantages
Interconnections between the Layers in the IC are represented by wires. These Wires have parameters such as
These parameters have different values for different Technologies (1.2m, 2m, 5 m). Interconnect parameters impact
Modern Interconnect
RESISTANCE
Resistance of a square slab of Conducting layer or material is Sheet Resistance (Rs) . Length (L) = Width (W) Parameters of the layer.
X
t w
Rs=/t where = Resistivity, t = Thickness, Rs is Independent of Area of square. Rs of Layers depends on Resistivity and Thickness. For Poly and Metal Layers
Resistivity and Thickness are known easily. Diffusion Depth - Thickness. Doping Level Resistivity.
Silicide
Silicides are the interconnecting medium for the Polysilicon due to its low resitivity than Polysilicon.
Properties: Conductivity: 8-10 times better than Poly Resistivity : very less then Poly Examples:
Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi
n+ p
n+
Silicides: WSi 2, TiSi 2, PtSi 2 and TaSi Conductivity: 8-10 times better than Poly Resistivity : very less then Poly
CAPCITANCE
Conductive Layers are separated by dielectric in MOS Transistor, so parallel plate capacitive effects must be present. Area Capacitance is denoted by C.
C = 0insA / D Farads
Standard unit of Capacitance is the gate to channel capacitance of MOS Transistor having W=L feature size.
It is denoted by Cg. Cg can be evaluated for MOS transistors of different feature size.
Multilayer capacitances
Wiring Capacitances
H tox
SiO2 Substrate
For wide conductors with W >> H, capacitance to substrate (of any ground plane) can be determined as a parallel plate capacitor For most real conductors in todays IC technology, fringing fields contribute a major part of the line capacitance and must be included in the capacitance calculations.
For W =~ H (below), fringing fields add more than the parallel plate portion to the total line capacitance.!
W>>H
(a)
H W - H/2
W=H
W=H/2
(b)
Interlayer Capacitance
The capacitance effects when multiple layers cross or underlies another is known interlayer capacitance. This Capacitance leads to Cross-talk.
Level2 Insulator
Creates Cross-talk
Peripheral capacitance
N-diffusion regions form junction with p-well and P-diffusion regions form junction with n-well, which leads to Peripheral capacitance. The smaller area of diffusion regions leads to high value of peripheral capacitance. Diffusion formed by implant have negligible peripheral capacitance due to negligible depth. This capacitance value is greater than area capacitance.
Delay Unit ()
When one standard gate area capacitance (1Cg) is charged through one feature size of n-channel resistance (1Rs), then delay unit () is = 1Rs x 1Cg sec. Delay unit can be calculated for 5m, 2m, 1.2m technologies respectively. value can be increased by a factor of 2 or 3, if we consider worst case delays.
Delay Unit ()
Delay unit value is approximately equal to Transit time (sd). Since Transit time depends on Vds, so as Delay unit (). So, can be calculated with Vds. All timings in the system can assessed with , so is the fundamental time unit.
Inverter Delays
Pull-down delay = Rpd x 1 Cg Pull-up delay = Rpu x 1 Cg Asymmetry in rise and fall due to resistance difference between pull-up and pull-down (factor of 4) (due to mobilities of carriers) Delay through a pair of inverters is (fall time) + 4 (rise time) Delay through a pair of NMOS inverters is therefore 5
Pull-down delay = Rpd x 2 Cg Pull-up delay = Rpu x 2 Cg Asymmetry in rise and fall due to resistance difference between pull-up and pull-down (factor of 2.5) (due to mobilities of carriers) Delay through a pair of inverters is 2 (fall time) + 5 (rise time) Delay through a pair of CMOS inverters is therefore 7
A CMOS Inverter discharges or charges through a Load capacitor CL , through which we can find Rise and Fall Times. Rise Time Estimation:
Mobility: Since mobility of electrons is 2.5 times greater than mobility of holes, Rise times have 2.5 times more delay than Fall times. So, the Width of P-Channel should be 2.5 times greater than n-channel. Load capacitance: Both Rise and Fall times are proportional. Source Voltage: Both Rise and Fall times are inversely proportional.
Rs and Cg.
Buffers may be used in long lines to reduce the total line delay.
Propagation Delays
Pass Transistors are used in series or parallel for switch logic. If a signal Vdd is sent through a series of pass transistors, then the signal is degraded to Vdd-Vtp. A pass transistor can be assumed as RC network during the operation. Propagation Delay (p) can be calculated w.r.t distance x of the network. Overall Delay (d) is of n pass transistors can also be calculated through the series RC network. If n increases then d increases. So, the max value of n=4.
Long Polysilicon wires also represents RC networks, which increase signal delay. This results in slow rise time and then noise. If noise is present, output values will switch between 0 and 1 for inverters. Long Diffusion wires have high C value, which also increase signal delay. So both Poly and diffusion wires should be used for shorter distances only.
In series pass transistors network, if a repeater is placed after 4 pass transistors, then delay will be decreased. For Polysilicon wires, use of repeaters (buffers or inverters). 1) speed-up the rise time. 2) guard the effects of noise. So the output will not be toggled especially for inverters.
Nature of Interconnect
Local Interconnect
Global Interconnect
IDEAL WIRE
Scaling - Introduction
VLSI technology is constantly evolving towards smaller line widths Reduced feature size generally leads to
More accurate description of modern technology is ULSI (ultra large scale integration.
Scaling - Introduction
Minimum feature size. Number of gates on one chip. Power dissipation. Maximum operational frequency. Die size Production cost.
Full Scaling
Scaling Rules
Scaling Models
Constant Electric field Scaling Constant Voltage Scaling Combined Voltage and Dimension scaling.
In our discussions we will consider 2 scaling factors, and 1/ is the scaling factor for VDD and oxide thickness D 1/ is scaling factor for all other linear dimensions We will assume electric field is kept constant
It is important that you understand how the following parameters are effected by scaling
Gate Area Gate Capacitance per unit area Gate Capacitance Charge in Channel Channel Resistance Transistor Delay Maximum Operating Frequency Transistor Current Switching Energy Power Dissipation Per Gate (Static and Dynamic) Power Dissipation Per Unit Area Power - Speed Product
Limitations of scaling
Substrate Doping
Built-in-potential VB depends on substrate doping level NB. VB should be added to Vdd for obtaining effective voltage. To scale down depletion width, NB should be increased and VB should also increase. Then Vdd should also be scaled. Now the total is the sum of VB and Vdd
Scaling of Length depends on photolithographic technology. If Channel length (L) scaling is more, then depletion width decreases and depletion region of source comes closer to drain. To maintain proper transistor action, Channel Length should be twice the depletion width. It also depends on substrate doping and supply voltage.
Scaling Limits
Scaling of Interconnects
Resistance: Resistance of track R ~ L / wt R (scaled) ~ (L / ) / ( (w/ )* t (t /)) R(scaled) = R Therefore resistance increases with scaling. Thickness should be scaled less to decrease resistance. A w
Time constant of track connected to gate, T = R * Cg T(scaled) = R * ( / 2) *Cg = ( / ) *R*Cg Let = , therefore T is unscaled! Therefore delays in tracks dont reduce with scaling Therefore as tracks get proportionately larger, effect gets worse Cross talk between connections gets worse because of reduced spacing
Scaling device dimensions lengthens the interconnections in the chip. So resistance, capacitance and time constant increases. The effects are 1) Increased Propagation delay. 2) Signal decay. 3) Clock Skew. But delay of device will not increase.
Multilayer interconnections with thicker and wider conductors reduce both R and C. Inclusion of cascaded drivers and repeaters in long interconnects. Optical fibers, Lasers are used as longer interconnects due to its advantage of high speed. The values of R and C are very less for optical fibers when compared to Metal (Al). Integration of GaAs with optical fibers is more compatible than integration of Silicon with optical fibers