VHDL Design Units

VHDL Design Units

Entity Package Configuration Primary Design Units

Architecture Package body

Secondary Design units

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VHDL Terms
Entity :
All designs are expressed in terms of entities. An entity is the most basic building block in a design. If the design is hierarchical, then the top-level description will have lower-level descriptions contained in it. These lower-level descriptions will be lower-level entities contained in the top-level entity description

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VHDL Terms
Architecture :
All entities that can be simulated have an architecture description. The architecture describes the behaviour of the entity. A single entity can have multiple architectures. One architecture might be behavioural while another might be structural description of the design.

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VHDL Terms
Configuration :
A Configuration statement is used to bind a component instance to an entity-architecture pair.

Package :
A package is a collection of commonly used data types and subprograms in a design. (like a toolbox that contains tools used to build designs)
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An Entity and its Model

Entity Hardware Abstraction of a Digital System Entity Declaration Model

Architecture Bodies

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Components
Package Declaration Entity (Interface)

Package Body

Architecture (Function)

Configuration

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A VHDL File

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Design Entity
E n t i t y E I n A F
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n t e

t i t y r f a i t e

D c e

c D

r c h u n

c t u n
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c t i o

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Entity
Declares the design name. Provides the port information Describes the interface of the design entity . The interface includes all inputs, outputs and bidirectional signals and generics. A declarative part to declare Subprograms, types and constants . Declarations are visible to all the architectures assigned to the entity An entity may contain its own passive statements.

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Entity Syntax
Entity entity-name is [generic (list-of-generics-and-their-types);] [port (list-of-interface-port-names-and-theirtypes);]

[entity-item-declarations]
[begin
entity-statements]

End [entity][entity_name];
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PORTS
Each I/O signal in an entity declaration is a port. Must have a name, a direction (mode) and a data type. A port is a data object (signal). It can be assigned values and used in expressions.

port ( portname : [mode] subtype_indication [:= init_value] {; portname : [mode] subtype_indication [:= init_value]} );
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Port Data Types

Pre defined Boolean bit bit_vector integer IEEE std_logic_1164 std_ulogic , std_logic std_logic_vectors

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Modes
In - input port, read only out - output port , write only inout - bi-directional port, read/write, multiple drivers buffer - read and update, single driver
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VHDL Entity
entity- name of a function and its interfaces

a_in b_in cy_ in

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Full adder

sum_ou t cy_out

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Entity
entity fulladder port is in bit ;

( a_in,b_in,cy_in :

sum_out,cy_out out bit ) ; : end fulladder ;

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Entity Declarations

a 4 4 b ci

4 add4 Entity add4

Sum co

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Entity Declaration
Example
Entity add4 is port ( a b ci co : : : : in std_logic_vector(3 downto 0); std_logic_vector in std_logic_vector(3 downto 0); std_logic_vector in std_logic; std_logic out std_logic); std_logic

sum : out std_logic_vector(3 downto 0); std_logic_vector end add4;

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Example
entity and 2 is port (a,b end and2; architecture dataflow of and2 is Begin y<=a and b; end dataflow; : in bit; y : out bit); --and gate
a b y

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