ECE 465 Lecture Notes # 1 Introduction to Digital Design

Shantanu Dutt ECE Dept. UIC

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Copyright: Shantanu Dutt

Copyright: Shantanu Dutt

the analog BW is proportional to n, the the # of distinct values or levels, while the corresponding digital BW is proportional to log n (or more exactly to Vdd(log n))
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i.e., 2s complement number system, floating-point number system, etc.

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 Pure if-then-else type constructs can be implemented using combinational circuits

Loops generally need to be impl. using sequential circuits, since the circuit/system needs to remember where it is in the loop

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Copyright: Shantanu Dutt

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Copyright: Shantanu Dutt

Copyright: Shantanu Dutt

There are two switches S1 and S2 to control the a light bulb (e.g., one switch near each door of a room w/ 2 doors). Design a logic circuit so that the bulb can be controlled (essentially, toggled) by either switch (i.e., by flicking/pushing either switch).

Diff. initial conditions

S1

S2

S1

S2

np/0 np/0 0 np/0 p/1 p/1 p/1 p/1 1 0 np/0 1

np/0 np/0 1 np/0 p/1 p/1 p/1 p/1 0 1 np/0 0

1-switch flick transition arrows (verifying consistency Legend: np: not pushed (or, say, up posn) of corresponding p: pushed (or, say, down posn) o/p transitions)

Design Steps (for small-size designs w/ up to around 6 vars; we will later learn about hierarchical or divide-and-conquer strategies for larger designs) 1a. If TT can be obtained directly (due to the nature of the problem statement), then encode inputs and outputs, get the TT, and go straight to the minimization step (Step 4). Otherwise go to Step 1b.
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Alternate Statement

Design Steps (for small-size designs w/ up to around 6 vars; we will later learn about hierarchical or divide-and-conquer strategies for larger designs) 1b.

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FPGAswill do later)

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 Example: Consider an 8-variable NOR function f = (x7+x6+x5+x4+x3+x2+x1+x0). Its implementation using a single n/w is given below; we assume that a pMOS transistor has a voltage drop of 0.2 V when conducting a 1which can be considered conducting a good 1 as by itself this drop is small. Note that f = x7x6 .. x1x0
Vdd=3v x7 x6 x5 x4 x3 x2

x1

x0

0.2 V

0.2 V

0.2 V

0.2 V

0.2 V

0.2 V

0.2 V

0.2 V

f
Vop=1.4V when f=1; not a reliable logic 1 voltage (probably in no-mans land)

Corresponding compl. n/w (f=x7+x6+.+x1+x0)

GND

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Problem with Large Switching Networks (contd)

The solution is using a number of smaller switching n/ws, so that the deterioration of the signal (1 or 0 logic value) is small. Further, each small n/w replenishes the logic value at its o/p from Vdd or GND in spite of the (small) deterioration of the signal at its inputs (assuming these come from other n/ws). Thus any deterioration from previous n/ws do not propagate to subsequent n/ws in the circuit, and such deterioration is in fact corrected in n/ws fed by slightly deteriorated signals coming from other n/ws Thus we need to break down a large function (function w/ many variables generally > 6) into smaller ones that can each be implemented using smaller n/ws. This happens to a large extent when a function is represented as an SOP or POS expression (it is lready broken down into ANDs and ORs) but not always (e.g., an AND or OR term may have a large # of vars). E.g., the 8-i/p NOR function f can be decomposed as (and then impl as beow):
f = [(x7+x6+x5+x4) + (x3+x2+x1+x0)] = [(x7x6x5x4) + (x3x2x1x0)] = NOR(NAND(x7,x6,x5,x4), NAND(x3,x2,x1,x0))

Vdd=3V

x7 x6 x5 x4 0.2 V

Vdd=3V

x3 x2 x1 Vdd x0 0.2 V 0.2 V

x7 x6 x5 x4

h
x3 x2 x1 x0

g f h

g (=2.8V for 1)
GND

0.2 V
Compl n/w for h

(=2.6V for 1)

GND

Compl n/w for g

(=2.8V for 1)

GND

Compl n/w for NOR

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Problem with Large Switching Networks (contd)

These small switching networks are called gates Thus need to use gates to implement large logic functions

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Copyright: Shantanu Dutt