Dependence of the Propagation Delay of Silicon Nanowire Metal-Oxide-Semiconductor Field-Effect Transistors on Some Important Parameters

Subindu Kumar
(subindukumar@hotmail.com) &

Dharamvir Kumar
(dharamvir_kumar2007@yahoo.co.in)

Department of Electronics Engineering Indian School of Mines Dhanbad, Jharkhand India

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INTRODUCTION
In recent years, Silicon nanowire (SiNW) metal-oxidesemiconductor field-effect transistors (MOSFETs) has emerged as one of the most promising structures to extend the scaling of CMOS devices. In addition to the effective suppression of short channel effects, the SiNW MOSFETs with multiple gates show excellent current drive and they are also compatible with conventional CMOS processes. Recently, CMOS compatible multi channel SiNW MOSFETs having diameters 5 nm have been demonstrated with excellent performance. Due to the enhanced electronic properties of nanowires, SiNW based inverters show better performance than their planar counterpart.
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INTRODUCTION
As one of the most important performance parameters in CMOS digital circuits, propagation delay is of concern to designers and users. Both the speed/frequency and dynamic power dissipation of a circuit are affected by propagation delay, so timing analysis has been investigated for several decades. There is no well-established compact model to capture the transient characteristics of circuits based on ultrasmall nanoscale devices.

In this paper, we first discuss a simple method for calculating the average propagation delay in SiNW based CMOS inverters and then show the dependence of the propagation delay of these inverters on some important parameters, such as, thickness of the oxide (insulator), wire dimension, number of channels, and so on, for different load capacitances.
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THEORETICAL DETAILS
The drain current, ID of a coaxially gated SiNW MOSFET, under non-degenerate carrier statistics can be expressed as:

where COX is the oxide capacitance per unit length, vT is the unidirectional thermal velocity given by (2kBTL/m*)1/2 and other symbols have their usual meanings. COX is related to the oxide thickness (TOX) and Si wire diameter (Dwire) as:

[Mark Lundstrom, and Jing Guo, Nanoscale Transistors : Device Physics, Modeling and Simulation Springer(India)
Private Limited, 2008. ]
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THEORETICAL DETAILS
In eq. (1) it has been assumed that the quantum capacitance (CQ) >> COX . Due to the finite quantum energy level spacing of electrons in nanowires, it costs energy to add an electron to the system. By equating this energy cost with an effective quantum capacitance q2/CQ, one arrives at the following expression for the (quantum) capacitance per unit length:

[P. J. Burke, IEEE Trans. Nanotechnology, vol. 1, no. 3, pp. 129-144, Sep. 2002.]

In order to include the effect of CQ in eq. (1), COX has to be replaced by the equivalent capacitance of two series connected capacitors COX and CQ. In this work, we have chosen the number of n-MOS and pMOS nanowire channels in the ratio of 1:2 to achieve symmetry in rise and fall times at the output.
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THEORETICAL DETAILS

Fig.1 A CMOS inveter utilizing two coaxially gated SiNW MOSFETs

CL is the load capacitance which includes the parasitic output capacitance of the inverter, the interconnect capacitance and the gate capacitance of the next stage inverter.

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THEORETICAL DETAILS
The propagation delay, tp of a CMOS inverter is given by: tp= (tPHL + tPLH)/2 Where (4)

tPHL = ln(2).n is the output fall time from VDD to VDD/2 tPLH = ln(2).p is the output rise time from 0 V to VDD/2

And

n(p) = Ravg,n(p).CL is the time constant related to the discharging (and charging) of the n-MOS(p-MOS) respectively, and Ravg, n(p) = Average resistance offered by the n-MOS (pMOS) during the discharging(and charging) of the load capacitance.
[John P. Uyemura, Introduction to VLSI Circuits and Systems, Wiley India, 2006.]

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RESULTS AND DISCUSSIONS

Variation of Propagation delay with oxide thickness
There is a monotonic increase in the propagation delay time with the increase in load capacitance. Validation : The delay computed for an oxide thickness of 10 nm and wire diameter of 5 nm is 57.4 ps(CL=50 fF), which is 6.6 ps lower than the value reported by Buddharaju et al.

Fig. 2 Dwire=5 nm, VT=0.3 V, N=40(for nMOS)

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RESULTS AND DISCUSSIONS

Variation with Wire diameter

We see that the propagation delay decreases with increase in the wire diameter.

The load capacitance has a direct effect on propagation delay.

Fig. 3 TOX=1 nm, VT=0.3 V

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RESULTS AND DISCUSSIONS

Variation with Quantum capacitance
For a fixed value of the wire diameter and oxide thickness, the inclusion of quantum capacitance increases the propagation delay time. This result is expected since inclusion of the quantum capacitance decreases the drain current, thus increasing the average channel resistance and the propagation delay.

Fig. 4 Propagation delay considering the effect of quantum capacitance, CL=50 fF, TOX=1 nm
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RESULTS AND DISCUSSIONS

Variation with no. of nMOS channels(N)
The number of p-MOS channels is also changed accordingly in order to maintain equal fall and rise times.

Propagation delay decreases rapidly with the increase in the no. of channels.

This is because, the current driving capability is directly proportional to the no. of channels.
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Fig. 5 Propagation delay vs no. of nMOS channels(N), TOX=10 nm, Dwire=5 nm

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RESULTS AND DISCUSSIONS

Variation with Threshold voltage

=0 =1

fixed threshold voltage varying threshold voltage

Fig. 6 Propagation delay considering the effect of threshold voltage, VTH/Dwire = 35 mV/nm , TOX=1 nm N. Singh et al., International Electron Devices Meeting, San Francisco, pp.1-4, Dec. 2006.

We see that as we change the threshold voltage with the wire diameter, there is a slight improvement in the propagation delay.
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SUMMARY
We have investigated the effects of some important parameters such as, SiNW diameter, oxide thickness, quantum capacitance and number of channels on the propagation delay of CMOS compatible SiNW based inverters. The variation of the propagation delay with the threshold voltage is also studied.

It was found that the delay decreases significantly if the number of channels in each n and p-MOS structure increases. The results obtained are in line with the bench marking data and could be useful for researchers working in this field.

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THANK YOU

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