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Dr. V. Kpuska
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The UART includes interrupt handling hardware. Interrupts can be generated from 12 different events.
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The DMA method requires minimal software intervention as the DMA engine itself moves the data. See Chapter 9 of HRM, Direct Memory Access for more information on DMA.
Either one of the peripheral timers can be used to provide a hardware assisted autobaud detection mechanism for use with the UART. See Chapter 15 of HRM, Timers, for more information.
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Serial Communication
The UART follows an asynchronous serial communication protocol with these options:
5 8 data bits 1, 1, or 2 stop bits None, even, or odd parity Baud rate = SCLK/(16 Divisor), where SCLK is the system clock frequency and Divisor can be a value ranging from 1 to 65536
All data words require a start bit and at least one stop bit. With the optional parity bit, this creates a 7- to 12-bit range for each word. The format of received and transmitted character frames is controlled by the Line Control register (UART_LCR). Data is always transmitted and received least significant bit (LSB) first.
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Data Bits B0 B1 B2 B3 B4 B5 B6 B7
Stop Bit
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UART_THR Register
All data words begin with a 1-to-0-transition start bit.
The transfer of data from UART_THR to the Transmit Shift register (TSR) sets the Transmit Holding Register Empty (THRE) status flag in the UART Line Status register (UART_LSR).
The write-only UART_THR register is mapped to the same address as the read-only UART_RBR and UART_DLL registers.
To access UART_THR, the DLAB bit in UART_LCR must be cleared. When the DLAB bit is cleared,
writes to this address target the UART_THR register, and reads from this address return the UART_RBR register.
Note data is transmitted and received least significant bit (LSB) first (bit 0) followed by the most significant bits (MSBs).
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UART_RBR Register
Sampling Clock Issues:
A sampling clock equal to 16 times the baud rate samples the data as close to the midpoint of the bit as possible. Because the internal sample clock may not exactly match the asynchronous receive data rate, the sampling point drifts from the center of each bit. The sampling point is synchronized again with each start bit, so the error accumulates only over the length of a single word. A receive filter removes spurious pulses of less than two times the sampling clock period.
The read-only UART_RBR register is mapped to the same address as the write-only UART_THR and UART_DLL registers. To access UART_RBR, the DLAB bit in UART_LCR must be cleared.
When the DLAB bit is cleared,
writes to this address target the UART_THR register, while reads from this address return the UART_RBR register.
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UART_IER Register
Non DMA data transfers Setting this register without enabling system DMA causes the UART to notify the processor of data inventory state by means of interrupts. For proper operation in this mode, system interrupts must be enabled, and appropriate interrupt handling routines must be present. For backward compatibility, the UART_IIR still reflects the correct interrupt status. Important Note: The UART features three separate interrupt channels to handle data transmit, data receive, and line status events independently, regardless whether DMA is enabled or not.
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UART_IER Register
DMA data transfers With system DMA enabled, the UART uses DMA to transfer data to or from the processor. Dedicated DMA channels are available to receive and transmit operation. Line error handling can be configured completely independently from the receive/transmit setup. The UART_IER register is mapped to the same address as UART_DLH. To access UART_IER, the DLAB bit in UART_LCR must be cleared.
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When a UART interrupt is pending, the interrupt service routine (ISR) needs to clear the interrupt latch explicitly. The following figure (next slide) shows how to clear any of the three latches. The TX interrupt request is cleared by
writing new data to the UART_THR register or by reading the UART_IIR register.
Please note the special role of the UART_IIR register read in the case where the service routine does not want to transmit further data.
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Important Note:
If either the Line Status interrupt or the Receive Data interrupt has been assigned a lower interrupt priority by the SIC, a deadlock condition can occur. To avoid this, always assign the lowest priority of the enabled UART interrupts to the UART_THR empty event. Because of the destructive nature of these read operations, special care should be taken. For more information, see Speculative Load Execution on page 6-69 and Conditional Load Behavior on page 6-70.
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The 16-bit Divisor formed by UART_DLH and UART_DLL resets to 0x0001, resulting in the highest possible clock frequency by default. If the UART is not used, disabling the UART clock will save power. The UART_DLH and UART_DLL registers can be programmed by software before or after setting the UCEN bit.
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UART_GCTL Register
The IrDA TX Polarity Change bit and the IrDA RX Polarity Change bit are effective only in IrDA mode. The two force error bits, FPE and FFE, are intended for test purposes. They are useful for debugging software, especially in loopback mode.
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No additional buffering is provided in the UART DMA channel, so the latency requirements are the same as in non-DMA mode. However, the latency is determined by the bus activity and arbitration mechanism and not by the processor loading and interrupt priorities. For more information, see Chapter 9, Direct Memory Access.
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Depending on whether DMA is enabled or not, upon receiving these requests, the DMA control unit either
generates a direct memory access or passes the UART interrupt on to the system interrupt handling unit. However, the UARTs error interrupt goes directly to the system interrupt handling unit, bypassing the DMA unit completely.
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SPORTs,
SPI port,
UART, and PPI.
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The processor has multiple, independent DMA controllers that support automated data transfers with minimal overhead for the core. DMA transfers can occur between
the internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including the SDRAM controller and the asynchronous memory controller. DMAcapable peripherals include the
SPORTs, SPI port, UART, and PPI.
Each individual DMA-capable peripheral has at least one dedicated DMA channel.
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DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks.
The 2D DMA capability supports arbitrary row and column sizes up to 64K x 64K elements, and arbitrary row and column step sizes up to +/- 32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be deinterleaved on the fly.
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UART RS-232
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// Configure the UART DMA parameter registers // Transmit DMA *pDMA7_START_ADDR = tx_buffer; *pDMA7_X_COUNT = BUFFER_SIZE; *pDMA7_X_MODIFY = 1;
// Autobuffer DMA Continously transmit the data *pDMA7_CONFIG = 0x1081;
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DMA Configuration
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// Configure the UART DMA parameter registers // Transmit DMA *pDMA7_START_ADDR = tx_buffer; *pDMA7_X_COUNT = BUFFER_SIZE; *pDMA7_X_MODIFY = 1;
// Autobuffer DMA Continously transmit the data *pDMA7_CONFIG = 0x1081;
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// Configure the UART DMA parameter registers // Transmit DMA *pDMA7_START_ADDR = tx_buffer; *pDMA7_X_COUNT = BUFFER_SIZE; *pDMA7_X_MODIFY = 1;
// Autobuffer DMA Continously transmit the data *pDMA7_CONFIG = 0x1081;
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Transmit_uart_533.c
/******************************************************* This example code tests the UART using the stop mode DMA across two kits. This code is the transmitter code. *******************************************************/ #include #include #include #include <CdefBF533.h> <defBF533.h> <signal.h> <sys/exception.h>
#define BUFFER_SIZE 16 /******************************************************* Function declarations *******************************************************/ void setup_UART(); void setup_interrupts(); /******************************************************* ISR declarations *******************************************************/ EX_INTERRUPT_HANDLER(transmit_isr); /******************************************************* Variable declarations *******************************************************/ char tx_buffer[BUFFER_SIZE]; volatile unsigned int tx_cnt = 0;
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// Configure the UART DMA parameter registers // Transmit DMA *pDMA7_START_ADDR = tx_buffer; *pDMA7_X_COUNT = BUFFER_SIZE; *pDMA7_X_MODIFY = 1;
// Autobuffer DMA Continously transmit the data *pDMA7_CONFIG = 0x1081;
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// Configure the UART DMA parameter registers // Transmit DMA *pDMA7_START_ADDR = tx_buffer; *pDMA7_X_COUNT = BUFFER_SIZE; *pDMA7_X_MODIFY = 1;
// Autobuffer DMA Continously transmit the data *pDMA7_CONFIG = 0x1081;
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// Configure the UART DMA parameter registers // Transmit DMA *pDMA7_START_ADDR = tx_buffer; *pDMA7_X_COUNT = BUFFER_SIZE; *pDMA7_X_MODIFY = 1;
// Autobuffer DMA Continously transmit the data *pDMA7_CONFIG = 0x1081;
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*pDMA7_CONFIG = 0x1081
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*pUART_DLH = 0x0000
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Boud-Rate
BAUD RATE = SCLK/(16 x Divisor)
SCLK/(16x255) = SCLK/4096 SCLK = 100 MHz BAUD RATE = 100 MHz /4096 = 24414.0625 bps
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DMA Configuration
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Receive_uart_533.c
/******************************************************* This example code tests the UART using the stop mode DMA across two kits. This code is the receiver code. *******************************************************/ #include <CdefBF533.h> #include <defBF533.h> #include <signal.h> #include <sys/exception.h> #define BUFFER_SIZE 10000 /******************************************************* Function declarations *******************************************************/ void setup_UART(); void setup_interrupts(); /******************************************************* ISR declarations *******************************************************/ EX_INTERRUPT_HANDLER(receive_isr); /*********************** ******************************** Variable declarations *******************************************************/ char rx_buffer[BUFFER_SIZE]; volatile unsigned int rx_cnt = 0;
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*pDMA7_CONFIG = 0x0083
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*pUART_DLH = 0x0000
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Boud-Rate
BAUD RATE = SCLK/(16 x Divisor)
SCLK/(16x255) = SCLK/4096 SCLK = 100 MHz BAUD RATE = 100 MHz /4096 = 24414.0625 bps
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END