IF-3531

Pengantar Arsitektur Komputer

PENDAHULUAN

FULL ADDER 1 - Bit

MULTIPLIER 2/4 - Bit

ALU 1 - Bit

ALU 1-Bit and Table

Representasi ALU

ALU 1-bit

ALU 1-bit

ALU 1-bit

ALU 1-bit

ALU 1-bit

ALU 1-bit

ALU 1-bit

ALU 1-bit

Simbol ALU

ALU

CPU and Internal Bus

CPU - Internal Architecture System

MQ : Multiplier Quotient MBR : Memory Buffer Register

Central Processing Unit (CPU)

Arithmetic and Logic Unit
Accumulator

MQ

Arithmetic & Logic Circuits

Input Output Equipment

MBR Instructions & Data

Main Memory

IBR

PC MAR

IR

Control Circuits

Address Program Control Unit

IBR MBR PC IR MAR MQ : Instruction Buffer Register : Memory Buffer Register : Program Counter : Instruction Register : Memory Address Register : Memory Queue

Computer Components
Top Level View

Three Memory Management Model

Basic Execution Environment Intel 32 bit

Model Instruksi
Two Step

Simplified CPU Block Diagram

i-CACHE

CODE CACHE
Data Bus

INSTRUCTION POINTER

INSTRUCTION DECODER
Memory
CODE

CONTROL UNIT

Register Set
DATA

ALU

ALU FLOATING POINT UNIT

DATA CACHE
Addres Bus d-CACHE

Instruction Execution Cycle

Fetch: Control Unit mengaktifkan instruction berikutnya yang ada dalam antrian instruksi (instruction queue) dan menaikkan angka penunjuk pointer instruksi IP kadang disebut dengan istilah lain program counter (PC). Decode: Control Unit memeriksa code instruksi (Decode) yang artinya untuk mengetahui apa yang ingin dilakukan oleh code instruksi tsb. Code instruksi kemudian dilepas ke ALU, dengan melepas signal tertentu ke ALU yang mengindijasikan operasi ALU yang harus dikerjakan. Fetch operands: Jika code instruksi memiliki operand yang berlokasi di memory, Control Unit beraksi membaca dan mengambil operand dan mengcopy ke internal registers processor. Execute: ALU mengksekusi instruction, internal registers berisi operand dan hasil operasi ALU, dapat pula hasil ALU disimpan ke memory. ALU mengupdate status ags untuk menyediakan info bagi OS atau User tentang processor state. Store output operand: If the output operand is in memory, the control unit uses a write operation to store the data.

Model Instruksi
Multi Step

Instruction Fetch

Operand Fetch

Operand Store

MEMORY CPU
Instruction Address Calculation Instruction Operation Decoding Multiple Operand Multiple Operand

Operand Address Calculation

Data Operation

Operand Address Calculation

Return for String or vector data

Instruction Complete Fetch Next Instruction

Processor Instructions Set

Instruction Set : ada 3 Class yang umum
1. Data movement instructions
Move data from a memory location or register to another memory location or register without changing its form Loadsource is memory and destination is register Storesource is register and destination is memory Change the form of one or more operands to produce a result stored in another location Add, Sub, Shift, etc. Alter the normal flow of control from executing the next instruction in sequence Br Loc, Brz Loc2,unconditional or conditional branches

2. Arithmetic and logic (ALU) instructions

3. Branch instructions (control flow instructions)

ALU Instruction
Instruction MULF A, B, C nabs r3, r1 ori $2, $1, 255 DEC R2 SHL AX, 4 Meaning multiply the 32-bit floating point values at mem locns. A and B, store at C Store abs value of r1 in r3 Store logical OR of reg $ 1 with 255 into reg $2 Decrement the 16-bit value stored in reg R2 Shift the 16-bit value in reg AX left by 4 bit posns. Machine VAX11 PPC601 MIPS R3000 DEC PDP11 Intel 8086

Data Movement Instruction

Instruction MOV A, B LDA A, Addr LWZ R3, A LI $3, 455 MOV R4, dout IN AL, KBD LEA. L (A0), A2 Meaning Move 16 bits from memory location A to Location B Load accumulator A with the byte at memory location Addr Move 32-bit data from memory location A to register R3 Load the 32-bit integer 455 into register $3 Move 16-bit data from R4 to output port dout Load a byte from in port KBD to accumulator Load the address pointed to by A0 into A2 Machine VAX11 M6800 PPC601 MIPS R3000 DEC PDP11 Intel Pentium M6800

Branch Instruction
Instruction BLSS A, Tgt bun r2 beq $2, $1, 32 SOB R4, Loop JCXZ Addr Meaning Branch to address Tgt if the least significant bit of mem locn. A is set (i.e. = 1) Branch to location in R2 if result of previous floating point computation was Not a Number (NAN) Branch to location (PC + 4 + 32) if contents of $1 and $2 are equal Decrement R4 and branch to Loop if R4 0 Jump to Addr if contents of register CX 0. Machine VAX11 PPC601 MIPS R3000 DEC PDP11 Intel 8086

Format dan pseudo code Instruksi, BERBEDA antar masing-masing mesin prosessor. Namun beberapa pabrikan Processor yang berbeda kadang-kadang menyepakati satu model ISA tertentu.

Simplified CPU Block Diagram

i-CACHE

CODE CACHE
Data Bus

INSTRUCTION POINTER

INSTRUCTION DECODER

CONTROL UNIT

Register Set

Memory
CODE

ALU

ALU FLOATING POINT UNIT

DATA

DATA CACHE
Addres Bus d-CACHE

Format ISA
n bit m bit ; n < m

opcode

Operand Address

Opcode : jenis instruksi operasi processor Operand Address : Alamat Operand ( Register atau Memory ) Jumlah operand address ISA yang dikenal adalah :
4 Address 3 Address 2 Address 1 Address 0 Address

4 Address ISA
n bit 4 x m bit

opcode Contoh : ADD

OpAdd1

OpAdd2

OpAdd3

OpAdd4

R3, R1, R2, R4

artinya : R3 R1 + R2

R1, R2, R3, dan R4 adalah Register Biasanya digunakan dengan urutan sebagai berikut : R3 R1 + R2 R4 berisi alamat instruksi berikutnya (PC PC + 1)

3 Address ISA
n bit 3 x m bit

opcode Contoh : SUB

OpAdd1

OpAdd2

OpAdd3

R3, R1, R2

artinya : R3 R1 R2

2 Address ISA
n bit 2 x m bit

opcode Contoh : MOV R1, R2

OpAdd1

OpAdd2

artinya : salin isi R2 ke R1 : R1 R2

Untuk menghtung : R3 R1 * R2, digunakan dengan urutan sebagai berikut : MOV R3, R1 MUL R3, R2 jika diperhatikan perintahnya menjadi 2 baris .!

1 Address ISA
n bit 4 x m bit

opcode Contoh : MUL R4

Operand Address

Bagaimana dengan : R3 R1 + R2 LOAD R1 ADD R2 STORE R3 perhatikan jumlah instruksi menjadi 3 baris

0 Address ISA
n bit

opcode

Contoh : C A + B
PUSH A PUSH B ADD POP C

Machine View 4 Address

Machine View 3 Address

Machine View 2 Address

Machine View 1 Address

Machine View 0 Address

Instruction Set Principles

(a) Stack TOS Stack Accumulator (b) Accumulator (c) Register-Memory (d) Reg-Reg/Load-Store (e) Memory-Memory

Reg. Set

Reg. Set

ALU

ALU

ALU

ALU

ALU

Memory

Memory

Memory

Memory

Memory

Push A Push B Add Pop C

Load A Add B Store C

Load R1,A Add R3,R1,B Store R3,C

Load R1,A Load R2,B Add R3,R1,R2 Store R3,C

Add C,A,B

Y = (A-B)/(C+D*E)

3 Op Address
SUB Y,A,B MUL T,D,E ADD T,T,C DIV Y,Y,T

2 Op Address
MOV Y,A SUB Y,B MOV T,D MUL T,E ADD T,C DIV Y,T

1 Op Address
LOAD D MUL E ADD C STORE Y LOAD A SUB B DIV Y STORE Y

0 Op Address
PUSH A PUSH B SUB PUSH C PUSH D PUSH E MUL ADD DIV POP Y