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Microcontrollers & Embedded Systems

The 8051 Microcontroller


Sudipta Mahapatra, Ph.D. Department of E & ECE IIT Kharagpur

Module-2 : The 8051 Microcontroller


Overview of 8051 family; Architecture of 8051; Programming model, Instruction set, Addressing modes; 8051 programming in C.

Book: 1. The 8051 Microcontroller and Embedded Systems Using Assembly and C, Mazidi M. A.. 2. Microcontrollers Principles and Applications, Ajit Pal 3. Embedded System Design, Santanu Chattopadhyay
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8051
Is an 8-bit microcontroller.
4 KB 128 Bytes

30 pF

30 pF
1.24-12 MHz
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8051 Features
ROM 4K Bytes RAM 128 Bytes Timer 2 I/O Pins 32 (P0 to P3) Serial Port 1 Interrupt sources 6

Other Family members

8051 Register Organization


General purpose: 4 banks of 8-bit registers (R0-R7) RAM address 00 07H; 08H-0FH; 10H-17H; 18H-1FH Special function register: A (8) ACC; B (8) : Commonly used during / operation DPH and DPL (16) : Data pointer registers used for external memory access Stack pointer - SP (8) P0 P3 (8): I/O port registers Timer/Counter Registers: TMOD, TCON, TH0, TL0, TH1, TL1 : Hold the count values of the two on-chip timers/counters 6

Memory Organization
Has separate program memory and data memory. Program memory: 4 KB on-chip memory; provision of having 64KB external program memory. For EA=1, access internal memory from 0000-000FH and external memory for higher addresses. If its 0, all instructions are accessed from the external memory only.
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Data Memory
128 bytes of on-chip RAM and the 21 SFRs. There is provision for having 64 KB external data memory.

8051

RAM Allocation in 8051

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Register banks and RAM addresses

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8051 SFRs
Address Range RAM locations 80H to FFH Serial port registers: SCON Control Register, SBUF(Tx), SBUF(Rx) hold the serial data to be output/input. Interrupt Control: IE (Interrupt enable), IP (interrupt priority) PSW Register: Flag bits; Register bank selection bits; Parity bit (0/1 E/O)

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8051 SFRs
PSW Register

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8051 Special Function Registers

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8051 Special Function Registers (Contd.)

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Pin Diagram

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Pin Diagram

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Multifunction I/O ports


32 out of 40 pins are used to provide 4 I/O ports (P0P3) These are used - As parallel bidirectional I/O ports (P0, P1 -To interface with internal memory - As timer/counter - As serial ports - For interrupt processing The ports are initialized as input ports Write the first zero - becomes an output port Write an one becomes input port
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Port functionality
http://www.mikroe.com/eng/chapters/view/65/chapter2-8051-microcontroller-architecture/ P0: Used to output the lower order address byte (A0A7) when external memory is interfaced; otherwise, acts as simple I/O port. No pull up resistor. P1: Used as a simple I/O port. Has pull up resistor. P2: Used to output the higher order address byte (A8-A15) when external memory is interfaced; otherwise, acts as simple I/O port. Has pull-up resistor. P3: Used as simple I/O ports or alternate functions. Has a pull-up resistor. 19

Port lines

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Schematic of Port 0

P0 can sink the current of eight LS TTL loads (~3.2mA)

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LS-TTL Unit Load Low power schottky

Schematic of Port 1

P1, P2 and P3 can sink/source three LS TTL loads


(~1.2mA)

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Schematic of Port 2

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Schematic of Port 3

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ALU Capability
Arithmetic Operation: ADD, INC, DEC, CMPZ, DEC and CMPZ, SUBwith-Borrow, MUL, DIV Logical Operation: AND, OR, EX-OR, RL, RLC, RR, RRC, Swap Nibbles within ACC Boolean Processor- Provides rich bit manipulation capability, including Set, Clear, Complement, J-if-Set, Jif-NSet, J-if-Set-then-Clear. These operations can be performed on a part of the data RAM (128 bits) and 128 bits within the SFRs.
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Bit addressable RAM and Registers


Registers

P0-P3, A, B, PSW,IP,IE ACC, SCON, TCON

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Bit addressable SFRs

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Reset Operation
Hold the RST pin to a high level for at least 2 cycles Power-on reset - can be implemented by connecting a 10 uF capacitor between RST pin and ground.
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Interrupt Structure
External Interrupt (2) Generated by external sources through and . Internal Interrupt (3) From the on-chip functional units

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Interrupt Priority
Set by writing to the special function interrupt priority register (IP).
Bits 7 X 6 X 5 X 4 3 2 1 0 PS PT1 PX1PT0 PX0

PS: Serial port priority level (1/0) PT1/PT0: Timer (1/0) Interrupt Priority level (1/0) PX1/PX0: External Interrupt 1/0 Priority level (1/0) Internal polling sequence selects the interrupt to be serviced if priority is same for received interrupts INT0 > T0 > INT2 > T1 > Serial port
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Interrupt Masking
IE Register used to enable or disable interrupts Bits 7 6 5 4 3 2 1 0 EA X X ES ET1 EX1 ET0 EX0 EA=0 Disable all the interrupts; EA=1 set or reset the corresponding masking bit to enable (=1) or disable (=0) an interrupt. Bits 7 6 5 4 3 2 1 0 EA X X ES ET1 EX1 ET0 EX0 Serial port Timer External Intr.
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Interrupt Structure (Contd.)


INT0 and INT: External interrupt; Low level sensitive; Must be active for at least 12 CC to be sensed by the processor; REI instruction at the end of the ISS deactivates this signal. Can be configured in edge-triggered (high-low) mode by setting the IT0 or IT1 bits in the TCON register.

TCON register:

Bits 7 6 5 4 3 2 1 0 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 If IT0/IT1=1, IE0/IE1 is set by H/W when 1-0 transition is detected on INT0 or INT1.

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Event sequence
Initialization: Configure different components/ registers by appropriate values. Polling: After initialization, application program is executed. Active interrupts are checked as per the assigned priority levels and are serviced.

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