ARM Processors (Advanced RISC Machines)

G N V Ratnakishor

Introduction to 16/32 bit processors

A 32-bit processor with an instruction set facilitating a subset of instructions for 16-bit coding is called 16/32-bit processor ARM has 32-bit instruction set supported by a 16bit compressed code, called Thumb instruction set. MCUs based on ARM architecture provides the following
Precise computing Minimum power dissipation Smaller code-size for given computations

 Applications
Mobile phones Image processing Video games Robotics Adaptive control systems

 ARM uses RISC superscalar processor architecture Processor retains the best of CISC features also. ARM architectures are used as core or chip.

ARM basic features

1. RISC feature 2. 32-bit ARM CISC like instruction set implemented with low power dissipation 3. 16-bit Thumb extension for low code density 4. Multiple variants

 ARMs RISC features

Same length instructions Single cycle execution due to three-stage pipeline. Hardwired implementation Large register set Load-Store architecture

 Three stage pipeline

 ARM variants
1. 2. 3. 4. 5. 6. v1 ARM1 v2 ARM2 v2as ARM3, and ARM250 v3 ARM6, ARM7, and ARM8 v4 Strong ARM, and ARM9 v6 ARM10

Processor modes

ARM register set

ARM has 37 registers all of which are 32-bits long

1 dedicated program counter 1 dedicated current program status register (CPSR) 5 dedicated saved program status registers (SPSR) 30 general purpose registers.
A particular set of r0-r12 registers A particular r13 (SP) and r14 (link register, lr) The program counter (PC) The current program status register (CPSR)

Each mode can access

ARM/THUMB programming model

Overview of the memory organization in ARM family MCUs.
ARM

Princeton Architecture (ARM7)

Harvard Architecture (ARM9)

Word(32-bits) (B3-B2-B1-B0) B0 B1

Address 0
Address 1 Address 2 Address 3

B3 B2

B2 B3
Little endian

B1 B0
Big endian

 ARM processor operates on 32-bit words at an instance and can also operate separately on each byte or on half words. When used in relation to the ARM:
Byte means 8 bits Halfword means 16 bits (two bytes) Word means 32 bits (four bytes)

 CPU architecture

 RALU (Register Arithmetic Logic Unit)

Three address machine with two source operands and one destination operands. Source 1: one of the source operands from a register. Source 2:
Can be either from register+memory, or from register, or an immediate operand. Can also be first operand with rotate or shift instructions.

Result is stored in destination register.

IR (Instruction Register)
Holds the current instruction byte

ID (Instruction Decoder)
Decode the IR byte and activate the appropriate signals for hardwired implementation of instruction at IR.

 Conditional Test and Branch Logic

Additional circuit to test the flags and initiate appropriate program flow path by branching.

CSPR
Current Program Status Register for each mode Conditional code flags: N(Negative flag), Z(Zero flag),C(Carry flag), and V(Overflow flag) T bit : 0 for ARM state 1 for Thumb state

SPSR
Saved Program Status Word Saves program status register from CPSR on branch and link(routine call) SPSR is stacked for each processor mode

32-bit MAC
Needed for DSP and control applications

Instruction set
Conditional execution and flags:
ARM instructions can be made to execute conditionally by post fixing them with the appropriate condition code field.

 By default, data processing instructions do not affect condition code flags but the flags can be optionally set by using s.

CMP does not need s

 Branch instructions

An unconditional jump: LABEL . .. B LABEL

; unconditional branch

 Data processing instructions:

 Multiply instructions: