FET ( Field Effect Transistor)

1. Unipolar device, yaitu bekerja tergantung hanya pada satu jenis

pembawa muatan (hole atau elektron)
2. Device dikendalikan tegangan (tegangan gate voltage
mengendalikan arus drain)
3. Input impedance sangat tinggi (~10
9
-10
12
O)
4. Source dan Drain bekerja saling mempengaruhi pada frekuensi
sangat rendah
5. Memungkinkan beroperasi pada tegangan rendah dan arus rendah
(konsumsi daya kecil)
6. Nois rendah dibandingkan dengan BJT
7. Tidak menyimpan pembawa minoritas (Turn off lebih cepat)
8. Self limiting device
9. Ukuran sangat kecil, sebagai implementasi kesesuaian dengan
ukuran IC sangat kecil kapasitas besar
10. Memungkinan beroperasi pada arus rendah dan tegangan rendah
dalam MOSFET
11. Memungkinkan terjadi aliran pada temperatur nol
Keuntungan/kelebihan FET dari transistor bipolar:
Beberapa Jenis dari Field Effect Transistor (klasifikasi)
JFET
MOSFET (IGFET)
n-Channel JFET
p-Channel JFET
n-Channel
EMOSFET
p-Channel
EMOSFET
Enhancement
MOSFET
Depletion
MOSFET
n-Channel
DMOSFET
p-Channel
DMOSFET
FET
n-Channel JFET.
Junction Field Effect Transistor (JFET)
Gate
Drain
Source
LAMBANG / SYMBOLS
n-channel JFET
Gate
Drain
Source
n-channel JFET
Offset-gate symbol
Gate
Drain
Source
p-channel JFET
n-Channel JFET dan pembiasan rangkaian
Pembiasan JFET
Daerah deplesi nonconductif menjadi mengembang dengan ditingkatkanya reverse bias.
(Cat: dua daerah gate dari setiap FET dihubung satu sama lain.)
Operasi dari JFET pada variasi Potensial Gate Bias
P P
+
-
+
-
+
-
N
N
Operasional JFET
Gate
Drain
Source
rangkaian untuk karaktersitik drain dari n-channel JFET dan Karakteristik Drain.
Daerah non-saturasi (Ohmic) :

Arus drain dinyatakan dengan

(
(
(

|
.
|

\
|
=
2
2
2
2
DS
DS P GS
P
DSS
DS
V
V V V
V
I
I
(
(

|
.
|

\
|
=
2
2
P GS
P
DSS
DS
V V
V
I
I
2
1 and
|
|
|
.
|

\
|
=
P
GS
DSS DS
V
V
I I
Dimana, I
DSS
adalah short circuit arus drain , V
P
tegangan pinch off
Keluaran atau Drain (V
D
-I
D
) Karakteristik dari n-JFET
Daerah saturasi (atau Pinchoff):
|
.
|

\
|
<
P GS DS
V V V
|
.
|

\
|
>
P GS DS
V V V
n-Channel FET untuk v
GS
= 0.
Simple Operasional dan Breakdown pada n-Channel JFET
Jika v
DG
diatas tegangan breakdown V
B
, arus drain meningkat secara cepat.
Daerah Break Down
Karakteristik dan Breakdown N-Channel JFET
Figure: Typical drain characteristics of an n-channel JFET.
V
D
-I
D
Karakteristik EMOS FET
Pinch off atau
daerah saturasi
Locus dari pts dimana ( )
P GS DS
V V V =
Mutual Karakteristik n-Channel JFET
2
1
|
|
|
.
|

\
|
=
P
GS
DSS DS
V
V
I I
I
DSS
V
GS (off)
=V
P
Transfer (Mutual) Characteristic pada n-Channel JFET
Kurva transfer JFET yang menunjukan
grafik nilai I
D
untuk setiap V
GS
yang diberikan

Rangkaian Bias untuk JFET
Rangkaian bias fixed
Self bias circuit
Rangkaian bias pembagi tegangan
Rangkaian bias JFET (n-channel)
2
1
|
|
|
.
|

\
|
=
P
GS
DSS DS
V
V
I I
0 , = = = + =
G GS GS G G GG
I Fixed V V R I V
D DS DD DS
P
GS
DSS DS
R I V V
V
V
I I
=
|
|
.
|

\
|
=
dan
1
2
S
GS
DS
S DS GS
R
V
I
R I V
=
= + 0
Untuk Self Bias Circuit
Untuk rangkaian bias fixed
Penerapan KVL pada gate diperoleh..
dan
dimana, V
p
=V
GS-off
& I
DSS
di short. I
DS
Penghitungan rangkaian bias JFET
atau Fixed Bias Ckt.
JFET Self (atau Source) Rangkaian Bias
2
1 and
|
|
|
.
|

\
|
=
P
GS
DSS DS
V
V
I I
S
GS
P
GS
DSS
R
V
V
V
I =
|
|
|
.
|

\
|

2
1
0 2 1
2
= +
(
(
(

|
|
|
.
|

\
|
+
S
GS
P
GS
P
GS
DSS
R
V
V
V
V
V
I
This quadratic equation can be solved for V
GS
& I
DS
Bias Pembagi Potensial (Tegangan)
0 1
2
=

|
|
|
.
|

\
|

S
GS G
P
GS
DSS
R
V V
V
V
I
DS GS
I V gives equation quadratic this Solving and
Penyederhanaan CS Penguat dan Variasi pada I
DS

dengan V
gs
Analisis FET Mid-frequency :
g
s
rd
gmvt
vi = vt
ii
io
vo
d
s
+ +
_
_
mid-frequency CE amplifier circuit
RD RL RTh vs

+

_

is
' ' o o i
vi m L L d D L vs vi
i s s i
i
i Th Th 1 2
i
Analysis of the CS mid-frequency circuit above yields:
v v Z
A = = -g R , where R = r R R A = = A
v v R + Z
v
Z = = R , where R = R R
i
(
(

L
o i
I vi
i L
o o
o d D P vi I
o i
seen by R
i Z
A = = A
i R
v p
Z = = r R A = = A A
i p
(
(

Penguat common source (CS) seperti pada
gambar disamping.
R
s
C
i
R
L
C
o
C
SS
v
i
v
o
+

+

v
s
+

_

_

_

i
o
i
i
D

S

G

V
DD

V
DD

R
1

R
SS

R
D

R
2

Rangkaian mid-frequency digambarkan sebagai berikut:
kopling kapasitor (C
i
dan C
o
) dan bypass kapasitor
(C
SS
) merupakan short circuit
short tegangan sumber DC (superposition)
tempatkan kembali FET dengan model hybrid-t
menghasilkan rangkaian mid-frequency seperti di
bawah.
Prosudur: Analysis dari penguat FET pada mid-frequency:
1) Dapatkan DC Q-point. Akan menunjukan bahwa FET beroperasi pada daerah
saturasi dan nilainya dibutuhkan untuk langkah selanjutnya.
2) Dapatkan g
m
. Jika g
m
tidak ditentukan, hitung dengan menggunakan nilai DC dari
V
GS
sebagai berikut:




3) Hitung nilaii-nilai yang dibutuhkan (seperti A
vi
, A
vs
, A
I
, A
P
, Z
i
, and Z
o
. gunakan
formula untuk pendekatan konfigurasi penguat (CS, CG, CD, dst).
( )
( )
DSS D
m GS P 2
GS P
D
m GS T
GS
GS
2I I
g = = V - V (for JFET's and DM MOSFET's)
V V
I
g = = V - V (for EM MOSFET's)
V
(Note: Uses DC value of V )
K
c
c
c
c
Latihan
Tentukan nilai-nilai mid-frequency : A
vi
, A
vs
, A
I
, A
P
,
Z
i
, dan Z
o
untuk penguat yang ditunjukan gambar
disamping. Anggap bahwa C
i
, C
o
, dan C
SS
besar.
Catatan bahwa rangkaian bias seperti ini nilai
V
GS
= -0.178 V.
Spesifikasi yang dimiliki JFET adalah:
I
DSS
= 4 mA, V
P
= -1.46 V, r
d
= 50 k
10 k
Ci
8 k
Co
CSS
vi
vo
+
+
vs
+

_
_
_
io
ii
D

S

G

18 V 18 V

800 k

2 k
500
400 k

Konfigurasi dan Relasi dari FET Amplifier
:
'
' ' m L
vi m L m L
'
m L
'
L d D L d D L SS L
i Th SS Th
m
o d D d D SS
m
i i i
vs vi vi vi
s i s i s i
i i i
I vi vi vi
L L L
P vi I vi I
CS CG CD
g R
A -g R g R
1 g R
R r R R r R R R R
1
Z R R R
g
1
Z r R r R R
g
Z Z Z
A A A A
R + Z R + Z R + Z
Z Z Z
A A A A
R R R
A A A A A
+
( ( (
( ( (

( ( (
( ( (

vi I
Th 1 2

A A
where R = R R
VCC
RD
S

R2
RSS
Rs
Ci
RL
Co
C2
vi
vo
+
+
vs
+
_
_
_
io
ii
Common Gate (CG) Amplifier
R1
D

G

Note: The biasing circuit is the same for each amp.
Rs
Ci
RL
Co
CSS
vi
vo
+
+
vs
+
_
_
_
io
ii
D

S

G

VDD

VDD

R1

RSS

RD

R2

Common Source (CS) Amplifier

R s
C i
v i
+
v s
+
_
_
i i
G

V DD

V DD

R 1

R SS

R 2

Common Drain (CD) Amplifier (also called source follower)

R L

C o

v o

+

_

i o

D

S

Symbol rangkaian untuk enhancement-mode n-channel MOSFET.
n-Channel Enhancement MOSFET menunjukan panjang L channel dan lebar W channel.
Untuk v
GS
< V
to
pn junction antara drain dan body adalah bias reverse dan i
D
=0.
Figure: For v
GS
>V
to
a channel of n-type material is induced in the region under the gate.
As v
GS
increases, the channel becomes thicker. For small values of v
DS
,i
D
is proportional to v
DS.
The device behaves as a resistor whose value depends on v
GS.
Figure: As v
DS
increases, the channel pinches down at the drain end and i
D
increases more slowly.
Finally for v
DS
> v
GS
-V
to
, i
D
becomes constant.
Current-Voltage Relationship of
n-EMOSFET
Locus of points where
Figure: Drain characteristics
Figure: This circuit can be used to plot drain characteristics.
Figure: Diodes protect the oxide layer from destruction by static electric charge.
Figure: Simple NMOS amplifier circuit and Characteristics with load line.
Figure: Drain characteristics and load line
Figure v
DS
versus time for the circuit of Figure 5.13.
Figure Fixed- plus self-bias circuit.
Figure Graphical solution of Equations (5.17) and (5.18).
Figure Fixed- plus self-biased circuit of Example 5.3.
Figure The more nearly horizontal bias line results in less change in the Q-point.
Figure Small-signal equivalent circuit for FETs.
Figure FET small-signal equivalent circuit that accounts for the dependence of i
D
on v
DS
.
Figure Determination of g
m
and r
d
. See Example 5.5.
Figure Common-source amplifier.
For drawing an a c equivalent circuit of Amp.
Assume all Capacitors C1, C2, Cs as short
circuit elements for ac signal
Short circuit the d c supply
Replace the FET by its small signal model
Analysis of CS Amplifier
L gs m L o o
gs
o
v
R v g R i v
v
v
A
= =
= gain, Voltage
d D L L m
gs
o
v
r R R R g
v
v
A = = = ,
D d
D d
D d o
R r
R r
R r Z
+
= = imp., put Out
2 1
imp., Input R R R Z
G in
= =
A C Equivalent Circuit
Simplified A C Equivalent Circuit
Analysis of CS Amplifier with Potential Divider Bias
) R || (r g Av D d m =
D
R 10 r D, m
d
R g Av > ~
) R || (r g Av D d m =
This is a CS amplifier configuration therefore the
input is on the gate and the output is on the drain.
2 1 R || R Zi =
D d R || r Zo=
D d
D
10R r
R Zo
>
~
Figure v
o
(t) and v
in
(t) versus time for the common-source amplifier of Figure 5.28.
Figure Common-source amplifier.
An Amplifier Circuit using MOSFET(CS Amp.)
Figure Small-signal equivalent circuit for the common-source amplifier.
A small signal equivalent circuit of CS Amp.
Figure v
o
(t) and v
in
(t) versus time for the common-source amplifier of Figure 5.28.
Figure Gain magnitude versus frequency for the common-source amplifier of Figure 5.28.
Figure Source follower.
Figure Small-signal ac equivalent circuit for the source follower.
Figure Equivalent circuit used to find the output resistance of the source follower.
Figure Common-gate amplifier.
Figure See Exercise 5.12.
Figure Drain current versus drain-to-source voltage for zero gate-to-source voltage.
Figure n-Channel depletion MOSFET.
Figure Characteristic curves for an NMOS transistor.
Figure Drain current versus v
GS
in the saturation region for n-channel devices.
Figure p-Channel FET circuit symbols. These are the same as the circuit symbols for n-channel devices,
except for the directions of the arrowheads.
Figure Drain current versus v
GS
for several types of FETs. i
D
is referenced into the drain terminal
for n-channel devices and out of the drain for p-channel devices.